Polynomial circuit models for component matching in high-levelsynthesis

Design reuse requires engineers to determine whether or not an existing block implements desired functionality. If a common high-level circuit model is used to represent components that are described at multiple levels of abstraction, comparisons between circuit specifications and a library of potential implementations can be performed accurately and quickly. A mechanism is presented for compactly specifying circuit functionality as polynomials at the word level. Polynomials can be used to represent circuits that are described at the bit level or arithmetically. Furthermore, in representing components as polynomials, differences in precision between potential implementations can be detected and quantified. We present a mechanism for constructing polynomial models for combinational and sequential circuits. Furthermore, we derive a means of approximating the functionality of nonpolynomial functions and determining a bound on the error of this approximation. These methods have been implemented in the POLYSYS synthesis tool and used to synthesize a JPEG encode block and infinite impulse response filter from a library of complex elements     

Stochastic context-free grammars and hidden Markov models for modeling of bursty channels

In order to design good error-control schemes for bursty channels and also to facilitate performance analysis, it is important to develop accurate and simple statistical channel error models for the channels of interest. We propose two novel generative methods to model the end-to-end error profile of radio channels described by long well-defined error bursts interleaved with long error-free intervals. The first method makes use of the power of stochastic context-free grammars to model palindromes. The second utilizes simple hidden Markov models with specific structures, which are suggested by the ideas presented in the first method. Both methods achieve much better performance than previously proposed approaches without introducing more complexity. Although the complexity of the second method is slightly greater than that of the first, its advantage is that it can be easily applied in decoding implementations specifically tailored to deal with bursty channels.     

Modeling of high error rate binary communication channels (Corresp.)

Most of the existing mathematical models for binary communication channels describe low error rate wire lines satisfactorily. For typical high error rate channels, like the ultrahigh frequency (UHF) or very high frequency (VHF) wideband data channel encountered in military uses, finite-state as well as denumerable infinite state Markov chain models do not achieve an accurate characterization. The above models, including some more recent compound models, are compared against data from the actual channel using the multigap distribution as a tool. A modification of a compound model is shown that allows more accurate modeling of a wider class of channels including the high error rate radio channel.     

Supporting Multiple Consistency Models within a Mobility Enabled File System Using a Component Based Framework

Most existing Distributed File Systems (DFSs) implement a single consistency model to maintain one-copy equivalence. The functionality of that consistency model is based on a balance between environmental constraints and the targeted level of consistency. Such systems efficiently maintain consistency while the environmental capabilities remain constant, e.g., presuming uninterrupted connectivity. However, when these characteristics change, the inflexible nature of a single consistency model results in its inability to maintain an expected balance between consistency and constraints. This illustrated with existing implementations of DFSs. GLOMAR is a DFS middleware layer that allows application developers to map their specific consistency models to environmental constraints. As a result, multiple consistency models can be created, with each scoped for a particular application and environmental scenario. This paper outlines important aspects of GLOMAR, detailing its implementation and outlining a number of consistency models.     

Accurate Area,Time and Power Models for FPGA-Based Implementations

This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family (Deng et al. 2008). These models are designed to facilitate efficient design space exploration in an automated algorithm-architecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18×18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption. The proposed models have also been integrated into a hardware-software partitioning tool to facilitate design space exploration under area and time constraints.     

An order downdating algorithm for tracking system order andparameters in recursive least squares identification

A new time and order recursive method for on-line tracking of system order and parameters using recursive least squares (RLS) is presented. The method consists of two parts: a time updating portion that uses existing RLS inverse QR decomposition algorithms and a new computationally efficient “order downdating” portion that calculates the model parameters and residual error energies for an entire set of models with order varying from one to some prespecified maximum model order     

Testability of artificial neural networks: A behavioral approach

Testability analysis of neural architectures can be performed at a very high abstraction level on the computational paradigm. In this paper, we consider the case of feed-forward multi-layered neural networks. We introduce a behavioral error model which allows good mapping of the physical faults in widely different implementations. Conditions for error controllability, observability and global testability are analytically derived; their purpose is that of verifying whether it is possible to excite all modeled errors and to propagate the error's effects to the primary outputs (actual test vectors being then technological-dependent). Mapping of physical faults onto behavioral errors is performed for some representative, architectures.     

Evaluation of a data communication model for switched fibre channel

The ANSI standard fibre channel is emerging as the networking protocol of choice for high bandwidth applications. Fibre channel is an enabling technology because of the tremendous advantages in speed and latency it provides over existing networking technologies. Applications that weren't feasible before are now possible, and more applications that demand similar performance will follow. Fibre channel is the high performance alternative to existing networking technologies such as FDDI, Fast Ethernet, and ATM. Fibre channel (FC) provides for two different data communication models: connection (class 1 service) and connectionless (class 2 or 3 service). Although interoperable, some of these implementations may not result in optimal performance. There is some disagreement in the FC community as to which is more appropriate. Both have their advantages and disadvantages, and so it's necessary to look at each application individually. The article addresses some of these issues by simulating these two communication models over different switch architectures     

电子战软件中组件式定时器的开发与应用

对现有的定时器模型进行了分析,分别指出了其中存在的问题,并给出了解决方案。通过组件式软件开发技术,将基于线程的定时器封装成组件,隐藏了复杂的内部实现细节,使设计人员可以更多地关注业务领域模型,提高整个软件开发团队的效率,减少软件出错,提高软件品质。     

Cascade SD modulator for low-voltage wideband applications

A new cascade SigmaDelta modulator architecture with unity signal transfer function is presented which avoids the need for digital filtering in the error cancellation logic. The combination of these two aspects makes it highly tolerant to noise leakages, very robust to nonlinearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioural simulations are presented that demonstrate the higher efficiency of the proposed topology compared to existing cascades intended for wideband applications.     

椭圆曲线密码的芯片集成

椭圆曲线密码(ECC)是一种非常复杂的数学算法,设计出能够完整实现ECC算法的专用集成电路芯片(ASIC)非常困难.当前,对ECC的研究主要集中在ECC的实现方面,其中,尤其是ECC的芯片集成引入关注.为此文章在总结已有ECC芯片实现情况的基础上,介绍了清华大学微电子学研究所在ECC芯片实现方面所做的工作.     

Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs

This paper studies the implementation of Double Error Correction Orthogonal Latin Squares (OLS) in Xilinx Field Programmable Gate Arrays (FPGAs). Several existing options to implement the decoder are considered and evaluated. The results show that the decoder complexity can be significantly optimized by appropriately selecting the implementation that is better suited to the internal FPGA structure. A new implementation tailored for the FPGA structure is proposed, which has a more efficient physical resource utilization compared with the existing ones. It is shown that the improvement on resource utilization is also highly correlated with the soft error vulnerability. The proposed decoder scheme has a reduced soft error cross section compared with other implementations. Based on these results, it seems that optimizing the ECC implementation for FPGAs can be effective and may be useful for other codes.     

Design and Performance of PRAN: A System for Physical Implementation of Ad Hoc Network Routing Protocols

Simulation and physical implementation are both valuable tools in evaluating ad hoc network routing protocols, but neither alone is sufficient. In this paper, we present the design and performance of PRAN, a new system for the physical implementation of ad hoc network routing protocols that unifies these two types of evaluation methodologies. PRAN (physical realization of ad hoc networks) allows existing simulation models of ad hoc network routing protocols to be used - without modification - to create a physical implementation of the same protocol. We have evaluated the simplicity and portability of our approach across multiple protocols and multiple operating systems through example implementations in PRAN of the DSR and AODV routing protocols in FreeBSD and Linux using the standard existing, unmodified ns-2 simulation model of each. We illustrate the ability of the resulting protocol implementations to handle real, demanding applications by describing a demonstration with this DSR implementation transmitting real-time video streams over a multihop mobile ad hoc network; the demonstration features mobile robots being remotely operated based on the real-time video stream transmitted from the robot over the network. We also present a detailed performance evaluation of PRAN to show the feasibility of our architecture     

Weighted sum codes for error detection and their comparison withexisting codes

Describes a new family of error detection codes called weighted sum codes. These codes are preferred over four existing codes (CRC, Fletcher checksum, Internet checksum, and XTP CXOR), because they combine powerful error detection properties (as good as the CRC) with attractive implementation properties. One variant, WSC-1, has efficient software and hardware implementations; while a second variant, WSC-2, is almost as efficient in software (still significantly better than CRC) and offers commutative processing (that enables efficient out-of-order, parallel, and incremental update processing)     

Rain attenuation model for south east asia countries

A model for predicting rain attenuation on Earth-to-space is developed by using the measured data obtained from tropical and equatorial regions that was revised from the ITU model. The proposed rain attenuation model uses the complete rainfall rate cumulative distribution as input data. It is shown that significant improvements in terms of prediction error over existing attenuation models are obtained     

一种新的无线传感器节点的连续参数功耗模型

为了估计传感器节点的能量开销,需要对节点功耗进行合理、准确的建模。然而,现有的节点功耗模型都没有很好地满足准确性这一要求。该文提出了一种新的基于连续参数功耗状态机的节点功耗模型,可用于任意类型传感器节点的功耗建模。该模型能够根据电源电压和工作频率等参数的变化对节点功耗进行更为准确的预测。通过对传感器节点中常用的ATmega128(L)微处理器进行实际建模并与独立的实测结果进行比较,可以发现该模型对活动状态功耗的预测误差小于1%,对空闲状态功耗的预测误差小于9.7%。该模型可用于替换传感器网络仿真工具的现有模型,为传感器节点的能量开销提供更为准确的预测结果。     

Robust image deblurring with an inaccurate blur kernel

Most existing nonblind image deblurring methods assume that the blur kernel is free of error. However, it is often unavoidable in practice that the input blur kernel is erroneous to some extent. Sometimes, the error could be severe, e.g., for images degraded by nonuniform motion blurring. When an inaccurate blur kernel is used as the input, significant distortions will appear in the image recovered by existing methods. In this paper, we present a novel convex minimization model that explicitly takes account of error in the blur kernel. The resulting minimization problem can be efficiently solved by the so-called accelerated proximal gradient method. In addition, a new boundary extension scheme is incorporated in the proposed model to further improve the results. The experiments on both synthesized and real images showed the efficiency and robustness of our algorithm to both the image noise and the model error in the blur kernel.     

IPv6邻居发现协议的一致性测试序列生成

自1998年互联网工程任务组(IETF)提出下一代互联网标准规范以来,IPv6已经历了十多年的发展。现今已有越来越多的IPv6产品被投入到了开发与应用中。而如何提高不同产品间的互通性和可靠性则成为了一个关键问题。进行协议一致性测试是提高IPv6实现可靠性的一种有效方式。本文就重点针对IPv6邻居发现协议进行了一致性测试分析。本文首先简要分析了IPv6邻居发现协议的主要功能及实现原理,并据此抽象出其有限状态机（FSM）模型。进而结合一种现有基于有限状态机(FSM)的一致性测试序列改进算法生成了该协议的抽象测试序列。本文在最后对得到的测试序列进行了有效性和可靠性分析,分析表明,使用该算法得到的测试序列不仅在序列长度上较传统UIO序列法有了明显的缩短,同时对测试过程中可能发生的输出错误及末状态转换错误也具备良好的检测能力。本文获得的抽象测试序列可对相关IPv6协议开发者提供有效参考。      

Direct blind MMSE channel equalization based on second-orderstatistics

A family of new MMSE blind channel equalization algorithms based on second-order statistics are proposed. Instead of estimating the channel impulse response, we directly estimate the cross-correlation function needed in Wiener-Hopf filters. We develop several different schemes to estimate the cross-correlation vector, with which different Wiener filters are derived according to minimum mean square error (MMSE). Unlike many known sub-space methods, these equalization algorithms do not rely on signal and noise subspace separation and are consequently more robust to channel order estimation errors. Their implementation requires no adjustment for either single- or multiple-user systems. They can effectively equalize single-input multiple-output (SIMO) systems and can reduce the multiple-input multiple-output (MIMO) systems into a memoryless signal mixing system for source separation. The implementations of these algorithms on SIMO system are given, and simulation examples are provided to demonstrate their superior performance over some existing algorithms     

Flexible spectrum and future business models for the mobile industry

The concept of flexible spectrum is often considered as a medium-to-long-term solution to overcome some of the current inefficiencies and high entry barriers plaguing the mobile industry. Increasingly, a cognitive pilot channel (CPC) is regarded as a central enabler for flexible spectrum. This paper outlines the CPC concept from a business point of view and clarifies its current status in the standardization and regulation fields. The idea of a worldwide CPC will be under consideration by the World Radio Conference in 2011. Based on several potential CPC implementations, the paper identifies a number of flexible spectrum business configurations and revenue sharing models. It also performs an initial forward-looking evaluation of these models using a business model scorecard approach, and finds that while the scope appears to be limited for a fully competitive, cross-operator spectrum market, several platform models (e.g. association or consortium models) stand out as feasible options.