A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

A 300-/spl mu/W 1.9-GHz CMOS oscillator utilizing micromachined resonators

A low-power low-phase-noise 1.9-GHz RF oscillator is presented. The oscillator employs a single thin-film bulk acoustic wave resonator and was implemented in a standard 0.18-/spl mu/m CMOS process. This paper addresses design issues involved in codesigning micromachined resonators with CMOS circuitry to realize ultralow-power RF transceiver components. The oscillator achieves a phase-noise performance of -100 dBc/Hz at 10-kHz offset, -120 dBc/Hz at 100-kHz offset, and -140 dBc/Hz at 1-MHz offset. The startup time of the oscillator is less than 1 /spl mu/s. The oscillator core consumes 300 /spl mu/A from a 1-V supply.     

A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS

We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost, and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a baseband processor, such as SoC, in a GPS receiver. The GPS chip, with a total size of 6.3 mm /spl times/ 6.3 mm, contains a 2.3 mm /spl times/ 2.0 mm radio part, including RF front end, phase-locked loops, IF functions, and 500 K gates of baseband logic, including mask ROM, SRAM, and dual port SRAM . It is fabricated using 0.18-/spl mu/m CMOS technology with a MIM capacitor and operates from a 1.6-2.0-V power supply. Experimental results show a very low power consumption of, typically, 57 mW for a fully functional chip including baseband, and a high sensitivity of -152dBm. Through countermeasures against substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external low-noise amplifier.     

On the feasibility of CMOS multiband phase shifters for multiple-antenna transmitters

We present the design of an integrated multiband phase shifter in RF CMOS technology for phased array transmitters. The phase shifter has an embedded classical distributed amplifier for loss compensation. The phase shifter achieves a more than 180/spl deg/ phase tuning range in a 2.4-GHz band and a measured more than 360/spl deg/ phase tuning range in both 3.5-GHz and 5.8-GHz bands. The return loss is less than -10dB at all conditions. The feasibility for transmitter applications is verified through measurements. The output power at a 1-dB compression point (P/sub 1 dB/) is as high as 0.4dBmat 2.4GHz. The relative phase deviation around P/sub 1 dB/ is less than 3/spl deg/. The design is implemented in 0.18-/spl mu/mRF CMOS technology, and the chip size is 1200/spl mu/m /spl times/ 2300 /spl mu/m including pads.     

Saddle add-on metallization for RF-IC technology

A cost-effective add-on process module for reducing ohmic losses of radio-frequency (RF) inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on CMOS logic processes is proposed. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects through copper (Cu) electroplating in selected areas. The combination of dense Cu-interconnects in the CMOS logic sections, of thick Cu top-level wiring through local Cu electroplating in the RF sections, and of aluminum (Al) capping of the bond pads provides an optimum tradeoff between packaging requirements, quality of passive components and interconnects, and cost. A special wet-etch process sequence for removal of the Cu-seed and adhesion films from the exposed top metal layer is described. A record quality factor of /spl sim/13 for a 10-nH inductor on a conventional 5-/spl Omega/-cm silicon substrate is demonstrated.     

A wide-band T/R switch using enhanced compact Waffle MOSFETs

A wide-band complementary metal oxide semiconductor (CMOS)transmit/receive (T/R) switch using enhanced compact waffle metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. The compact waffle layout configuration saves much active area to give a low on-resistance. Furthermore,the low drain-to-substrate capacitance (CDB) in waffle MOSFETs can help reduce high frequency substrate coupling and substrate loss for CMOS radio frequency (RF)/microwave integrated circuits (ICs). A 2-dB higher maximum stable gain/maximum available gain (MSG/MAG)and a 2-GHz higher f/sub max/ are obtained compared with those of conventional multifinger MOSFETs. The CMOST/R switch implemented in a standard 0.35-/spl mu/m CMOS technology gives a low insertion loss of 1.7dB,high isolation of more than 40dB, larger than 15-dB return loss, 7-dBm P/sub 1 dB/ and 13-dBm input IP3 at 900MHz with a 3-V supply voltage. The switch maintains a wide-band performance up to 2.4GHz with only a slight deterioration.     

Small-signal substrate resistance effect in RF CMOS cascode amplifier

With common-source RF application amplifier, it is well known that the small substrate resistance helps to improve the output resistance as well as the transconductance. This idea can be easily extended to all CMOS transistors in RF applications. However, with cascode amplifier at high frequencies, the maximum available gain, noise figure minimum, and the tuned output impedance are improved by increasing the substrate resistance of the common-gate transistor, so that the range of operational frequency can be extended. These contradicting phenomenons between the common-source and common-gate topology can be explained theoretically, and the supporting measurement results are presented base on a 0.35 /spl mu/m CMOS technology.     

A 0.18-/spl mu/m RF SiGe BiCMOS technology with collector-epi-free double-poly self-aligned HBTs

This paper describes an RF SiGe BiCMOS technology based on a standard 0.18-/spl mu/m CMOS process. This technology has the following key points: 1) A double-poly self-aligned SiGe-HBT is produced by adding a four-mask process to the CMOS process flow-this HBT has an SiGe epitaxial base selectively grown on an epi-free collector; 2) two-step annealing of CMOS source/drain/gate activation is utilized to solve the thermal budget tradeoff between SiGe-HBTs and CMOS; and 3) a robust Ge profile design is studied to improve the thermal stability of the SiGe-base/Si-collector junction. This process yields 73-GHz f/sub T/, 61-GHz f/sub max/ SiGe HBTs without compromising 0.18-/spl mu/m p/sup +//n/sup +/ dual-gate CMOS characteristics.     

RF MEMS switch integrated on printed circuit board with metallic membrane first sequence and transferring

This letter reports, for the first time, on RF MEMS switches integrated on flexible printed circuit boards (i.e., FR-4) using transfer technology. The devices were first processed on Si-substrate using a modified MEMS sequence and subsequently transferred onto an FR-4 substrate by thermal compressive bonding, mechanical grinding, and wet removal of silicon. The switches were demonstrated with flat metal membrane (top electrode), precisely controlled gap between the membrane and bottom electrode, low insertion loss (/spl les/ 0.15 dB at 20 GHz), and high isolation (/spl sim/ 21 dB at 20 GHz). This technology shows the potential to monolithically integrate RF MEMS components with other RF devices on organic substrate for RF system implementation.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

An enhanced fully scaled 1.2-/spl mu/m CMOS process for analog

An n-well CMOS technology has been developed for high-speed/precision 10-V analog operation while retaining VLSI packaging densities and performance. Several enhancements to a fully scaled 1.2-/spl mu/m CMOS process were made to attain performance levels necessary for state-of-the-art data-conversion applications. The technology incorporates components essential for analog circuit design such as high-gain/low-noise n-p-n BJTs, laser trimmable Cr-Si resistors, and extremely accurate interpoly oxide capacitors. Inclusion of an optimized LDD structure on n-channel transistors has permitted 10-V CMOS capabilities down to 2.5-/spl mu/m drawn gate lengths.     

Highly effective junction isolation structures for PICs based on standard CMOS Process

This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-/spl mu/m CMOS technology.     

A miniaturized Wilkinson power divider with CMOS active inductors

A miniaturized Wilkinson power divider implemented in a standard 0.18-/spl mu/m CMOS process is presented in this letter. By using active inductors for the circuit implementation, a significant area reduction can be achieved due to the absence of distributed components and spiral inductors. The power divider is designed at a center frequency of 4.5GHz for equal power dividing with all ports matched to 50/spl Omega/. Drawing a dc current of 9.3mA from a 1.8-V supply voltage, the fabricated circuit exhibits an insertion loss less than 0.16dB and a return loss better than 30dB at the center frequency while maintaining good isolation between the output ports. The active area of the miniaturized Wilkinson power divider is 150/spl times/100/spl mu/m/sup 2/, which is suitable for system integration in monolithic microwave integrated circuit (MMIC) applications.     

Fully integrated wideband high-current rectifiers for inductively powered devices

This paper describes the design and implementation of fully integrated rectifiers in BiCMOS and standard CMOS technologies for rectifying an externally generated RF carrier signal in inductively powered wireless devices, such as biomedical implants, radio-frequency identification (RFID) tags, and smartcards to generate an on-chip dc supply. Various full-wave rectifier topologies and low-power circuit design techniques are employed to decrease substrate leakage current and parasitic components, reduce the possibility of latch-up, and improve power transmission efficiency and high-frequency performance of the rectifier block. These circuits are used in wireless neural stimulating microsystems, fabricated in two processes: the University of Michigan's 3-/spl mu/m 1M/2P N-epi BiCMOS, and the AMI 1.5-/spl mu/m 2M/2P N-well standard CMOS. The rectifier areas are 0.12-0.48 mm/sup 2/ in the above processes and they are capable of delivering >25mW from a receiver coil to the implant circuitry. The performance of these integrated rectifiers has been tested and compared, using carrier signals in 0.1-10-MHz range.     

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).     

Monolithic digital galvanic isolation buffer fabricated in silicon on sapphire CMOS

A monolithic four-channel digital galvanic isolation buffer in the 0.5 /spl mu/m silicon on sapphire (SOS) CMOS technology is reported. Advantage is taken of the insulating properties of the sapphire substrate to integrate on the same die both the isolation structure and the interface electronics. Each isolation channel has been tested to operate at data rates over 100 Mbit/s. The system can tolerate ground bounces of 1 V//spl mu/s and is tested for 800 V isolation. The system includes an integrated isolation charge pump to power the input circuit and is hence capable of operating from a single 3.3 V power supply.     

Crosstalk suppression in mixed-mode ICs by the /spl pi/ technology and the future with an SOC integration platform: particle-beam stand (PBS)

A /spl pi/ technology (particle-enhanced isolation, PEI) is proposed to employ penetrating proton beams on the already manufactured mixed-mode (analog-digital) IC wafers (prior to packaging) for the suppression of undesirable substrate coupling. Results indicated that an improvement of 25-30 dB could be achieved by applying a relatively low-fluence proton bombardment on the isolation-intended region in a metal pads pattern. Hall measurements of the irradiated spots were conducted and the associated physics are elaborated on. Issues relevant to the commercial-scale implementation of this technology are also pointed out and discussed. Finally, a /spl pi/-technology-based post-very large scale integration (VLSI) concept: the "particle-beam stand" (PBS) is promoted, which, especially with its design rules pushed to the front end, can potentially serve as the general system-on-a-chip (SOC) integration platform and end most mixed-mode and RF SOC development difficulties.     

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.     

A 10-bit wide-band CMOS direct digital RF amplitude modulator

This paper describes a low-distortion wide-band CMOS direct digital RF amplitude modulator, which uses a 10-bit linear interpolation current-steering digital-to-analog converter (DAC) and a Gilbert-cell-based mixer to generate an amplitude modulated RF signal directly. The linear interpolation increases the attenuation of the DAC's image components. The reconstruction filter is, therefore, eliminated. The DAC's differential current signals are directly sent to the mixer, which improves the linearity of the modulated RF signal. Thus, the RF transmitter structure is simplified, and the low distortion is achieved. This modulator is suitable for system-on-chip (SOC) design and is easily scalable. The chip was fabricated in a 0.35-/spl mu/m 3.3-V double-poly triple-metal CMOS process. The core size of the chip is 0.52 mm/spl times/0.68 mm. With a 3.3-MHz modulation signal, a 50-MHz clock, and a 1-GHz carrier, the distortion components are below -53.81 dBc, and the attenuation of the image signal is 47.45 dB. The output power is -6.5 dBm, and the total power consumption is 159.8 mW.     

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.