一种彩色形态塔式结构方法

本文提出了彩色图像的彩色形态采样,得到了彩色图像多分辨率表示的新方法,即彩色形态塔式结构。基于RGB（红绿蓝）彩色坐标系统上的彩色形态变换,讨论了彩色形态采样与其两种彩色形态重建,即彩色形态膨胀重建与彩色形态闭重建,提出了相应的彩色图像分析与合成方法,并给出了彩色形态采样与彩色形态塔式结构的实验结果。     

生成式双波段彩色融合图像质量评价

为了解决融合图像数据量有限的问题,提出了一种生成式双波段彩色融合图像质量评价方法。该方法基于对抗生成网络生成伪彩色融合图像,在训练过程中考虑了结构的不相似性,为伪彩色融合图像加入不同程度的无序变量生成新的数据集。使用孪生网络在伪彩色融合图像数据集中进行预训练,在真彩色融合图像数据集中进行微调,对彩色融合图像质量进行评价。实验结果表明,生成式双波段彩色融合图像质量评价方法的计算结果与人眼主观感受具有较高的一致性,可以有效地对彩色融合图像进行客观评价。     

彩色全息显示方法与系统概述

彩色全息显示是全息视频显示技术发展的重要目标。概述了基于空间光调制器实现彩色全息显示的方法与系统构建问题。首先,介绍了彩色全息显示中三个单色全息像叠加生成彩色全息再现像的基本原理。分析了全息图生成的方法,比较了光全息图、数字全息图、计算机生成全息图的不同。其次,讨论了彩色全息显示系统构建时空间光调制器的选择以及多波长照明下的相位调制特性问题。在实际系统中,红、绿、蓝三色激光或者发光二极管都可以用作系统照明光源。然后,描述了基于时分复用、空间复用、空间划分、空间叠加方法构建的彩色全息显示系统架构,指出彩色全息重构结果受到空间光调制器像素结构和色差等问题的影响。最后,展望了彩色全息显示技术的发展方向。     

基于衍射成像的荧光图像伪彩色自动融合研究

为了提高荧光图像的高分辨融合能力,提出基于衍射成像的荧光图像伪彩色自动融合方法。构建荧光衍射图像的伪彩色特征分割模型,采用边缘区域信息融合方法进行荧光图像伪彩色特征检测与识别,采用联合结构相似性特征提取方法进行荧光图像的边缘轮廓检测,建立荧光衍射图像的轮廓曲线演化分割模型,采用边缘模糊度特征提取方法进行荧光衍射图像的轮廓模型检测,根据图像的区域信息进行边缘梯度信息分割,构建荧光图像伪彩色径向纹理特征模型,采用衍射成像和荧光图像伪彩色表观模型重建的方法,实现荧光图像伪彩色自动融合。仿真结果表明,采用该方法进行荧光图像伪彩色融合的特征分辨能力较好,输出信噪比较高,提高了荧光图像伪彩色自动融合和检测能力。     

彩色夜视技术方法综述

为了得到具有自然彩色的夜视图像, 彩色夜视技术的研究成为夜视技术研究领域的一大热点。介绍了夜视技术的发展概况和获得具有自然感彩色夜视图像的彩色夜视技术手段, 主要可分为硬件方式和软件合成的方式, 其中软件方式主要有基于多传感器图像融合的方法和基于色彩传递的方法。详细介绍了两种方式的技术方案, 并对彩色夜视技术做出了技术展望。     

基于HSL空间的彩色形态变换

彩色形态变换是数字形态从灰度图象到彩色图象的推广。该文基于HSL（hue-saturation-lightness)彩色空间，提出了彩色形态变换理论，定义了新的彩色形态算子，并讨论了它们的性质。彩色形态变换作为一种数学形态学方法在彩色空间的延拓，可有效地应用于图象处理、图象编码和目标形状特征提取等。     

灰度图像彩色化的效果评价研究

灰度图像彩色化的效果评价是目前图像彩色融合和增强急需解决的问题之一。从彩色化图像与原灰度图像比较和彩色化图像之间比较两方面对灰度图像的彩色化效果评价进行研究,提出了相应的主观评价方法和客观评价参数。     

彩色数字全息检测的实时无颜色串扰采集技术研究

提出一种基于Foveon CCD的实时无颜色串扰的彩色数字全息干涉计量方法。针对当前实时彩色数字全息图中存在颜色串扰的问题,分析了Foveon CCD的工作原理与控制模式,对变换颜色矩阵消除颜色串扰方法作了相应的分析,提出通过改变CCD的颜色变换矩阵的方法,可以有效降低了颜色串扰对彩色数字全息的影响。实验结果及实验数据表明,一定条件下,通过该方法能实现实时无颜色串扰彩色数字全息图采集,对彩色数字全息实时检测有一定的应用价值。     

电视彩色校正的一种方法

彩色校正是一种重要的视频处理手段,本文介绍了一种不用价格昂贵的专用彩色校正器,而用常规电视设备实现后期彩色校正的方法。     

基于不平度颜色混合的图像彩色化方法

黑白图像的彩色化是图像处理领域一个活跃的、有挑战性的研究课题。该文在总结图像彩色化方法的基础上,提出了一种新型的、基于不平度的颜色混合方法。实验表明,该方法能够大大简化对初始着色的要求,并且达到很好的彩色化效果。     

The two-dimensional scanned reservoir for the multilayer gas-discharge panel

A two-dimensional scanning reservoir with open cathode segments that service more than a single display cell has been developed. This correspondence describes the principles of the scanning reservoir for the multilayer gas-discharge display panel which results in simplified addressing and a reduced number of drive circuits.     

Temperature effects on BTI and soft errors in modern logic circuits

Since thermal responses of the drive current in recent 3D FinFET and conventional planar transistors are different, addressing performance and reliability in advanced VLSI circuits must be reconsidered. This study investigates temperature effects on two of the most problematic reliability issues in modern logic circuits, namely Bias Temperature Instability (BTI) and soft errors. In particular, we initially examine the inversion of temperature effect that strengthens the drive current in 14-nm bulk tri-gate FinFETs with increasing temperature, and model it as a source of threshold voltage reduction. This temperature-induced threshold voltage variation is consequently adapted into our proposed simulation and analysis framework for BTI degradation in large combinational circuits. The BTI aging results from our proposed estimation are more pessimistic than that from the conventional approach where the temperature effect is excluded. Simulation results show that long-term BTI aging delay worsens as temperature increases, yet the domination of thermal effect on the drive current leads to overall performance improvement in all circuits under 10-year BTI stress. In addition, soft errors and their masking probabilities in logic circuits are addressed under the inversion of temperature effect and supply voltage variation. The results reveal that soft error immunity in all experimental circuits improves significantly with increasing supply voltage and temperature, mainly due to the increase of critical charge. The average relative soft error rate when the supply voltage changes from 0.4 V to 0.6 V and 0.8 V at 0 °C is as low as 3.7% and 0.08% of the average result at 0.4 V, respectively. On average, the relative soft error rate at a particular supply voltage when temperature changes from 0 °C to 40 °C, 80 °C, and 120 °C is around 70%, 50%, and 30% of the average result at 0 °C, respectively.     

LED智能显示屏的结构及驱动,显示电路原理

介绍了ＬＥＤ智能显示屏的结构、驱动与显示电路的组成，对该电路的原理进行了详尽的分析。实践证明：该驱动与显示电路逻辑可靠，实用．     

混合封装电力电子集成模块内功率电路对驱动保护电路的热影响

混合封装电力电子集成模块(IPEM)是目前中功率范围内电力电子集成的主要方式。IGBT器件与控制和驱动电路高密度地封装在一起,IGBT的发热对驱动保护电路会产生非常不利的影响,我们针对这个问题进行了研究。利用三维有限元法建立了模块内的传热模型,对不同发热功率下IGBT的结温以及驱动保护电路PCB的最高温度进行了计算和分析。另外,对功率电路与驱动保护电路PCB之间存在空气隙以及模块完全被密封后模块内的传热问题也进行了实验研究。     

Coreless printed circuit board (PCB) transformers with multiplesecondary windings for complementary gate drive circuits

This paper describes the modeling and implementation of a coreless printed circuit board (PCB)-based transformer with “multiple” secondary outputs. This new PCB transformer has been successfully applied in complementary gate drive circuits in a novel low-profile power converter with high-power density and a converter bridge. The PCB-based transformers do not require the manual winding procedure and thus simplify the manufacturing process of transformer-isolated gate drive circuits. The use of the multiple secondary outputs can in principle simplify the complementary gate drive circuits that are often required in many power electronics applications     

IR2110驱动电路的优化设计

介绍IR2110驱动模块的特点．针对其存在的一些不足．给出相关解决方案。设计相应的优化驱动电路,较好地改善IR2110的驱动和保护性能,增强其实用性。     

A new method to reduce addressing time in a large AC plasma displaypanel

To replace the dual scan system by single scan in large ac plasma display panel (PDP), the addressing time should be reduced by modifying cell structure and/or driving circuits. Moreover, the luminance of the PDP can also be increased with the decrease in the addressing time. In this paper, we suggest the bus and address electrodes with triangular protruding tips in order to reduce the addressing time. Moreover, the addressing time of the ac PDP with these electrodes was investigated experimentally with address and display period separated (ADS) driving method. The experimental results show that the addressing time can be reduced more than 30% compared with the conventional type by modifying the electrodes without reducing the luminance of the PDP     

液晶投影系统的显示驱动电路

液晶投影系统的显示驱动电路分为取样/保持式驱动电路和锁存式驱动电路两种,本文介绍了这两种类型的典型驱动电路并对它们进行了比较.比较表明,锁存式驱动电路具有较高的优越性.     

Effect of Gate-Drive Circuits on GTO Thyristor Characteristics

This paper deals with the effects of gate drive circuits on turn-on and turn-off characteristics of GTO thyristors. The turn-on methods are outlined and their effects on switching performance are discussed. The turn-off characteristics and the failure modes associated with the storage, fall, tailing, and avalanche periods are presented. Solutions to failure modes are outlined. Both direct and indirect gate drive circuits are presented. The effects of ideal voltage source and series insertion of gate inductance to storage, fall, tailing, and avalanche breakdown period of the GTO thyristors are studied and compared. The suitability of using certain types of gate drive circuits for certain GTO thyristors is discussed.     

N+多晶硅栅薄膜全耗尽SOI CMOS器件与电路的研究

选用SIMOX(Separation by Implantation of Oxygen)衬底材料,对全耗尽SOI CMOS工艺进行了研究,开发出了N 多晶硅栅全耗尽SOI CMOS器件及电路工艺,获得了性能良好的器件和电路。nMOS和pMOS的驱动电流都比较大,且泄漏电流很小,在工作电压为3V时,1．2μm101级环振的单级延迟仅为50．5ps。