Self-aligned p-channel MISFET with a low-temperature-grown GaAsgate insulator

A new p-channel GaAs metal-insulator-semiconductor field-effect transistor (MISFET) using low-temperature-grown (LTG) GaAs as the gate insulator is demonstrated. Neither the GaAs conducting channel nor the gate insulator was doped, and a Be self-aligned implant was used to lower the source and drain series resistance. For a MISFET with a 1.5-μm gate length, the transconductance is 22 mS/mm and the maximum drain current is 120 mA/mm obtained at -8 V of gate bias. The measured unity-current-gain cut-off frequency f_T is 2.0 GHz     

Single transistor MOS RAM using a short-channel MOS transistor

The relationship between sensitivity and other factors in the sense circuit of a single transistor MOS RAM has been investigated by computer simulation. An expression for sensitivity of the sense circuit has been derived. It suggests key points to increase the sensitivity of the sense circuit. A new sense circuit that defects a signal less than /spl plusmn/30 mV and has low power capability 50 /spl mu/W/circuit is realized by following the suggestions. The high performance of the proposed sense circuit has been verified through the fabrication of a 1K MOS RAM. Fine pattern technology, such as 2-/spl mu/m minimum pattern width and spacing and 500-/spl Aring/ gate oxide thickness, has been adopted. The threshold voltage of the MOS transistor is 0.8 V and dc supplies are 7 V and /spl plusmn/2 V. This 1K RAM has characteristics of 80-ns access time, 150-ns cycle time, and 30-mW power dissipation.     

Self-aligned transistor with sidewall base electrode

A multiple self-aligned structure that facilitates high packing density and high speed in bipolar VLSI's is proposed. The device has polysilicon sidewall base electrodes to reduce parasitic junction capacitances. The new devices indicate that capacitances between the base and collector regions are reduced to 14 and the ratio of reverse-to-forward current gain is increased about 5 times that of conventional bipolar transistor structures, and gate delay in IIL circuits is about 1 ns/gate. The structure opens the way for further scaled-down VLSI.     

Deep-channel MOS transistor

A new type of ion-implanted MOS transistor is described. The transistor functions, for example, as an integrating nondestructively readable photosensor and its technology is fully compatible with the advanced MOS integrated circuits.     

Negative-resistance MOS transistor

The author proposes a novel approach for implementing a negative-resistance MOSFET that uses a non-uniform drain-current flow within one integrated structure. This MOS device exhibits a negative output conductance within a specific bias range as a consequence of current sharing between two MOSFETs of different geometries. The author describes a negative-resistance MOS transistor and discusses in detail its principle of operation, design, and electrical characteristics. The MOSFET is a three-terminal voltage-controlled device that consists of two MOS transistors with the same type of channel conductivities and can be implemented either in n-channel or p-channel versions. The proposed device is a compact element that can be fabricated together with other semiconductor devices using a standard CMOS technology     

MOS晶体管技术

简要回顾MOS晶体管一些具有代表性的技术进展,分析了其在将来超大规模集成电路(ULSI)应用中的主要限制.从材料以及器件结构两个方向分别阐述了突破现有MOS技术而最有希望被将来ULSI工业所采用的新型晶体管技术.     

Self-aligned GaAs gate heterojunction SISFET

A self-aligned GaAs gate heterojunction enhancement-mode SISFET with a layer structure of n+-GaAs/undoped Al0.5Ga0.5As/undoped GaAs is fabricated and shows a high transconductance and a low threshold voltage. The highest transconductance at both room temperature and at 77 K ever reported on a long-channel GaAs gate SISFET, 197 mS/mm and 313 mS/mm, respectively, is obtained.     

Self-aligned GaAs MISFET's with a low-temperature-grown GaAs gateinsulator

GaAs MISFET's with a low-temperature-grown (LTG) GaAs gate insulator and ion-implanted self-aligned source and drain n⁺ regions are demonstrated. The resistivity and breakdown field of the LTG GaAs insulator were not changed appreciably by implantation and 800°C activation annealing. The gate leakage current remained very low at a value of approximately 1 μA per μm² of gate area at 3 V forward gate bias. Because of the reduced source and drain resistance, the drain saturation current and the transconductance of self-aligned MISFET's increased more than twofold after ion implantation     

Optimizing MOS transistor mismatch

An investigation of MOS transistor mismatch is undertaken and a methodology is developed for optimizing mismatch without increasing layout area. Dramatic improvements of up to 300% in matching can be realized by selecting the optimum W/L ratio without changing the overall WL area product. The theoretical basis for the obtainable improvements is fully described and an expression is derived and verified by experiment to predict the W/L ratio which gives optimum matching     

Photoresponses of MOS transistor

Illumination effects on the drain current were studied for a p-channel enhancement-type MOS transistor, and the results show that the photoresponses are mainly due to electron excitation in the conduction band from surface states lying near the top of the valence band. It also appears that the hole density of the channel decresses in the vicinity of the drain region but is almost constant over the entire channel when more than 200 µm away from the drain edge.     

Substrate current in silicon p-channel MOS transistors

Substrate currents are observed in silicon p-channel MOSFET devices. These currents are similar to those observed in n-channel MOSFETs but have a markedly higher threshold voltage.     

GaAs亚微米自对准工艺技术研究

总结了在５０ｍｍＧａＡｓ圆片上实现自对准介质膜隔离等平面工艺技术的研究，着重描述了离子注入、自对准亚微米难熔栅制备、钝化介质膜生长、干法刻蚀、电阻和电容制备等关键工艺的研究结果。这套工艺的均匀性、重复性好，在５０ｍｍＧａＡｓ圆片上获得了满意的成品率。采用这套工艺已成功地研制出多种性能良好的ＧａＡｓＩＣ和ＧａＡｓ功率ＭＥＳＦＥＴ，证明国家自然科学基金委员会这一重大课题的选择对发展我国ＧａＡｓＩＣ确实具有重大意义。     

Effect of surface passivation of AlGaN/GaN heterostructurefield-effect transistor

The effect of SiN passivation of the surface of AlGaN/GaN transistors is reported. Current deep level transient spectroscopy (DLTS) measurements were performed on the device before and after the passivation by a SiN film. The DLTS spectra from these measurements showed the existence of the same electron trap on the surface of the device. The DLTS spectrum obtained from the measurement of the passivated device showed a significantly lower peak for this trap. The discrepancy in the DLTS peak amplitude is explained by the effect of the passivation on the surface traps and underlines the surface nature of the major defect noticed in the device     

Trap effects in p-channel GaAs MESFET's

After processing of conventional n-channel GaAs MESFETs, traps in the channel and channel interface regions cause several deleterious parasitic device effects. It is known that a p-well GaAs MESFET structure eliminates all of the undesirable parasitic effects in n-channel devices; moreover, complementary p-channel MESFETs are realizable with the same p-well technology. The hole capture and emission processes of deep-level traps associated with p-channel GaAs MESFETs are characterized here using temperature-dependent drain current transient measurements. The transient behavior is dominated by trapping in the channel-substrate interface region analogous to an n-channel MESFET. By employing a one-level model to extract the activation energy and capture cross section, the traps in the channel-substrate region of the p-channel MESFET are attributed to an EL2 antisite defect (As_Ga )     

Self-aligned submicron gate digital GaAs integrated circuits

Digital normally-off (ENFET) GaAs integrated circuits have been fabricated using a novel self-aligned gate process that has produced high speed ring-oscillators with propagation delays as low as 25 ps and other low power circuits with power dissipation as small as 16 µW (at room temperature). The process is unique in that it permits control of parasitic FET source resistance and gate capacitance and also can achieve submicron gate lengths using conventional optical lithography.     

自对准AlGaAs/GaAs微波异质结双极晶体管(HBT)

本文提出了一种制作HBT采用的垂直台面结构自对准工艺.利用该工艺及对A1GaAs/GaAs具有高选择比的化学湿法腐蚀剂,已研制成微波HBT.发射区台面与基极电极间隙为0.1μm,最大直流电流增益为40,截止频率f_T为10GHz.     

Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors

The high-frequency thermal noise in the drain and the gate of an enhancement mode MOS field-effect transistor was analyzed by using the transmission line model of the channel. The analysis gave the mean squared noise current generators of the drain and the gate and their correlation. The correlation coefficient of the drain and the gate noise was zero for zero drain voltage and was 0.395j at saturation. The noise figure of the MOS field-effect transistor was calculated from the result of the analysis. The high-frequency noise characteristics of an MOS field-effect transistor were similar to those of a junction gate field-effect transistor.     

p-channel GaAs SIS (semiconductor-insulator-semiconductor) FET

The first p-channel GaAs SIS (semiconductor-insulator-semiconductor) FET having a p+-GaAs/undoped GaAlAs/undoped GaAs structure is reported. The FET fabricated shows a transconductance of gm=30 mS/mm, a drain conductance of gd=2.5 mS/mm and a threshold voltage of Vth=+0.2 V at 77 K in the dark.     

MOS Pass transistor turn-off transient analysis

Errors induced by turn-off transients are one fundamental limit in precision switched capacitor circuits. This paper presents detailed pass transistor turn-off transient analysis. Conventional single-lump models which assume quasi-static operation can introduce substantial errors for high-speed analog applications. New distributed and two-lump models have been constructed to analyze pass transistor turn-off transients in the diffusion mode of operation. A pass transistor test chip including a new selectively doped pass transistor approach has been designed, fabricated, and tested to verify the transient analysis. Measured performance of the nonuniformly doped pass transistors shows advantages in reducing transient charge errors.     

p-Channel MOS transistor in indium antimonide

A p-channel MOS transistor in InSb single crystal, operating at 77 K, is described. The source and drain are defined by etching a mesa structure in a cadmium diffused p layer into a tellurium-doped InSb substrate. The gate is formed by evaporation of chromium gold on top of a layer of SiO2, deposited at 215°C. The MOS transistor is characterized by a threshold voltage of -3 V and an effective hole mobility of 330 cm². V^-1.s^-1.