Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

An operational amplifier with rail-to-rail input and output voltage range in 0.6 μm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62° phase margin, 2.5 V/μs slew rate, and 147 μW power consumption.     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

Effective parameter extraction using multiple-objective function for VLSI circuits

In this paper an input stage and an output stage are presented for application in low-voltage CMOS operational amplifiers. The input stage operates in strong inversion and has a rail-to-rail common-mode input voltage range. The transconductance (g _m ) is insensitive to the common-mode input voltage. The class AB output stage has a rail-to-rail output range. A class AB control circuit prevents any transistors in the output stage from switching off. This improves the large-signal high-frequency behavior and the step response of the amplifier. A complete two-stage Op Amp employing the proposed input and output stages was realized in a semi-custom CMOS process with minimum channel lengths of 10µm and transistor threshold voltages of approximately 0.7 V. The measured minimum supply voltage is 2.5 V. The measured input voltage range exceeds the supply rails and the output voltage reaches both rails within 130 mV. The unity-gain bandwidth of the complete Op Amp is severely limited by the long channel lengths. Simulations show that a unity-gain bandwidth of 7 MHz is feasible if 2.5µm channel lengths are used.     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

一种恒跨导轨对轨CMOS运算放大器的设计

设计了一种新颖的恒跨导轨对轨CMOS运算放大器结构。输入级采用轨对轨的结构,在输入级采用4个虚拟差分对管来对输入差分对的电流进行限制,使运放的输入级跨导在工作范围内保持恒定。输出级采用前馈式AB类输出结构,以使输出达到全摆幅。仿真结果显示,在5 V电源电压和带有10 pF电容与10 kΩ电阻并联的负载下,该运放在共模输入范围内实现了恒跨导,在整个共模输入范围内跨导变化率仅为3%,输出摆幅也达到了轨对轨全摆幅,运放的开环增益为108.5 dB,增益带宽积为26.7 MHz,相位裕度为76.3°。     

An Adaptive Biased Single-Stage CMOS Operational Amplifier with a Novel Rail-to-Rail Constant-<Emphasis Type="Italic">g</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript> Input Stage

Using rail-to-rail (R-R) swing analog circuits has become almost mandatory in the design of low supply voltage circuits. In this paper, a new architecture for constant-g_m rail-to-rail input stages is presented. The design features a less than 5% deviation in g_m over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. By employing these techniques, a low-power operational amplifier (op-amp) with 100 MHz unity-gain bandwidth, 106 dB gain, 60^∘ phase margin, 2.65 V swing, and 6.4 nV/✓Hz input-referred noise with rail-to-rail input common-mode range is realized in a 0.8 μ m CMOS technology. This amplifier dissipates 10 mW from a 3 V power supply.     

一种恒跨导CMOS运算放大器的设计

设计了一种宽带轨对轨运算放大器,此运算放大器在3.3 V单电源下供电,采用电流镜和尾电流开关控制来实现输入级总跨导的恒定。为了能够处理宽的电平范围和得到足够的放大倍数,采用用折叠式共源共栅结构作为前级放大。输出级采用AB类控制的轨对轨输出。频率补偿采用了级联密勒补偿的方法。基于TSMC 2.5μm CMOS工艺,电路采用HSpice仿真,该运放可达到轨对轨的输入/输出电压范围。     

低功耗轨至轨CMOS运算放大器设计

设计了一个1.5 V低功耗轨至轨CMOS运算放大器。电路设计中为了使输入共模电压范围达到轨至轨性能,采用了NMOS管和PMOS管并联的互补差动对输入结构,并采用成比例的电流镜技术实现了输入级跨导的恒定。在中间增益级设计中,采用了适合在低压工作的低压宽摆幅共源共栅结构;在输出级设计时,为了提高效率,采用了简单的推挽共源级放大器作为输出级,使得输出电压摆幅基本上达到了轨至轨。当接100 pF电容负载和1 kΩ电阻负载时,运放的静态功耗只有290μW,直流开环增益约为76 dB,相位裕度约为69°,单位增益带宽约为1 MHz。     

一种用于视频信号处理的高速宽带运算放大器

基于高速亚微米互补双极工艺,设计了一种用于视频信号处理的高速宽带运算放大器。电路内部采用高速输入差分对、电流型放大单元、Rail-to-Rail输出单元等结构进行信号传输和放大。对开环增益提升、高速电压-电流信号转换、满摆幅输出设计以及频率稳定性补偿等关键技术进行分析,利用Spectre软件进行仿真。流片后的测试结果表明,在±5 V工作电压下,该放大器的－3 dB带宽≥200 MHz,失调电压≤5 mV,电源电流≤6 mA,满足高速通信、高速ADC前端信号采集、视频信号处理等各种场合的应用需求。     

一种电流跟踪补偿的输入输出全摆幅运算放大器

介绍了一种工作在2.5V电压下、具有全摆幅输入与输出功能的两级CMOS运算放大器。通过一种简单有效的电流跟踪电路实现了输入跨导恒定的要求，这样使得频率补偿变得容易实现；为了降低功耗，输入级工作在弱反型区：输出级采用带有前馈控制电路的AB类输出电路，实现了输出信号的轨至轨。电路具有结构简单、功耗低、面积小、性能高等优点。     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

一种用于生物信号采集的CMOS全差分前置跨阻放大器设计

针对生物信号微弱、变化范围大等特点设计了一种用于检测微弱电流的全差分跨阻放大器(TIA)电路结构。不同于传统电路的单端输入,该结构采用高增益的全差分两级放大器实现小信号输入及轨到轨输出。基于CSMC 0.18μm CMOS工艺,采用1.8V电源电压对设计的电路进行了仿真,仿真结果表明:TIA输入电流动态范围为100nA^10μA,最大跨阻增益达到104.38dBΩ,-3dB带宽为4MHz,等效输入噪声电流为1.26pA/Hz。对电路进行跨阻动态特性仿真表明,在输入电流为100nA时,输出电压的动态摆幅达到3.24mV,功耗仅为250μW,总谐波失真(THD)为-49.93dB。所设计的高增益、低功耗、宽输入动态范围TIA适用于生物医疗中极微小生物信号的采集,可作为模块电路集成在便携设备中。     

采用输入信号适配技术的BiCMOS运放

为了满足高性能开关电源中集成运放的应用需要,设计了一种结构简单且具有轨对轨输出的运算放大器.该运放基于0.5μm BiCMOS 工艺,采用浮动输出的输入信号适配器(ISAFO),将输入信号放大至差分输入级的工作区域,从而实现了轨对轨的运行.对所设计的运放进行了仿真分析,结果表明在工作电源电压为±0.75 V、外接100 kΩ电阻的条件下,该运放的直流开环增益达到了102 dB,单位增益-带宽为6.35 MHz,相位裕度为62.5°,而功耗仅约为150 μW.所设计的运放具有很宽的共模输入范围及较高的增益,所以特别适用于开关电源的误差放大器、过流、过压和过热保护模块中.     

1-V operational amplifier with rail-to-rail input and output ranges

A bipolar operational amplifier (OA) with rail-to-rail input and output ranges which can operate at supply voltages down to 1 V is presented. At this supply voltage, the input offset voltage is typically 1.0 mV in an input common-mode voltage range that extends beyond both supply rails for about 300 mV, with a common-mode rejection ratio (CMRR) between 38 and 100 dB, depending on conditions. The output voltage can reach both supply rails within 100 mV, the output current is limited to ±10 mA, the voltage gain is 100 dB, and the bandwidth is 450 kHz. The die is 2.5×5.5 mm². Qualities such as offset, input-bias current, and CMRR are improved when the supply voltage is increased and the dynamic level shift is autonomically turned off. The OA has been protected against unintentional reversal of the output signal when the inputs are substantially overdriven. The output stage of the circuit consists of two full complementary composite transistors, whose HF characteristics have been improved by internal Miller compensation and linearization of the transconductance     

微电容超声换能器的前端专用集成电路设计

针对微电容超声换能器(CMUT)微弱电流信号检测的要求,设计了一种用于CMUT的前端专用集成电路——运算放大器(OPA)电路。运算放大器电路采用两级放大结构,第一级采用全差分折叠-共源共栅结构,输出级采用AB类控制的轨到轨输出级,在运算放大器电路反相输入端和输出端通过一个反馈电阻实现CMUT电流信号到电压信号的转换。采用GlobalFoundries 0.18μm的标准CMOS工艺进行了仿真设计和流片,芯片尺寸为226μm×75μm。仿真结果表明,运算放大器的开环增益为62 dB,单位增益带宽为30 MHz,在3 MHz处的输入参考噪声电压为2.9μV/Hz^1/2,电路采用±3.3 V供电,静态功耗为11 mW。测试结果表明仿真与实测结果相符,该运算放大器电路能够实现CMUT微弱电流信号检测功能。     

A high-frequency fully differential BiCMOS operational amplifier

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-μm BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin, and a slew rate of 150 V/μs. The differential output range is 12 V. The circuit is operated from a ±5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages     

New Fully‐Differential CMOS Second‐Generation Current Conveyer

This paper presents a new CMOS fully‐differential second‐generation current conveyor (FDCCII). The proposed FDCCII is based on a fully‐differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit operating at a supply voltage of ± 1.5 V, it has a total standby current of 380 µA. The applications of the FDCCII to realize a variable gain amplifier, fully‐differential integrator, and fully‐differential second‐order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS 0.35 µm technology.     

Low Voltage CMOS Power Amplifier with Rail-to-Rail Input and Output

This paper describes a CMOS power amplifier with rail-to-rail input and output, also suitable for low voltage applications. The amplifier uses Simple Miller Compensation with high bandwidth stage to robustly and power efficiently compensate the amplifier. Circuit also includes a common mode adapter block, based on resistive level shift network, to implement rail-to-rail input and optional adaptive biasing block, which can be used to extend bandwidth of the amplifier for large high frequency inputs in continuous-time applications. Measurement results show that the amplifier is capable of driving heavy resistive and capacitive loads having maximum output current exceeding 100 mA, when driving 1 nF ‖ 10 Ω load from 3.0 V supply. Without adaptive biasing the linear amplifier achieves 5.7 MHz unity gain frequency and 61^∘ phase margin when driving 1 nF ‖ 1 kΩ load, while drawing 2.4 mA from 1.5 V supply.     

一种低压、恒增益Rail-to-rail运算放大器的设计

文章设计了一种低压、恒定增益、Rail-to-rail的CMOS运算放大器。该放大器采用直接交迭工作区的互补并联输入对作为输入级,在2V单电源下,负载电容为25pF时,静态功耗为0.9mW,直流开环增益、单位增益带宽、相位裕度分别为74dB、2.7MHz、60°。     

0.4-V bulk-driven differential-difference amplifier

A new solution for an ultra-low-voltage, low-power, bulk-driven fully differential-difference amplifier (FDDA) is presented in the paper. Simulated performance of the overall FDDA for a 50 nm CMOS process and supply voltage of 0.4 V, shows dissipation power of 31.8 μW, the open loop voltage gain of 58.6 dB and the gain-bandwidth product (GBW) of 2.3 MHz for a 20 pF load capacitance. Despite the very low supply voltage, the FDDA exhibits rail-to-rail input/output swing. The circuit performance has also been tested in two applications; the differential voltage follower and the second-order band-pass filter, showing satisfactory accuracy and dynamic range.