Contact Resistance Estimation for Time-Dependent Silicone Elastomer Matrix of Land Grid Array Socket

A land grid array (LGA) socket provides high-density, electrically-separable interconnect between a component and a printed circuit board. The LGA socket must not be susceptible to creep and stress relaxation, which can lead to loss of contact force and consequently the degradation of contact resistance. In this paper, the time-dependent contact resistance failure mechanisms were experimentally assessed and theoretically analyzed for silicone elastomer matrix socket interconnects. A time-dependent physics-of-failure model was developed for contact resistance simulation     

Optical interconnects for neural and reconfigurable VLSIarchitectures

The increasing transistor density in very large-scale integrated (VLSI) circuits and the limited pin member in the off-chip communication lead to a situation described as interconnect crisis in micro-electronics. Optoelectronic VLSI (OE-VLSI) circuits using short-distance optical interconnects and optoelectronic devices like microlaser, modulator, and detector arrays for optical off-chip sending and receiving offer a technology to overcome this crisis. However, in order to exploit efficiently the potential of thousands of optical off-chip interconnects, an appropriate VLSI architecture is required. We show for the example of neural and reconfigurable VLSI architectures that fine-grain architectures fulfill these requirements. An OE-VLSI circuit realization based on multiple quantum-well modulators functioning as two-dimensional (2-D) optical input/output (I/O) interface for the chip is presented. Due to the parallel optical interface, and improvement of two to three orders of magnitude in the throughput performance is possible compared to all-electronic solutions. For the optical interconnects, a planar-integrated free-space optical system has been designed leading to an optical multichip module. Such a system has been fabricated and experimentally characterized. Furthermore, we designed an manufactured fiber arrays, which will be the core element for a convenient test station for the 2-D optoelectronic I/O interface of OE-VLSI circuits     

Optimum voltage swing on on-chip and off-chip interconnect

Reduced voltage swings are often used for saving power on interconnects. In this paper, we demonstrate the existence of an optimum voltage swing for minimum power consumption, for on-chip and off-chip interconnects. Actual values of optimum swings and corresponding power savings for high performance interconnects are estimated     

Multiple impact characterization of wafer level packaging (WLP)

Wafer level packaging (WLP) of connectivity RF components for mobile devices has emerged as a low-cost and high performance, enabling technology. WLP devices are electronic components with an exposed die that utilizes a ball pitch compatible with standard surface mount technology (SMT) equipment and common printed circuit board (PCB) design techniques. WLP allows the devices to be directly mounted to the PCB of portable devices. One concern of adopting WLP for mobile device applications is reliability under multiple dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. A series of dynamic 4-point bend tests were conducted to evaluate the multiple impact reliability of WLP samples. The purpose of this work was to better understand the failure modes and actual reliability of WLP under uniaxial loading, which is commonly observed in mobile drop simulations and tests. The results have been applied to WLP failure prediction for the system-level drop test by using simulation technology.     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

Test structures for propagation delay measurements on high-speed integrated circuits

The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.     

一种基于WLP封装的声表面波滤波器

以41°Y X切型铌酸锂作为基底材料,选择双T型阻抗元结构,采用晶圆级封装（WLP）技术,制作了一款相对带宽5.8%,最小插入损耗为-2.8 dB,体积为1.1 mm×0.9 mm×0.5 mm的小型化WLP封装声表面波滤波器。并研制了专用探卡,对封装后晶圆完成在线测试。测试结果表明,探卡测试结果与装配到实际电路的测试结果进行对比,两者吻合较好,解决了WLP封装声表面波滤波器测试难题。     

基于CAN总线智能查线仪的设计与实现

提出了一种基于CAN总线的智能查线仪的设计和实现方案。将现场可编程芯片、AVR微处理器用于查线设备,使用CAN总线与计算机通信方式来实现各查线模块间的数据通信和结构连接,并通过软件设计来识别有大数量待测端子情况下所需硬件上查线模块的扩充和指定待测查线端点数量,有效地解决了以往各类查线设备缺乏灵活性、扩展性差的问题,能够适应多种场合的不同需求,为各种线缆电气连接关系的检查提供了一种新的解决方案。     

Electrical interconnects revitalized

Models of electrical interconnects, including inductance and skin effect, are reviewed. The models are used for estimating the performance of electrical interconnects, particularly related to delays, data rates, and power consumption for off-chip and on-chip interconnects and for clock distribution. It is demonstrated that correctly utilized, electrical interconnects do not severely limit chip or circuit board capacity. Delays, data rates, and power consumption of electrical interconnects within a circuit board are acceptable and superior to optical alternatives.     

Memory customisations for image processing applications targeting MPSoCs

Multiprocessor System on Chips (MPSoCs) are quickly becoming the mainstay in embedded processing platforms due to their hardware and software design flexibility. This flexibility increases the design space for developers, introducing trade-offs between performance and resource/power consumption. This paper presents a comprehensive evaluation of memory customisations for MPSoCs. Custom arrangements of instruction and data cache are presented to optimise off-chip memory consumption and improve system performance. Off-chip memory management and threading are presented to balance the computational load on available processors and improve system performance. The proposed methods are applied to an object detection case study, where performance increases of up to 2.93x are achieved when compared to standard memory designs. Furthermore, the proposed techniques can increase the number of possible processors in an MPSoC by reducing the number of bus interconnects.     

An investigation of the mechanical behavior of conductive elastomer interconnects

This paper presents our recent study on the mechanical behavior of conductive elastomer interconnects for the assembly of land-grid-array and ball-grid-array packages. Stiffness and contact-force relaxation were measured. Taking into consideration the actual operating conditions of the sockets, the effects of both environmental temperature and initial contact force on contact-force relaxation behaviors of conductive elastomer interconnects were investigated. The results show that temperature, rather than initial contact force, correlates with the long-term relaxation behavior of conductive elastomer interconnects.     

基于STM32的智能省电无隐患插座设计

针对人们用完电器设备通常不切断其供电电源致使其待机消耗大量能源的用电习惯,设计了一种基于ARM系列单片机STM32F103的具有监测设备用电状态和自动断电的智能省电插座。给出了插座的硬件电路设计构架,以及电压、电流监测电路,阐述了开关插座的软件设计方案。为了实现操作简单、快捷,设计的智能省电插座和普通的家用遥控器能相互兼容,该设计方案能使人们一键操作轻松解决待机能耗的问题,同时有效地延长了电器的安全使用寿命,具有节能、方便、安全的特点。     

Microwave frequency interconnection line model of a wafer level package

In this paper, we introduce the microwave transmission characteristics of interconnection lines on a wafer level package (WLP) and also propose a precise microwave-frequency model of the WLP interconnections. The slow wave factor (SWF) and attenuation constant are measured and discussed. High-frequency measurement is described, based on two-port S-parameter measurements, using an on-wafer microwave probe with a frequency range of up to 5 GHz. The extracted model is represented in the form of distributed lumped circuit model elements and can be easily merged into SPICE simulations. From the extracted model, it was found that line capacitance and inductance per unit length are 0.110 pF/mm and 0.286 nH/mm, respectively. We have successfully applied the extracted model to the design and analysis of a Rambus memory module for time domain simulation and signal integrity simulation. From the simulation, it was found that the WLP has better high-frequency performance, because of its low package inductance, compared with the /spl mu/BGA package, but longer propagation delay, because of the relatively high package capacitance.     

Low-K Dielectric Compatible Wafer-Level Compliant Chip-to-Substrate Interconnects

Performance, power, size, and cost requirements in the microelectronics industry are pushing for smaller feature size, innovative on-chip dielectric materials, higher number of interconnects at a reduced pitch, etc., without compromising the microelectronics reliability. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill material. These compliant interconnects are beneficial for integrated circuits (ICs) with low-K dielectric material. They are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we discuss the assembly and experimental reliability assessment, through thermal cycling, of G-Helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented. It is shown that the proposed interconnects are not likely to delaminate or crack the low-K dielectric material. Also, a unique integrative approach is discussed, with interconnects having varying compliance for optimum electrical and mechanical performance.     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.     

An IEEE 1149.1 Compliant Test Control Architecture

This paper deals with a design methodology and associated architecture to support the control of on-chip DFT and BIST hardware. The work is general in that it supports numerous test methods, such as partial and full scan, multiple and reconfigurable scan chains, and both test per clock BIST and scan BIST. The results presented here are compatible with the IEEE 1149.1 boundary scan architecture. The work is based on a hierarchical control methodology that includes systems, PCBs and MCMs. Various options for assigning control functions to be on-chip or off-chip are described. A new, partially distributed test control architecture is introduced that includes an internal test bus and distributed local controllers. There are three main modes of control of test resources, namely local static control, dynamic control and global static control. We show how the control mechanism can be implemented together with the IEEE 1149.1 test protocol. The synthesis of the on-chip test control hardware has been automated in a system called CONSYST.     

3D Modeling of electromigration combined with thermal–mechanical effect for IC device and package

This paper studies the numerical simulation method for electromigration in IC device and solder joint in a package under the combination of high current density, thermal load and mechanical load. The three dimensional electromigration finite element model for IC device/interconnects and solder joint reliability are developed and tested. Numerical experiment is carried out to obtain the electrical, thermal and stress fields with the migration failure under high current density loads. The direct coupled analysis and in-direct coupled analysis that include electrical, thermal and stress fields are investigated and discussed. The viscoplastic ANAND constitutive material model with both SnPb and SnAgCu lead-free solder materials is considered in the paper. An IC device is studied to show the modeling methodology and the comparison with previous test data. A global CSP package with PCB is modeled using relative coarse elements. In order to reduce the computational costs and to improve the calculation accuracy, a refined mesh sub-model is constructed. The sub-model technique is studied in a direct and indirect coupled multiple fields. The comparison of voids generation through numerical example in this paper and previous experimental result is given.     

Modeling and electrical analysis of seamless high off-chipconnectivity (SHOCC) interconnects

Scaling down on-chip interconnect cross-sectional dimensions results not only in higher circuit wiring density, but also in the long lossy line problem, wherein the long lines become highly resistive and have unacceptable delays. One possible solution to the problem of long lossy lines is to transfer these lines off-chip using seamless high off-chip connectivity (SHOCC) technology. In this work, me modeled and studied the electrical performance of SHOCC signal lines. The performance of SHOCC interconnects was compared with that of typical on-chip interconnerts. Modeling and simulation results, along with recommendations with regards to driver sizes and the type of interconnect that should be used, are presented     

A BiCMOS active substrate probe-card technology for digital testing

An active substrate silicon probe card has been implemented by forming a polyimide membrane on a silicon substrate. The probe card combines tungsten probe tips and aluminum interconnects in the polyimide membrane with active test circuitry integrated in the substrate. A monolithic prototype of the probe card designed to enhance the capabilities of conventional digital test systems has been fabricated in a 2-μm BiCMOS technology. The benefits of the proposed probe-card technology could be further exploited by integrating the timing measurement unit of a digital tester into the probe-card substrate. An integrated tester architecture based on time digitization is described. A prototype of a tester combining a time digitizer and two test channels has been integrated in a 0.6 μm BiCMOS technology. The time digitizer in the experimental circuit employs a two-stage ring oscillator that is phase-locked to an external reference and makes use of phase interpolation to achieve a timing resolution of 90 ps