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在配电网的电压和灵敏度的分析上,介入分布式电源会对配电网的安全性能造成一定的影响。回路分析法可以得到配电网中运行参数的动态变化。在具体的实践工作中,需要通过回路分析法,转变配电网中电路的方式,随后介入分布式电源后结合电压波动理论对效果进行研究,其中还会涉及到叠加定理,对回路中的指路电流进行叠加。配电网介入了分布式电源,电源系统会出现转变,不再是单一的电源,而是作为多种电源系统而存在。建设节点电压需要使用到回支关联矩阵,对线路损耗中的灵敏度分析电压产生的变化。最后在IEEE33节点当中对配电网进行仿真的研究。 相似文献
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为提升含分布式光伏配电网双层优化调度效果和该配电网的供电质量、降低运行成本与供电损耗、保障其运行的经济性与平稳性,提出一种基于云模型的含分布式光伏配电网双层优化调度方法。以低节点电压偏移量、低线路损耗及低运行成本为目标函数,为含分布式光伏配电网构建包含上层主动配电网与下层微电网优化调度模型的双层优化调度模型,结合云模型改进的粒子群(Cloud Model Improved Particle Swarm Optimization, CMOPSO)算法求解所构建的调度模型,完成基于云模型的含分布式光伏配电网双层优化调度方法的设计。实验结果表明,采用该方法进行优化调度后,可显著降低含分布式光伏配电网的线路损耗、电压偏移量及运行总成本,提高其各节点电压,使各节点电压更接近于安全电压基准值,减少配电网的供电损耗,提高其供电电能质量,保障其整体运行的平稳性与经济性;CMOPSO算法在求解模型时收敛到全局最优解的速度较高,收敛性能优越。所设计方法的总体效果较好,具有一定应用价值。 相似文献
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阐述分布式光伏发电系统的体系架构,配电网电压受到的分布式光伏发电系统的影响,探讨解决电压越限问题,并在此基础上建立模型进行解析。 相似文献
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针对恒定电压法在最大功率跟踪过程中所出现的精度差、受环境影响大等缺点,本文提出了一种基于优化电压的变电压最大功率跟踪算法,并给出实现方案。对于分布式光伏系统该方法能够在日照度、温度、负载变化的情况下有效的实现实际最大功率点的跟踪控制、减少系统能量的损耗。实验使用DSP来实现最大功率跟踪算法,并对温度、日照度、反向饱和电流进行补偿。结果证明该方法在日照度、温度、负载变化的情况下工作可靠、响应速度较迅速,并能够有效的改善输出动态特性。 相似文献
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《电子技术与软件工程》2016,(3)
为了提高光伏发电系统效率,研究了基于最大功率点跟踪的光伏发电系统控制原理。传统的恒定电压法(CVT)只与一固定的Um作比较,在温度变化时,Um变化,会影响最大功率点跟踪的精度。考虑到恒定电压法的局限性以及控制方法的复杂性,本文在恒定电压法中添加一个lookup table模块,来实现对Um的补偿。该方法规避了恒定电压法在温度变化时,由于开路电压变化导致与期望工作电压不匹配而造成的功率波动,改善了光伏阵列的最大功率跟踪的精度,同时也解决了最初的基于恒定电压法的最大功率点跟踪方法在实际应用中,需要手动调节开路电压的不足,实现了系统的自动化控制。 相似文献
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Tien-Yu Lo Chung-Chih Hung Mohammed Ismail 《Analog Integrated Circuits and Signal Processing》2010,62(1):9-15
A fully CMOS based voltage reference circuit is presented in this paper. The voltage reference circuit uses the difference
between gate-to-source voltages of two MOSFETs operating in the weak-inversion region to generate the voltage with positive
temperature coefficient. The reference voltage can be obtained by combining this voltage difference and the extracted threshold
voltage of a saturated MOSFET which has a negative temperature coefficient. This circuit, implemented in a standard 0.35-μm
CMOS process, provides a nominal reference voltage of 1.361 V at 2-V supply voltage. Experimental results show that the temperature
coefficient is 36.7 ppm/°C in the range from −20 to 100°C. It occupies 0.039 mm2 of active area and dissipates 82 μW at room temperature. With a 0.5-μF load capacitor, the measured noise density at 100 Hz
and 100 kHz is 3.6 and
2 5 \textnV/?{\textHz} , 2 5\,{\text{nV}}/\sqrt {\text{Hz}} , respectively. 相似文献
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A new common-mode voltage detector circuit to be used in the common-mode feedback loop of ultra-low voltage fully differential amplifiers is presented. The proposed circuit behaves linearly for most of the signal range and is able to operate with supply voltages as low as 0.4 V. The design issues and simulation results of the circuit in 0.18 m CMOS technology are presented. 相似文献
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Experimental evidence is given showing that Ag-n-Si Schottky diodes with resistivity about 40 m?cm have steeper reverse breakdown characteristics than corresponding low-voltage p-n junction regulator diodes fabricated by local epitaxy. Avalanche multiplication in such a diode starts at 1.7 V, and the device has a low positive temperature coefficient of breakdown voltage. 相似文献
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Kawahara T. Saeki S. Jyouno Y. Miyamoto N. Kobayashi T. Kimura K. 《Solid-State Circuits, IEEE Journal of》1998,33(1):126-132
A fabricated bandgap generator using 0.25-μm Flash memory process generated a stable reference voltage under 4 V, boosted from an external power supply of 2.5 V. The generated voltage was 1.297±0.025 V at a power supply of 4 V±10%; the temperature dependence was +0.7 mV/°C. The characteristics of a triple-well bipolar transistor for the Flash memory process are sufficient for a reference voltage generator; fT is 230 MHz, and HFE is 70. Dynamic operation reduced the average current consumption from 306 to 8.6 μA. Fabricated voltage-doubler circuits generated a voltage 1.8 times larger than that from conventional charge-pump circuits 相似文献
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A novel implementation of a rail-to-rail exponential voltage to voltage converter is presented. It is based on a pseudo-exponential approximation that is easily achieved by the nonlinear currents of a class-AB transconductor. Measurement results for a 0.5 /spl mu/m CMOS technology show a 52 dB output voltage range with linearity error less than /spl plusmn/2 dB using a dual supply voltage of /spl plusmn/750 mV. The power dissipation is less than 40 /spl mu/W. 相似文献
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Pouwelse J. Langendoen K. Sips H.J. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2003,11(5):812-826
Clock (and voltage) scheduling is an important technique to reduce the energy consumption of processors that support voltage scaling. It is difficult, however, to achieve good results using only statistics from the operating system level when applications show bursty (unpredictable) behavior. We take the approach that such applications must be made power-aware and specify their average execution time (AET) and the deadline to the scheduler controlling the clock speed and processor voltage. This paper describes our energy priority scheduling (EPS) algorithm supporting power-aware applications. EPS orders tasks according to how tight their deadlines are and how often tasks overlap. Low-priority tasks are scheduled first, since they can be easily preempted to accommodate for high-priority tasks later. The EPS algorithm does not always yield the optimal schedule, but has a low complexity. We have implemented EPS on a StrongARM-based variable-voltage platform. We conducted experiments with a modified video decoder that estimates the AET of each frame. Measurements show that application-directed voltage scaling reduces processor power consumption with 50% for the bursty video decoder without missing any frame deadlines. 相似文献
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