Online testing approach for very deep-submicron ICs

Very deep-submicron technologies pose new challenges to IC testing. In particular, crosstalk and transient faults are difficult to detect with traditional methods. Online testing techniques can detect these faults, however, and a new approach extends these techniques to include gross-delay faults. Moreover, this approach described by the authors can be exploited to detect stuck-at and bridging faults offline     

IDDQ testing for deep-submicron ICs: challenges andsolutions

The use of low-threshold devices in scaled low-voltage CMOS circuits leads to increased intrinsic leakage current. As a result, I _DDQ testing requires different techniques to remain effective     

Rethinking deep-submicron circuit design

Interconnect delay need not increase as CMOS process geometries shrink, and current IC design methods should suffice for modules of up to 50,000 gates. Beyond that, designers must focus on a new concept - global interconnect design. We consider the effects of both devices and interconnect, and our analysis shows that interconnect delay actually decreases for deep-submicron (DSM) processes in a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performance ASIC designs     

An evolutionary design methodology of printed circuit boards for high-speed VLSIs

As operation frequencies of the printed circuit boards (PCBs) increase in keeping with VLSI frequencies in the GHz domain, two independent serious problems occur in the PCB design. One is waveform distortion problem, or signal integrity (SI) degradation problem, in PCB traces. And the other is power-supply drop problem, or power integrity (PI) degradation problem, in PCB power planes. Those problems are barely able to be overcome on case-by-case empirical designs conventionally. In this paper we newly propose a design approach for each problem, both of which are based on the genetic algorithm. And we obtained improvement ratios of more than double compared with the both conventional designs for SI and PI degradations, respectively.     

Characterizing substrate coupling in deep-submicron designs

The accurate modeling of noise-coupling effects caused by crosstalk through the substrate is an increasingly important concern for design and verification of analog, digital, and mixed systems. With the technique described here, designers can efficiently extract accurate substrate-coupling parameters from deep-submicron designs     

Conquering noise in deep-submicron digital ICs

As feature sizes decrease and clock frequencies increase, noise is becoming a greater concern in digital IC design. The authors describe a verification metric, noise stability, which guarantees functionality in the presence of noise, and a CAD technique, static noise analysis, for applying this metric on a chipwide basis     

An integrated environment for technology closure of deep-submicron IC designs

With larger chip images and increasingly aggressive technologies, key design processes must interoperate, PDS, a physical-synthesis system, accomplishes technology closure through interacting processes of logic optimization, placement, timing, clock insertion, and routing, all using a common infrastructure with robust variable-accuracy analysis abstractions.     

Noise generation and coupling mechanisms in deep-submicron ICs

On-chip noise generation and coupling is an important issue in deep-submicron technologies. Advanced IC technology faces new challenges to ensure function and performance integrity. Selecting adequate test techniques depends on the circuit, its implementation, and the possible physical failures and parasitic coupling models. This new demand for test technology practices precipitated the investigation of dl/dt and dV/dt noise generation and propagation mechanisms     

Classic group testing with cost for grouping and testing

We generalize the classical group testing problem to incorporate costs associated with pooling and inspection, both of which are significant factors in actual applications. We formulate the expected cost model as a nonlinear integer programming problem, prove several propositions and a theorem concerning when pooling is more efficient than individual testing, and determine the optimal group size such that the expected cost is minimized.     

Model-based testing for real

Model-based testing relies on abstract behavior models for test case generation. These models are abstractions, i.e., simplifications. For deterministic reactive systems, test cases are sequences of input and expected output. To bridge the different levels of abstraction, input must be concretized before being applied to the system under test. The systems output must then be abstracted before being compared to the output of the model.The concepts are discussed along the lines of a feasibility study, an inhouse smart card case study. We describe the modeling concepts of the CASE tool AutoFocus and an approach to model-based test case generation that is based on symbolic execution with Constraint Logic Programming.Different search strategies and algorithms for test case generation are discussed. Besides validating the model itself, generated test cases were used to verify the actual hardware with respect to these traces.     

Extra stepping stone for testing

As the relatively young profession of software testing graduallymatures, certification is changing to keep up. ISEB has justupdated the content and structure of its practitioner leveland added a stepping stone to reach that standard, as HelenBoddy reports.     

Conformance testing for real-time systems

We propose a new framework for black-box conformance testing of real-time systems. The framework is based on the model of partially-observable, non-deterministic timed automata. We argue that partial observability and non-determinism are essential features for ease of modeling, expressiveness and implementability. The framework allows the user to define, through appropriate modeling, assumptions on the environment of the system under test (SUT) as well as on the interface between the tester and the SUT. We consider two types of tests: analog-clock tests and digital-clock tests. Our algorithm for generating analog-clock tests is based on an on-the-fly determinization of the specification automaton during the execution of the test, which in turn relies on reachability computations. The latter can sometimes be costly, thus problematic, since the tester must quickly react to the actions of the system under test. Therefore, we provide techniques which allow analog-clock testers to be represented as deterministic timed automata, thus minimizing the reaction time to a simple state jump. We also provide algorithms for static or on-the-fly generation of digital-clock tests. These tests measure time only with finite-precision digital clocks, another essential condition for implementability. We also propose a technique for location, edge and state coverage of the specification, by reducing the problem to covering a symbolic reachability graph. This avoids having to generate too many tests. We report on a prototype tool called and two case studies: a lighting device and the Bounded Retransmission Protocol. Experimental results obtained by applying on the Bounded Retransmission Protocol show that only a few tests suffice to cover thousands of reachable symbolic states in the specification.     

Bottom-up reuse for multi-level testing

Lifecycle models divide the test process into consecutive test levels that are considered independently. This strict separation obstructs the view on the test process as a whole and fails to reflect the commonalities across test levels. Multi-level testing is an emerging approach that addresses the challenge of integrating test levels, putting particular emphasis on embedded systems. In this paper, we introduce a test level integration strategy based on reuse that is called bottom-up reuse. In addition, we present a test level instrument that seamlessly supports this strategy: multi-level test cases. We also provide a case study that reflects the positive results we have obtained in practice so far and demonstrates the feasibility of our test level integration approach. Bottom-up reuse and multi-level test cases lead to testing earlier on in the development process while reducing the effort required by test specification, test design, and test implementation.     

Serial interfacing for embedded-memory testing

A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits for telecommunications. Even though the method uses serial access to the memory, a test pattern is applied every clock cycle because the memory itself shifts the test data. The method has been adapted to four common algorithms. In implementations of built-in self-test circuitry on several product chips, the area overhead was found to be acceptable     

Formal testing for separation assurance

In order to address the rapidly increasing load of air traffic operations, innovative algorithms and software systems must be developed for the next generation air traffic control. Extensive verification of such novel algorithms is key for their adoption by industry. Separation assurance algorithms aim at predicting if two aircraft will get closer to each other than a minimum safe distance; if loss of separation is predicted, they also propose a change of course for the aircraft to resolve this potential conflict. In this paper, we report on our work towards developing an advanced testing framework for separation assurance. Our framework supports automated test case generation and testing, and defines test oracles that capture algorithm requirements. We discuss three different approaches to test-case generation, their application to a separation assurance prototype, and their respective strengths and weaknesses. We also present an approach for statistical analysis of the large numbers of test results obtained from our framework.