A polysilicon contacted subcollector BJT for a three-dimensionalBiCMOS process

A polysilicon contacted subcollector (PCS) bipolar junction transistor (BJT) was fabricated using selective epitaxial growth (SEG) of silicon to form the active region. The fabrication is the first step in the development of a novel 3-D BiCMOS process. To study the efficacy of the polysilicon collector contact, three types of BJTs were fabricated and their collector resistances were compared. These were the PCS BJT, a BJT fabricated in SEG silicon grown from a shallow trench incorporating a shallow collector contact with a buried layer, and a BJT fabricated in the silicon substrate with a shallow collector contact but no buried layer. The PCS BJT exhibited the smallest collector resistance as well as excellent device characteristics, demonstrating its viability for a 3-D BiCMOS process     

Laser‐fired contact optimization in c‐Si solar cells

In this work we study the optimization of laser‐fired contact (LFC) processing parameters, namely laser power and number of pulses, based on the electrical resistance measurement of an aluminum single LFC point. LFC process has been made through four passivation layers that are typically used in c‐Si and mc‐Si solar cell fabrication: thermally grown silicon oxide (SiO₂), deposited phosphorus‐doped amorphous silicon carbide (a‐SiC_x/H(n)), aluminum oxide (Al₂O₃) and silicon nitride (SiN_x/H) films. Values for the LFC resistance normalized by the laser spot area in the range of 0.65–3 mΩ cm² have been obtained. Copyright © 2011 John Wiley & Sons, Ltd.     

Improvement of Ni/Si/4H-SiC ohmic contacts by VLS grown sub-contact layer

This work presents results of using VLS epitaxial Si-Ge-type structure as a sub-contact layer designated for Ni/Si ohmic contacts. The epitaxial growth was performed at 1240 and 1414 °C in various types of atmosphere in a processing chamber. The prepared layers had mostly smooth surface. XPS analysis showed that germanium escape from the structure occurred during the process of the epitaxial growth. An important result is that silicon and carbon bind in the form of SiC already at the surface of the structure, which proves silicon carbide formation during the epitaxial growth. Ni/Si-type contact metallization was deposited onto all epitaxial structures. After annealing we received ohmic contacts with contact resistivity equal or lower compared to the standard contact structure Ni/Si/SiC prepared on the same substrate. The best value of contact resistivity was 4 × 10⁻⁵ Ω cm². The doping concentration in the VLS epitaxial layers is reaching the value (6-7) × 10¹⁸ cm⁻³.     

Employing microsecond pulses to form laser‐fired contacts in photovoltaic devices

Laser‐fired contacts (LFCs) are typically fabricated with nanosecond pulse durations despite the fact that extremely precise and costly control of the process is necessary to prevent significant ablation of the aluminum metallization layer. Microsecond pulse durations offer the advantage of reduced metal expulsion and can be implemented with diffractive optics to process multiple contacts simultaneously and meet production demands. In this work, the influence of changes in laser processing parameters on contact morphology, resistance, and composition when using microsecond pulses has been fully evaluated. Simulated and experimental results indicate that contacts are hemispherical or half‐ellipsoidal in shape. In addition, the resolidified contact region is composed of a two‐phase aluminum–silicon microstructure that grows from the single‐crystal silicon wafer during resolidification. As a result, the total contact resistance is governed by the interfacial contact area for a three‐dimensional contact geometry rather than the planar contact area at the aluminum–silicon interface in the passivation layer opening. The results also suggest that for two LFCs with the same size top surface diameter, the contact produced with a smaller beam size will have a 25–37% lower contact resistance, depending on the LFC diameter, because of a larger contact area at the LFC/wafer interface. Copyright © 2014 John Wiley & Sons, Ltd.     

Application of selective CVD tungsten for low contact resistance via filling to aluminum multilayer interconnection

Process parameters for selective chemical vapor deposition of tungsten to fill vias between aluminum or aluminum alloy multilevel metallization have been identified and demonstrated. By controlling two competing parallel reactions: Aluminum and hydrogen reductions of tungsten hexafluoride in one reduction step process, the specific contact resistivity was found to be in the range of 2.5 to 8.0 x 10⁻⁹ ohm-cm² for 1.8 micron diameter vias. This is at least one order of magnitude lower than the values reported by the previous workers. It was also observed that alloying the aluminum did not appear to affect the contact resistance significantly. In this experiment one cold wall experimental reactor, two cold wall production systems of two different models and one hot wall tube furnace were used to deposit selective CVD tungsten on aluminum or aluminum with 1% silicon first level metal. As a consequence of these findings, problems associated with filling straight wall vias of high aspect ratio in VLSI multilevel interconnection (i.e., high contact resistance, poor step coverage, electromigration, etc.) can now be alleviated or resolved. Therefore, the use of selective CVD tungsten in the existing aluminum IC metallization becomes very attractive and feasible.     

Contact resistance behavior of the Pd2 Si-AlCuSi system

Aluminum to silicon contact resistance, R_c , is influenced by the choice of intermediate contact and interconnection metallurgies, as well as anneal cycles associated with metallization and post-metallization passivation processes in single and multi-level metal VLSI technologies. This is particularly evident for the metallurgical system comprised of palladium silicide, Pd₂ Si, and AlCuSi. This system has been investigated to ascertain the relationships between R , anneal time, and anneal temperature for various Pd Si thicknesses of AlCuSi contacts to N⁺ single-crystal silicon and polysilicon. The evaluations revealed that R_c and R_c distribution are inversely proportional to Pd₂ Si thickness, and increase with anneal time and temperature. The results are compared to the known physical chemical interactions of Pd Si and Al. The studies demonstrate that by proper selection of process parameters and contact structure design, stable Al-Si contact resistance can be achieved for semiconductor device applications when Pd is used as an intermediate contact metallurgy.     

Contact Engineering of Layered MoS2 via Chemically Dipping Treatments

The performance of electronic/optoelectronic devices is governed by carrier injection through metal–semiconductor contact; therefore, it is crucial to employ low‐resistance source/drain contacts. However, unintentional introduction of extrinsic defects, such as substoichiometric oxidation states at the metal–semiconductor interface, can degrade carrier injection. In this report, controlling the unintentional extrinsic defect states in layered MoS₂ is demonstrated using a two‐step chemical treatment, (NH₄)₂S(aq) treatment and vacuum annealing, to enhance the contact behavior of metal/MoS₂ interfaces. The two‐step treatment induces changes in the contact of single layer MoS₂ field effect transistors from nonlinear Schottky to Ohmic behavior, along with a reduction of contact resistance from 35.2 to 5.2 kΩ. Moreover, the enhancement of I_ON and electron field effect mobility of single layer MoS₂ field effect transistors is nearly double for n‐branch operation. This enhanced contact behavior resulting from the two‐step treatment is likely due to the removal of oxidation defects, which can be unintentionally introduced during synthesis or fabrication processes. The removal of oxygen defects is confirmed by scanning tunneling microscopy and X‐ray photoelectron spectroscopy. This two‐step (NH₄)₂S(aq) chemical functionalization process provides a facile pathway to controlling the defect states in transition metal dichalcogenides (TMDs), to enhance the metal‐contact behavior of TMDs.     

Comprehensive analysis of advanced solar cell contacts consisting of printed fine‐line seed layers thickened by silver plating

This work presents a detailed analysis of a new two‐layer process to contact industrial solar cells. However, most of the results seem to be transferable to standard screen print paste contacts. The seed layer was created by a pad or screen printer and thickened by light‐induced plating (LIP) of silver. These contact structures were investigated microscopically to gain a better understanding of the observed electrical parameters. A review of the present microscopic contact formation model for flat surfaces is presented. This model was extended and applied to surfaces textured with random pyramids. This analysis has revealed two new types of silver crystallites which can be described by a crystallographic model. The dependence of the silver crystallite density on the surface doping concentration was investigated. Next, the dependence of the contact resistance on the width of the seed layer was measured showing that the contact resistivity increases with a reduction of the seed layer width. These results have been further approved by an analysis of SEM images of wet‐chemically etched contacts examining the density of crystallites and the fraction of removed SiN_x layer. Contact resistance R_C measurements before and after LIP of silver showed surprisingly a positive influence of the plating process on R_C. A detailed microscopical analysis revealed four new possible current flow paths due to the LIP of a conventional contact or a seed layer. The results led to an extension of the existing model for a screen‐printed contact. Copyright © 2008 John Wiley & Sons, Ltd.     

Effect of rapid thermally nitrided titanium films contacting silicided and nonsilicided junctions

The effect of rapid thermally nitrided titanium films contacting silicided (titanium disilicided) and nonsilicided junctions has been studied in the temperature range of 800 to 900°C. The rapid thermal nitridation of titanium films used as diffusion barriers between aluminum and silicon, has a major impact on shallow junction complementary metal oxide semiconductor technologies. During the process of rapid thermal nitridation, the dopants in the junctions undergo a redistribution and affect the electrical properties of shallow junction structures. This work focuses on using novel contact resistance structures to measure the variation in electrical parameters for rapid thermally nitrided titanium films annealed at different temperatures. The self-aligned silicide (salicide) junctions in this study were formed using rapid thermally annealed titanium films. Electrical contact resistance testers were used to measure the interface contact resistance between the salicide and silicon, as well as between the metal and the salicide. The results show that the interface contact resistance to the p⁻ diffused salicided junctions increases with rapid thermal nitridation of the additional titanium film, whereas the interface contact resistance to the n⁻ diffused salicided junction shows a decrease. Further, as a function of the rapid thermal annealing temperature (for fixed titanium thickness), the nonsalicided diffusions show an increase in the interface contact resistance. The boron profiles at the TiSi₂/Si interface obtained using secondary ion mass spectroscopy show an excellent qualitative agreement with the electrical results for each of the conditions discussed. The films were also characterized using Rutherford back-scattering spectrometry and transmission electron microscopy and the results show good agreement with the measured variation in electrical parameters. These results also show that as the anneal temperature is increased, the TiN thickness increases, further the change in the silicide/silicon interface position with the nitridation of the additional titanium layer was verified. This work was carried out when the author was working at AT&T Bell Labs     

Progress with epitaxy wrap‐through crystalline silicon thin‐film solar cells

Wafer‐Equivalents are thin‐film solar cells that use a low‐cost silicon substrate to epitaxially grow a high‐quality crystalline silicon active layer. The epitaxy wrap‐through (EpiWT) cell is a back‐contact version of the Wafer‐Equivalent that aims to increase currents and gain other benefits of back contacts. The EpiWT cell can be made in a symmetrically interdigitated configuration with 50% back emitter coverage, or using an isolation layer to lower the back emitter coverage to ∼10%, which will theoretically increase voltages. The epitaxial deposition through via holes in the substrate depends on many factors, including the sealing of the deposition chamber, and produces various thicknesses and geometrical forms of the layers in the holes. An extended process has been developed to incorporate a passivated selective emitter and the first batch has been fabricated. The best result was an efficiency of 13.2% with ∼22 µm base layer thickness. The results are limited most by the fill factors at this stage, e.g. 75% for this cell, which is due to a processing difficulty encountered with screen‐printing in via holes. A new isolation layer was tested and successfully implemented for the low back‐emitter configuration. Comparable voltages and currents were achieved but the fill factors were lower than for the 50% back emitter cells, resulting in a best efficiency of 11.2%. Copyright © 2011 John Wiley & Sons, Ltd.     

Large‐area epitaxial silicon solar cells based on industrial screen‐printing processes

Thin‐film epitaxial silicon solar cells are an attractive future alternative for bulk silicon solar cells incorporating many of the process advantages of the latter, but on a potentially cheap substrate. Several challenges have to be tackled before this potential can be successfully exploited on a large scale. This paper describes the points of interest and how IMEC aims to solve them. It presents a new step forward towards our final objective: the development of an industrial cell process based on screen‐printing for > 15% efficient epitaxial silicon solar cells on a low‐cost substrate. Included in the discussion are the substrates onto which the epitaxial deposition is done and how work is progressing in several research institutes and universities on the topic of a high‐throughput epitaxial reactor. The industrial screen‐printing process sequence developed at IMEC for these epitaxial silicon solar cells is presented, with emphasis on plasma texturing and improvement of the quality of the epitaxial layer. Efficiencies between 12 and 13% are presented for large‐area (98 cm²) epitaxial layers on highly doped UMG‐Si, off‐spec and reclaim material. Finally, the need for an internal reflection scheme is explained. A realistically achievable internal reflection at the epi/substrate interface of 70% will result in a calculated increase of 3 mA/cm² in short‐circuit current. An interfacial stack of porous silicon layers (Bragg reflectors) is chosen as a promising candidate and the challenges facing its incorporation between the epitaxial layer and the substrate are presented. Experimental work on this topic is reported and concentrates on the extraction of the internal reflection at the epi/substrate interface from reflectance measurements. Initial results show an internal reflectance between 30 and 60% with a four‐layer porous silicon stack. Resistance measurements for majority carrier flow through these porous silicon stacks are also included and show that no resistance increase is measurable for stacks up to four layers. Copyright © 2005 John Wiley & Sons, Ltd.     

Comparison of TiO2 and other dielectric coatings for buried‐contact solar cells: a review

This paper compares the optical, electronic, physical and chemical properties of dielectric thin films that are commonly used to enhance the performance of bulk silicon photovoltaic devices. The standard buried‐contact (BC) solar cell presents a particularly challenging set of criteria, requiring the dielectric film to act as: (i) an anti‐reflection (AR) coating; (ii) a film compatible with surface passivation; (iii) a mask for an electroless metal plating step; (iv) a diffusion barrier for achieving a selective emitter; (v) a film with excellent chemical resistance; (vi) a stable layer during high‐temperature processing. The dielectric coatings reviewed here include thermally grown silicon dioxide (SiO₂), silicon nitride deposited by plasma‐enhanced chemical vapour deposition (a‐ SiN_x :H) and low‐pressure chemical vapour deposition (Si₃N₄), silicon oxynitride (SiON), cerium dioxide (CeO₂), zinc sulphide (ZnS), and titanium dioxide (TiO₂). While TiO₂ dielectric coatings exhibit the best optical performance and a simple post‐deposition surface passivation sequence has been developed, they require an additional sacrificial diffusion barrier to survive the heavy groove diffusion step. A‐ SiN_x :H affords passivation through its high fixed positive charge density and large hydrogen concentration; however, it is difficult to retain these electronic benefits during lengthy high‐temperature processing. Therefore, for the BC solar cell, Si₃N₄ films would appear to be the best choice of dielectric films common in industrial use. Copyright © 2004 John Wiley & Sons, Ltd.     

The thermal stability of ohmic contact to n-type InGaAs layer

The thermal stability of ohmic contact to n-type InGaAs layer is investigated. When Ni/Ge/Au is used as the contact metal, the characteristics of the ohmic contact are degraded after thermal treatment. The specific contact resistance of (Ni/Ge/Au)-InGaAs ohmic contact after annealing at 450°C is about 15 times larger than that of as-deposited sample. This is due to the decomposition of InGaAs and the interdiffusion of Ga and Au. A new phase of Au₄ln appears after annealing at 300°C. While in the case of Ti/Pt/Au, Au does not penetrate into the InGaAs layer as revealed by secondary ion mass spectroscopy. The specific contact resistance of (Ti/Pt/Au)-InGaAs ohmic contact after annealing at 450°C is eight times larger than that of as-deposited sample. Therefore, the thermal stability of (Ti/Pt/Au)-InGaAs ohmic contact is better than that of (Ni/Ge/Au)InGaAs ohmic contact.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Advanced tungsten plug process for beyond nanometer technology

This investigation elucidates various tungsten (W) nucleation layers in different W-plug fill processes. Four W-plug nucleation layers are evaluated. They involve an atomic layer deposition (ALD) W nucleation with SiH₄-base sequential nucleation layers, an ALD W nucleation with B₂H₆-base sequential nucleation layers, a conventional W chemical vapor deposition (CVD) nucleation layer, and a pulsed nucleation layer, respectively. Bulk deposition includes high pressures of 300 Torr and conventionally 90 Torr with hydrogen as a reductant of WF₆. A scanning electron microscopic analysis of the ALD W nucleation layer is conducted; it is a thin, smooth and dense film, which enhances the bulk deposition grain growth to increase grain size with low resistivity. Electrical results for ALD W processes are comparable to those for conventional W process in general barrier process condition. However, as the W-plug fills process on the weak and thin metal organic chemical vapor deposited (MOCVD) TiN barrier is varied, the ALD W processes retain their original electrical resistance performance. Unlike ALD W processes, the conventional W CVD suffers from serious contact resistance opening and tail bits. Transmission electron microscope profiles reveal that the thin and dense B₂H₆-base sequential nucleation layers prevent WF₆ molecular penetration through the TiN/Ti_x interface. Additionally, various W-plug fill processes are implemented in the tungsten damascene test vehicle, and the ALD B₂H₆-base sequential nucleation layers and subsequently formed bulk deposition at 300 Torr have lower resistance than under other conditions. The contact profile obtained using the transmission electron microscope reveals that the ALD B₂H₆-base W-plug has favorable fill-in capability for both 100 nm and 60 nm contact sizes. Their lower resistivity and thinner nucleation layer suit them in particular to implement at a contact size of 100 nm and smaller. The ALD B₂H₆-base sequential nucleation layers and subsequently formed bulk deposition at 300 Torr can be used in the next generation of W-plug fill process.     

On contact resistance measurement using four-terminal Kelvinstructures in advanced double-polysilicon bipolar transistor processes

The contact between a polycrystalline silicon (polysilicon) layer and a silicon substrate is investigated for an advanced double-polysilicon bipolar transistor process. Contact resistances are measured using four-terminal cross bridge Kelvin structures. The specific contact resistivity of the interface and the sheet resistance of the doped substrate region directly underneath the contact are extracted using a two-dimensional simulation model originally developed for metal-semiconductor contacts. The extracted sheet resistance values are found to be larger than those measured using van der Pauw structures combined with anodic oxidation and oxide removal. During the fabrication of the contacts, epitaxial realignment of the polysilicon in accordance to the substrate orientation and severe interdiffusion of dopants across the interface take place, which complicate the characterization. The validity of the two-dimensional simulation model applied to the poly-mono silicon contact is discussed     

Textured silicon surface passivation by high‐rate expanding thermal plasma deposited SiN and thermal SiO2/SiN stacks for crystalline silicon solar cells

Expanding thermal plasma (ETP) deposited silicon nitride (SiN) with optical properties suited for the use as antireflection coating (ARC) on silicon solar cells has been used as passivation layer on textured monocrystalline silicon wafers. The surface passivation behavior of these high‐rate (>5 nm/s) deposited SiN films has been investigated for single layer passivation schemes and for thermal SiO₂/SiN stack systems before and after a thermal treatment that is normally used for contact‐firing. It is shown that as‐deposited ETP SiN used as a single passivation layer almost matches the performance of a thermal oxide. Furthermore, the SiN passivation behavior improves after a contact‐firing step, while the thermal oxide passivation degrades which makes ETP SiN a better alternative for single passivation layer schemes in combination with a contact‐firing step. Moreover, using the ETP SiN as a part of a thermal SiO₂/SiN stack proves to be the best alternative by realizing very low dark saturation current densities of <20 fA/cm² on textured solar‐grade FZ silicon wafers and this is further improved to <10 fA/cm² after the anneal step. Optical and electrical film characterizations have also been carried out on these SiN layers in order to study the behavior of the SiN before and after the thermal treatment. Copyright © 2008 John Wiley & Sons, Ltd.     

On the source of scatter in contact resistance data

Previous treatments have assumed that small fluctuations in contact window dimensions between devices are chiefly responsible for the scatter in contact resistance data. Although this is plausible, it is shown in this paper that the source of this scatter is variation in contact resistivity, ρ_c, from resistor to resistor. It is further suggested that ρ_c is Cauchy distributed. Since standard deviation is in theory infinite for a Cauchy distribution, very high values of resistance at a contact window would occur with much greater frequency than common sense might suggest.     

Titanium Disilicide as High-Temperature Contact Material for Thermoelectric Generators

Thermoelectric devices can be used to capture electric power from waste heat in a variety of applications. The theoretical efficiency rises with the temperature difference across the thermoelectric generator (TEG). Therefore, we have investigated contact materials to maximize the thermal stability of a TEG. A promising candidate is titanium disilicide (TiSi₂), which has been well known as a contact material in silicon technology for some time, having low resistivity and thermal stability up to 1150 K. A demonstrator using highly doped silicon as the thermoelectric material has been integrated. A p- and an n-type wafer were oxidized and bonded. After cutting the wafer into pieces, a 200-nm-thick titanium layer was sputtered onto the edges. After a 750°C rapid thermal annealing step, the TEG legs were connected by a highly conductive TiSi₂ layer. A TEG with 12 thermal couples was integrated, and its joint resistance was found to be 4.2 Ω. Hence, we have successfully demonstrated a functional high-temperature contact for TEGs up to at least 900 K. Nevertheless, the actual thermal stability will be even higher. The process could be transfered to other substrates by using amorphous silicon deposited by plasma-enhanced chemical vapor deposition.