A Wavelet Based Hybrid Threshold Transform Method for Speech Intelligibility and Quality in Noisy Speech Patterns of English Language

The paper proposes a method to improve the performance of speech communication system in a highly noisy industrial environment. For the improvement, different speech signals are considered which includes signals from different environments such as car noise, railway station, babble noise, street noise which are corrupted with additional noise as input data set for processing. This database is processed using suitable filters which will remove the effect of noise to some extent. Different algorithms have been proposed to minimize the effect of noise to a certain limit. The denoising algorithms are generally the different wavelet thresholding method which removes the noise from the speech signal. Many researchers have worked on soft and hard thresholding for image processing. The proposed method of hybrid thresholding comprises of both soft and hard thresholding process which is comparatively better method than the previous methods. The method can be implemented for the non-stationary noise and it also removes the problems of edges. Unlike the traditional way of using single value, different values are used for the adaptive filtering to remove the edges. During the course of experiments, the dataset of IIIT-H with a set of noisy files from Noizeus and AURORA database having sampling rate of 16 kHz has been used. Results are calculated with subjective and objective measures for fine and broad level quality assessment. SNR, SSNR, PSNR, NRMSE, and PESQ parameters are used as performance parameters and outperform with other combinations as compared to conventional methods. The hybrid threshold method yields better results with significant improvement in speech quality and intelligibility.

     

Robust Perceptual Wavelet Packet Features for Recognition of Continuous Kannada Speech

An ASR system is built for the Continuous Kannada Speech Recognition. The acoustic and language models are created with the help of the Kaldi toolkit. The speech database is created with the native male and female Kannada speakers. The 80% of collected speech data is used for training the acoustic models and 20% of speech database is used for the system testing. The Performance of the system is presented interms of Word Error Rate (WER). Wavelet Packet Decomposition along with Mel filter bank is used to achieve feature extraction. The proposed feature extraction performs slightly better than the conventional features such as MFCC, PLP interms of WRA and WER under uncontrolled conditions. For the speech corpus collected in Kannada Language, the proposed features shows an improvement in Word Recognition Accuracy (WRA) of 1.79% over baseline features.

     

Mining of High-Utility Patterns in Big IoT-based Databases

When focusing on the general area of data mining, high-utility itemset mining (HUIM) can be defined as an offset of frequent itemset mining (FIM). It is known to emphasize more factors critically, which gives HUIM its intrinsic edge. Due to the flourishing development of the IoT technique, the uncertainty patterns mining is also attractive. Potential high-utility itemset mining (PHUIM) is introduced to reveal valuable patterns in an uncertainty database. Unfortunately, even though the previous methods are all very effective and powerful to mine, the potential high-utility itemsets quickly. These algorithms are not specifically designed for a database with an enormous number of records. In the previous methods, uncertainty transaction datasets would be load in the memory ultimately. Usually, several pre-defined operators would be applied to modify the original dataset to reduce the seeking time for scanning the data. However, it is impracticable to apply the same way in a big-data dataset. In this work, a dataset is assumed to be too big to be loaded directly into memory and be duplicated or modified; then, a MapReduce framework is proposed that can be used to handle these types of situations. One of our main objectives is to attempt to reduce the frequency of dataset scans while still maximizing the parallelization of all processes. Through in-depth experimental results, the proposed Hadoop algorithm is shown to perform strongly to mine all of the potential high-utility itemsets in a big-data dataset and shows excellent performance in a Hadoop computing cluster.

     

Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.     

Enhancing sensitivity-based power reduction for an industry IC design context

For many years, discrete gate sizing has been widely used for timing and power optimization in VLSI designs. The importance of gate sizing optimization has been emphasized by academia for many years, especially since the 2012/2013 ISPD gate sizing contests [1, 2]. These contests have provided practical impetus to academic sizers through the use of realistic constraints and benchmark formats. At the same time, due to simplified delay/power Liberty models and timing constraints, the contests fail to address real-world criteria for gate sizing that are highly challenging in practice. We observe that lack of consideration of practical issues such as electrical and multi-corner constraints – along with limited sets of benchmarks – can misguide the development of contest-focused academic sizers. Thus, we study implications of the “gap” between academic sizers and product design use cases. In this paper, we note important constraints of modern industrial designs that are generally not comprehended by academic sizers. We also point out that various optimization techniques used in academic sizers can fail to offer benefits in product design contexts due to differences in the underlying optimization formulation and constraints. To address this gap, we develop a new robust academic sizer, Sizer, from a fresh implementation of Trident [3]. Experimental results show that Sizer is able to achieve up to 10% leakage power and 4% total power reductions compared to leading commercial tools on designs implemented with foundry technologies, and 7% leakage power reduction on a modern industrial design in the multi-corner multi-mode (MCMM) context.     

Simultaneous driver and wire sizing for performance and poweroptimization

In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective functions: i) delay minimization only, or ii) combined delay and power dissipation minimization. We present general formulations of the SDWS problem under these two objectives based on the distributed Elmore delay model with consideration of both capacitive power dissipation and short-circuit power dissipation. We show several interesting properties of the optimal SDWS solutions under the two objectives, including an important result which reveals the relationship between driver sizing and optimal wire sizing. These results lead to polynomial time algorithms for computing the lower and upper bounds of optimal SDWS solutions under the two objectives, and efficient algorithms for computing optimal SDWS solutions under the two objectives. We have implemented these algorithms and compared them with existing design methods for driver sizing only or independent driver and wire sizing. Accurate SPICE simulation shows that our methods reduce the delay by up to 12%-49% and power dissipation by 26%-63% compared with existing design methods     

Specific accelerating factor: One more tool in motor sizing projects

This work is focused on improvement of motor sizing methods based on the accelerating factor [4]. This quantity is used to seek commercial motor–gearbox couples for mechatronics; unfortunately, it does not allow comparison of different acceptable solutions. The designer must therefore make a choice based on experience, instinct and poor data of catalogues. A per-unit-length value of the accelerating factor (specific accelerating factor) gives instead a rough but consistent idea of a servo-motor quality, for a more systematic and thoughtful selection. The specific accelerating factor represents a “benchmark” for a motor, it’s easy to calculate from datasheets and was defined using well known notions of electromechanical design (under certain assumptions).     

Useful-Skew Clock Routing with Gate Sizing for Low Power Design

This paper presents a new problem formulation and algorithm of clock routing combined with gate sizing for minimizing total logic and clock power. Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that only positive skew should be minimized while negative skew is useful in that it allows a timing budget larger than the clock period for gate sizing. We construct an useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes together form the feasible solution space of our problem. Inspired by the Deferred-Merge Embedding (DME) approach, we devise a merging segment perturbation procedure to explore various tree configurations which result in correct clock operation under the required period. Because of the large number of feasible configurations, we adopt a simulated annealing approach to avoid being trapped in a local optimal configuration. This is complemented by a bi-partitioning heuristic to generate an appropriate connection topology to take advantage of useful skews. Experimental results of our method have shown 12% to 20% total power reduction over previous methods of clock routing with zero-skew or a single fixed skew bound and separately sizing logic gates. This is achieved at no sacrifice of clock frequency.     

Efficient algorithm for glitch power reduction [CMOS logiccircuits]

An efficient algorithm is proposed for reducing glitch power dissipation in CMOS logic circuits. The proposed algorithm takes a path balancing approach that is achieved using gate sizing and buffer insertion methods. The gate sizing technique reduces not only glitches but also the effective circuit capacitance. After gate sizing, buffers are inserted into the remaining unbalanced paths which have not been subjected to gate sizing. ILP has been employed to determine the location of inserted buffers. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show that 61.5% of glitches are reduced on average     

An Efficient Approach for Enhancing Contrast Level and Segmenting Satellite Images: HNN and FCM Approach

Satellite image segmentation has gotten bunches of consideration of late because of the accessibility of commented on high-goals image informational indexes caught by the last age of satellites. The issue of fragmenting a satellite image can be characterized as ordering (or marking) every pixel of the image as indicated by various classes, for example, structures, streets, water, etc. In this paper centered to build up a satellite image segmenting process by utilizing distinctive optimization methods. The work is prepared dependent on three stages that are RGB change, preprocessing, and division. At first the database images are assembled from the database at that point select the blue band images by performing RGB change. To improve the differentiation and furthermore decreasing the commotion of these chose blue band images, Hopfield neural network (HNN) is utilized. After image upgrade, the images are fragmented dependent on fuzzy C means (FCM) clustering method. The images are clustered and segmented in the way of optimizing the centroid in FCM utilizing oppositional crow search algorithm. The exhibition of the proposed framework is investigated dependent on the presentation measurements, for example, affectability, particularity and accuracy. From the outcomes, the proposed strategy diminished the computational time by expanding the accuracy of 98.3% with HNN system.

     

Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer

This paper presents a new design of a grounded active inductor (AI) with an improved topology based on Manetakis regulated cascode active inductor comprising of three control voltages for tunability. An additional pMOST was introduced in the design as a drain load at the output of nMOST source follower. The aim of this work is to design a CMOS AI at Ku band using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool. Firstly, a reasonable AI operating at Ku band was manually designed using a 130 nm technology. This circuit and its design variables were fed to AIDA-C as an element of the initial population. Then the sizing of the proposed AI MOSTs was optimized. AIDA-C circuit sizing tool is able to achieve not only one but a set of solutions for the AI exhibiting high quality factor at a predefined Ku band operating frequency. This set of alternative Pareto optimal solutions enables the designer to choose the most suitable circuit sizing for a given application. AI’s main performance parameters in terms of s parameters (s₁₁), quality factor (Q), inductance value (L), linearity, noise figure, power consumption and tunability based on control and biasing voltages are presented. Layout of the optimized AI is also presented. This AI was used to design active filters. Their selectivity, insertion losses and noise analysis is presented and discussed.     

Generalized Simulation-Based Posynomial Model Generation for Analog Integrated Circuits

This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. Both the coefficient set as well as the exponent set of the posynomial expression, for some performance as a function of the design variables, are determined based on performance data extracted from SPICE simulation results with device-level accuracy. Techniques from design of experiments (DOE) are used to generate an optimal set of sample points to fit the models. We will prove that the optimization problem formulated for this problem typically corresponds to a non-convex problem, but has no local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows to automatically generate an accurate sizing model that can be used to compose a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming nature of hand-crafted analytic model generation. Experimental results illustrate the capabilities of the presented modeling technique.     

Upgrading Information Security and Protection for Palm-Print Templates

Biometric systems proven to be one of the most reliable and robust method for human identification. Integration of biometrics among the standard of living provokes the necessity to vogue secure authentication systems. The use of palm-prints for user access and authentication has increased in the last decade. To give the essential security and protection benefits, conventional neural networks (CNNs) has been bestowed during this work. The combined CNN and feature transform structure is employed for mapping palm-prints to random base-n codes. Further, secure hash algorithm (SHA-3) is used to generate secure palm-print templates. The proficiency of the proposed approach has been tested on PolyU, CASIA and IIT-Delhi palm-print datasets. The best recognition performance in terms of Equal Error Rate (EER) of 0.62% and Genuine Acceptance Rate (GAR) of 99.05% was achieved on PolyU database.

     

Gate sizing using geometric programming

A two-step transistor sizing optimization method based on geometric programming for delay/area minimization is presented. In the first step, Elmore delay is minimized using only minimum and maximum transistor size constraints. In the second step, the minimized delay found in the previous step is used as a constraint for area minimization. In this way, our method can target simultaneously both delay and area reduction. Moreover, by relaxing the minimized delay, one may further reduce area with small delay penalty. Gate sizing may be accomplished through transistor sizing tying each transistor inside a cell to a same scale factor. This reduces the solution space, but also improves runtime as less variables are necessary. To analyze this tradeoff between execution time and solution quality a comparison between gate sizing and transistor sizing is presented. In order to qualify our approach, the ISCAS??85 benchmark circuits are mapped to a 45?nm technology using a typical standard cell library. Gate sizing and transistor sizing are performed considering delay minimization. Gate sizing is able to reduce delay in 21?%, on average, for the same area and power values of the sizing provided by standard-cells library. Then, the transistor sizing is executed and delay can be reduced in 40.4?% and power consumption in 2.9?%, on average, compared to gate sizing. However, the transistor sizing takes about 23 times longer to be computed, on average, using a number of variables twice higher than gate sizing. Gate sizing optimizing area is executed considering a delay constraint. Three delay constraints are considered, the minimum delay given by delay optimization and delay 1 and 5?% higher than minimum delay. An energy/delay gain (EDG) metric is used to quantify the most efficient tradeoff. Considering the minimum delay, area (power) is reduced in 28.2?%, on average. Relaxing delay by just 1?%, area (power) is reduced in 41.7?% and the EDG metric is 41.7. Area can be reduced in 51?%, on average, relaxing delay by 5?% and EDG metric is 10.2.     

Locality-sensitive kernel sparse representation classification for face recognition

In this paper a new classification method called locality-sensitive kernel sparse representation classification (LS-KSRC) is proposed for face recognition. LS-KSRC integrates both sparsity and data locality in the kernel feature space rather than in the original feature space. LS-KSRC can learn more discriminating sparse representation coefficients for face recognition. The closed form solution of the l₁-norm minimization problem for LS-KSRC is also presented. LS-KSRC is compared with kernel sparse representation classification (KSRC), sparse representation classification (SRC), locality-constrained linear coding (LLC), support vector machines (SVM), the nearest neighbor (NN), and the nearest subspace (NS). Experimental results on three benchmarking face databases, i.e., the ORL database, the Extended Yale B database, and the CMU PIE database, demonstrate the promising performance of the proposed method for face recognition, outperforming the other used methods.     

An Expert Approach for Data Flow Prediction: Case Study of Wireless Sensor Networks

The data flow is an important parameter used in the optimization problem of Wireless Sensor Networks. This paper presents an expert approach for improved data flow prediction based on data discretization and artificial intelligence. The proposed approach has been implemented on various machine learning methods (a total of 17 methods). This data flow prediction is based on the dataset generated from the simulations with NS-2.35 for multiple Wireless Sensor Networks (5- to -50 nodes). The performance comparison of different machine learning models with continuous data and discretized data is also presented. The proposed approach considerably reduces the execution time of the machine learning models for training purposes and also enhances the accuracy of prediction. The result analysis shows that the proposed approach is better compared to various machine learning methods. Also, the proposed approach is able to handle both continuous and discrete data. The datasets used in this work are available as a supplement at NDS and DDS link.

     

An Enhanced Extension to Wilkinson's Equivalent Random Technique with Application to Traffic Engineering

In this paper we present an enhanced extension to Wilkinson's equivalent random technique that allows one to easily compute the different levels of blocking that various streams of traffic see using the same trunk group. This empirical extension is based on a regression analysis and is superior to a similar extension by Katz. An application of our extension to system sizing problems in AUTOVON is presented. Previous sizing methods in the AUTOVON access area did not properly account for the peakedness of overflow traffic and thereby violated desired grades of service. The methods presented here overcome this problem, and yield a lower cost solution using fewer two-way trunks.