Wideband HEMT MMIC low-noise amplifier with temperaturecompensation

A wideband low-noise pseudomorphic HEMT MMIC variable-gain amplifier has been designed and fabricated. The amplifier has a nominal gain of 13 dB across the band 2-20 GHz, with gain flatness better than ±0.4 dB. The noise figure is less than 3 dB across the band 6-16 GHz. An on-chip temperature-sensing diode is used to provide a linear temperature correction which has been used to reduce the gain variation of the amplifier by a factor of 2 across the temperature range -50°C to +95°C     

Current source load for HBT low-noise-amplifier linearisation at 1.8 GHz

A novel method employing a current source load lineariser is introduced to enhance the nonlinear performance of an HBT low-noise amplifier. This load compensates for the nonlinear behaviour of the amplifying transistor; obtaining a highly linear amplifier, achieving an IIP3 close to 20 dB and showing an independent test tone spacing behaviour.     

Silicon-on-Insulator Low-Noise Amplifier Fabricated Using the 0.18-μm Technology

A silicon-on-insulator CMOS low-noise amplifier has been designed, fabricated using the 0.18-μm topology, and tested. The following key characteristics of this amplifier have been determined: parameter S₂₁ is no lower than 11 dB in the frequency range from 500 MHz to 1.5 GHz, and the noise factor is no higher than 4 dB at 2 GHz.     

MMIC family for DBS down-converter with pulse-doped GaAs MESFETs

A monolithic microwave integrated circuit (MMIC) family was demonstrated as a low-noise block (LNB) downconverter for use in direct broadcast satellite (DBS) receivers operating from 11.7 to 12 GHz. A 12-GHz low-noise amplifier (LNA), a 12-GHz mixer (MIX), a 10.7-GHz dielectric resonator oscillator (DRO), and a 1-GHz IF amplifier (IFA) were designed with GaAs MMIC technology. These MMIC chips were designed to form a complete LNB downconverter function with the exception of the dielectric resonator. The most significant result of this work is that practical low-noise performance can be achieved without the use of high-electron-mobility transistors (HEMTs) in a preceding stage of the MMIC LNB downconverter. Almost noise-free satellite broadcast TV pictures were seen by using a parabolic antenna, 40 cm in diameter, without needing any additional circuit adjustment     

Analysis of the input noise contribution in the noise temperature measurements

In measuring the noise temperature of a cryogenic microwave low-noise amplifier (LNA), the noise from the input thermal buffer, i.e., the coaxial cable that connects the noise source to the amplifier, needs to be correctly accounted for. With the amplifier's noise temperature approaching just a few Kelvins, the postulate used in calculating the cable's noise temperature, that the cable is homogeneous and has a linear temperature profile, commands a further inspection. This letter analyzes these assumptions and clarifies the situations in which they hold. To substantiate this Kelvin-level discretion, a LNA is designed and measured.     

A 5.2 GHz low-voltage low-noise amplifier with 0.35 μm CMOS technology

A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35?µm CMOS high-frequency model to design a fully integrated 1?V, 5.2?GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source with feedback technology is used in this circuit. The first stage of the LNA is the common-source with feedback structure and the output stage is a buffer which increases the gain somewhat. An interstage negative-impedance circuit is added between the two stages of the LNA to further enhance the overall gain and thus upgrade its performance. Mainly because of the finite Q of the inductor, the negative-impedance circuit used in this interstage can cancel the losses in the first-stage inductor load. The input and output matching network is matched to approximately 50?Ω. The simulation results show that the amplifier provides a gain of 9.48?dB, a noise figure of 4.08?dB, and draws 13.4?mW from a 1?V supply. The S11 and S22 are both lower than ?15?dB.     

A $$3\,\hbox{nV}/{\sqrt{\hbox{Hz}}}$$ rail-to-rail operational amplifier in silicon-on-sapphire with constant transconductance

This paper presents the design, fabrication, and electrical measurement results from a low-noise high-performance amplifier fabricated in the 0.5 μm silicon-on-sapphire (SOS) technology. The amplifier was designed with rail-to-rail input and output swing and constant transconductance in its entire common-mode range and targets biomedical instrumentation in SOS/SOI technologies. The amplifier reports \(3\,\hbox{nV}/{\sqrt{\hbox{Hz}}}\) of input-referred voltage noise at 10 kHz and has 0.4 mV of input-referred offset. The gain-bandwidth product of the amplifier is 12 MHz and the open-loop gain is 75 dB. The amplifier occupies 0.08 mm² of area and consumes 1.4 mW of power.     

A low-noise BiCMOS amplifier channel for telecommunications

A low-noise low-pass amplifier channel designed for telecommunications is described. The channel has an 80-kHz corner frequency and total dynamic range of 94 dB. To achieve the high dynamic range, the amplifier channel is constructed with a BiCMOS process and a relative high supply voltage of ±8V is used. To further increase the dynamic range, the baseband amplifier has two branches, a low gain (A = 29 dB) and a high gain (A = 73 dB) branch, comprising a common continuous-time preamplifier and separate antialias filters, switchedcapacitor filters, and postamplifiers. Differential signal processing is used to reduce the effect of common-mode disturbances.     

A low-noise gain-tunable amplifier for large array biopotential recording systems

This paper presents a low-noise gain-tunable biopotential amplifier that is designed based on a folded-cascode structure. Sub-threshold and self-biasing techniques are employed to achieve a low-noise and low-power amplification. With a bias-current tuning block, the gain of the proposed biopotential amplifier can be precisely adjusted. Designed in a standard 0.13 μm CMOS process, the proposed amplifier provides a 5.9 kHz bandwidth and 30.1 dB gain with 732 nW power. The input-referred noise over the entire bandwidth is 4.3 μV _rms , equivalent to a noise-efficiency factor of 2.48.     

Micropower fully integrated CMOS readout interface for neural recording application

In this paper, we presented a micropower, small-size fully integrated CMOS readout interface for neural recording system. A crucial and important module of this system is the amplifier circuit with low-power low-noise. We describe a micropower low-noise readout circuit using an active feedback fully differential structure to reject the 1/f noise and large DC-offsets, the substrate-bias technology to further decrease the noise and power of the neural recording amplifier. Therefore, the neural amplifier with micropower low-noise and high input impedance is presented. The readout interface core, fully differential amplifier is implemented in 0.35-μm CMOS process, passes neural signals from 10 Hz to 9 kHz with an input-referred noise of 4.3 μV_rms. The power consumption of single amplifier is 5.6 μW while consuming 0.03 mm² of die area. The low cutoff frequencies of the circuit can adjusted from 10 Hz to 400 Hz, and the high cutoff frequencies form 4 kHz to 9 kHz.     

Parametric amplifier using a silver bonded diode

Recently, the parametric amplifier has merited attention because of its low-noise characteristics. A novel diode has been designed which is suitable for use in a parametric amplifier. The diode is a bonded type and is composed of a silver-gallium whisker and an N-type germanium. The cutoff frequency of the silver bonded diode is higher than 150 kMc. The parametric amplifier was made using these diodes at 6 kMc and 11 kMc, and stable gain of more than 20 db was obtained. The noise figures were approximately 5 db and 6.5 db at 6 kMc and 11 kMc, respectively.     

Analysis of the Survivability of GaN Low-Noise Amplifiers

This paper presents a detailed analysis of the stressing mechanisms for highly rugged low-noise GaN monolithic-microwave integrated-circuit amplifiers operated at extremely high input powers. As an example, a low-noise amplifier (LNA) operating in the 3-7-GHz frequency band is used. A noise figure (NF) below 2.3 dB is measured from 3.5 to 7 GHz with NF<1.8 dB between 5-7 GHz. This device survived 33 dBm of available RF input power for 16 h without any change in low-noise performance. The stress mechanisms at high input powers are identified by systematic measurements of an LNA and a single high electron-mobility transistor in the frequency and time domains. It is shown that the gate dc current, which occurs due to self-biasing, is the most critical factor regarding survivability. A series resistance in the gate dc feed can reduce this gate current by feedback, and may be used to improve LNA ruggedness     

可调增益均衡性宽带MMIC低噪声放大器设计

文章提出了一种新颖的具有可调增益均衡特性的宽带全单片低噪声放大器电路设计方法,它将用于微波功率模块(MPM)的固态功率放大器(SSPA)链前端中的两项功能独立的电路(多级单片宽带低噪声放大器LNA和单片宽带频率均衡放大器FEA)组合设计在一块单片电路芯片中。其中LNA部分采用高效率高增益宽带级联型分布放大器取代常规的行波式分布放大器,使得放大器级数显著减少;频率均衡放大器提出用一种利用FET作可调元件的嵌入式低损无源网络来取代,使得放大器的增益特性在频带中部下凹可调,补偿了行波管“山丘状”功率增益特性。在此基础上完成设计的 MMIC LNA,仅使用3个0．25μm×120μm pHEMT,在6GHz～18GHz频带内,小信号增益14．3 ±0．8 dB,输入、输出反射损耗<-10 dB,NF<5 dB;嵌入可调增益均衡网络后,在其他性能参数基本保持不变的前提下,频带中部引入的电调衰减范围超过6．5 dB,完全满足MPM要求。     

A direct-conversion receiver for the 3G WCDMA standard

A highly integrated direct-conversion receiver that satisfies requirements of the third-generation wide-band code-division multiple-access mobile phone standard is described. The receiver integrated circuit includes the front-end low-noise amplifier, downconversion mixers, baseband variable-gain amplifiers, channel-select filters, and the frequency synthesizer. External components are limited to matching elements required for the low-noise amplifier and the mixers and two passive band-select filters. The receiver is implemented in a SiGe BiCMOS process and consumes a total current of 46 mA from a 2.7-V supply.     

110-120-GHz monolithic low-noise amplifiers

The authors discuss the development of 110-120-GHz monolithic low-noise amplifiers (LNAs) using 0.1-mm pseudomorphic AlGaAs/InGaAs/GaAs low-noise HEMT technology. Two 2-stage LNAs have been designed, fabricated, and tested. The first amplifier demonstrates a gain of 12 dB at 112 to 115 GHz with a noise figure of 6.3 dB when biased for high gain, and a noise figure of 5.5 dB is achieved with an associated gain of 10 dB at 113 GHz when biased for low-noise figure. The other amplifier has a measured small-signal gain of 19.6 dB at 110 GHz with a noise figure of 3.9 dB. A noise figure of 3.4 dB with 15.6-dB associated gain was obtained at 113 GHz. The authors state that the small-signal gain and noise figure performance for the second LNA are the best results ever achieved for a two-stage HEMT amplifier at this frequency band     

集成运算放大器同相和反相形式的En-In噪声分析和比较

本文通过分析和比较同相和反相放大器E_n-I_n噪声的特点,给出了若干新结果。本文方法在低噪声运放电路设计和运放噪声参数提取中都具有十分重要的意义。     

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier(LNA) and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm~2 die size.     

Full-band staggered-gain Gunn-effect amplification in Ka band

The feasibility of full-band low-noise instantaneous amplification in Ka band has been demonstrated using a staggered-gain amplifier technique. A simplified analysis of the overall gain variations in this two-stage amplifier is used to calculate the minimum isolation levels needed to meet a maximum allowable ripple. Using this technique, 10 ± 2.2-dB gain has been obtained from 26.6-39.4 GHz.     

雷达中频放大器的线性对数双特性设计

雷达数字中频接收机需要一个线性中频预放大电路和一个监测用的对数中频放大器。采用射频变压器形成输入匹配网络,采用高性能低噪声宽带差分放大器AD8350作为线性放大器件,采用双调谐回路作为选频网络,采用魔T电路构成功率分配网络,采用高动态范围宽带对数放大器AD8309作为对数放大器件,设计了一个兼具线性和对数特性的中频放大器。实验表明,该放大器中频输入输出阻抗50Ω,中心频率30 MHz,带宽4 MHz。线性通道增益为18 dB,输出动态范围达98 dB(1 dB压缩点-90 dBm和+8 dBm)。对数通道中,在输入功率为-68 dBm～-8 dBm时,对数放大器输出电压范围对应为0.19 V～2.06 V。     

A 7-GHz 1.8-dB NF CMOS low-noise amplifier

A 7-GHz low-noise amplifier (LNA) was designed and fabricated using 0.25-μm CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads were adopted to improve the gain and the noise performance. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. An associated gain of 8.9 dB, a minimum noise figure of 1.8 dB, and an input-referred third-order intercept point of +8.4 dBm were obtained at 7 GHz. The LNA consumes 6.9 mA from a 2.0-V supply voltage. These measured results indicate the feasibility of a CMOS LNA employing these techniques for low-noise and high-linearity applications at over 5 GHz