A V-band quasi-optical GaAs HEMT monolithic integrated antenna and receiver front end

A single-chip monolithic integrated V-band folded-slot antenna with two Schottky-barrier diodes and a local oscillator source is developed as a quasi-optical receiver for the first time. The monolithic microwave integrated circuit consists of a voltage-controlled oscillator (VCO), a coplanar waveguide (CPW)-to-slotline transition, a low-pass filter, a folded-slot antenna, and a 180/spl deg/ single balanced mixer. The chip is fabricated based on the 0.15-/spl mu/m GaAs high electron-mobility transistor technology and the overall chip size is 3/spl times/1.5 mm/sup 2/. A finite-difference time-domain method solver is also developed for analyzing the embedded impedance characteristics of the folded-slot antenna to design the mixer. The chip is placed on an extended hemispherical silicon substrate lens to be a quasi-optical receiver. The performance of the receiver is verified by experimental measurements. The VCO has achieved a tuning range from 61.9 to 62.5 GHz and approximately 9.3-dBm output power. The CPW-to-slotline transition has bandwidth from 50 to 70 GHz. The mixer results in 15-dB single-sideband conversion loss and the receiving patterns of the IF power are also measured.     

A Ku-band integrated receiver front end

A Ku-band integrated receiver front end has been fabricated on 20-mil aluminum oxide substrates. The receiver consists of a balanced mixer and a Gunn oscillator within an area of 0.300/spl times/0.325 inch. The performance of both packaged and unpackaged microstripline receivers is described. Using external RF tuning, a noise figure of 9 dB at 18 GHz was obtained. A higher Q Gunn oscillator design is needed for more reliable single-frequency operation.     

Quasi-optical antenna duplexers

The development of antenna duplexers for transceiving quasi-optical systems of millimeter and submillimeter wavelengths are considered for two groups of devices — passive and active action. Duplexers, using properties of quasi-optical hybrids, belong to the first group, and duplexers on the base of semiconductor or ferrite devices are included to the second group. Results of developments and investigations of considered devices in the millimeter wave range are presented.     

2.5 Gb/s GaAs PIN/PHEMT单片集成光接收机前端

采用0.5 μm GaAs PHEMT工艺,研制了一种PIN光探测器和分布放大器单片集成850 nm光接收机前端. 探测器光敏面直径为30 μm,电容为0.25 pF,10 V反向偏压下的暗电流小于20 nA.分布放大器-3 dB带宽接近20 GHz,跨阻增益约46 dBΩ;在50 MHz～16 GHz范围内,输入、输出电压驻波比均小于2;噪声系数在3.03～6.50 dB之间.单片集成光接收机前端在1.0和2.5 Gb/s非归零(NRZ)伪随机二进制序列(PRBS)调制的光信号下得到较为清晰的输出眼图.     

A monolithic GaAs-on-Si receiver front end for optical interconnectsystems

The authors describe a monolithic technology for integrating GaAs with Si bipolar devices and demonstrate that such integration can provide improved system performance without degrading individual devices. The technology has been used to implement a 1-GHz GaAs/Si optical receiver with an equivalent input noise current density of less than 3 pA/√Hz for midband operation, and less than 4.5 pA/√Hz at 1 GHz. In this receiver an interdigitated GaAs metal-semiconductor-metal (MSM) photodetector is combined with a transimpedance preamplifier fabricated in silicon bipolar technology. The measured dark current of the GaAs/Si photodetector is 7 nA. The measured pulse response of an experimental integrated receiver is less than 550 ps FWHM. The integrated front end provides a wideband, low-noise optical receiver for use in local optical interconnections and demonstrates the successful application of integrated GaAs-on-Si technology to optoelectronics     

A 5-GHz CMOS wireless LAN receiver front end

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-μm CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm     

Quasi-optical slot antenna SIS mixers

A quasi-optical SIS mixer designed for efficient radiation coupling is described. The mixer uses a twin-slot antenna which has the advantages of a good beam pattern and a low impedance. The radiation and impedance characteristics of the antenna were obtained from a moment-matched calculation. Tapered superconducting microstrip transmission lines are used to carry the radiation from the slot antennas to the tunnel junction. The effective impedance seen by the tunnel junction is quite low, about 4 Ω, which allows micron-size junctions to be used at 500 GHz. The mixers have been fabricated using Nb/Al-oxide/Nb tunnel junctions and a receiver noise temperature of 420 K (DSB) was measured at 490 GHz, which is the best yet obtained for a quasi-optical mixer at this frequency. The comparatively large junction area increases the mixer saturation power and allows strong suppression of noise from the Josephson effect by the application of a magnetic field of modest strength     

Monolithically integrated receiver front end: In0.53Ga0.47As p-i-n amplifier

Monolithically integrated InGaAs p-i-n amplifiers have been successfully fabricated. The structure utilizes a vertical integration of a p-i-n diode and recessed-gate InP MISFETs, while maintaining a planar surface for fine-line photolithography. The preamplifier consists of a gain stage and a buffer stage, both made of InP MISFETs with aluminium phosphorous oxide as gate insulator. At 400 Mb/s, the receiver sensitivity is better than -27 dBm for 1×10^-9 bit error rate     

一种低功耗的高速光接收器跨阻前置电路设计

为了降低芯片面积和功耗,提出了一种10 Gb/s光接收器跨阻前置放大电路。该电路采用了两个带有可调共源共栅（RGC）输入的交叉有源反馈结构,其中的跨阻放大器未使用电感,从而减少了芯片的总体尺寸。该跨阻前置电路采用0.13μm CMOS工艺设计而成,数据速率高达10 Gb/s。测试结果表明,相比其他类似电路,提出的电路芯片面积和功耗更小,芯片面积仅为0.072mm2,当电源电压为1.3 V时,功率损耗为9.1 mW,实测平均等效输入噪声电流谱密度为20pA/（0.1-10）Hz,且-3dB带宽为6.9 GHz。     

基于星载平台的DBF体制接收前端组件研制

研制了一种应用于星载平台DBF接收机前端组件,针对其应用的特殊环境要求,给出了较详细电路设计和实现方法。通过对设计完成的电性件实测结果表明,设计实现的DBF接收前端组件具有高度的宽温稳定性和幅相一致性,同时具有高增益和低噪声系数的特点,测试结果充分证明该项技术在星载平台上应用的条件已经成熟。     

60 GHz multi-chip-module receiver with substrate integrated waveguide antenna and filter

A compact 60 GHz MCM receiver has been demonstrated by integrating millimetre-wave substrate-integrated waveguides and GaAs MMICs for the first time. The module includes a waveguide antenna and filter, MMIC LNA and mixer, and lumped elements for IF filtering embedded into the multilayer photo-imageable thick-film substrate. Cavities for MMIC attachment are photo-imaged as part of the standard process.     

无线电高度表微波集成前端

研制的4.3GHz无线电高度表微波集成前端已得到实际应用,它代替了整机原用的振荡-放大一倍频方案,提高了效率、减小了体积.微波集成前端采用了高线性度FET压控振荡器作发射源,采用高隔离度的单桥路不等负载三分贝混合环混频器.在-40°～70℃的环境温度范围内发射功率大于150mW,压控带宽123MHz,线性度小于3%,接收机噪声系数小予8dB.     

An ADSL-RT full-rate analog front end IC with integrated linedriver

An analog front end IC for ADSL systems compliant with ANSI, ITU, and ETSI standards is presented. The IC contains all analog functions on one silicon die, including programmable gain amplifiers, highly linear continuous-time filters, 14-bit DAC and ADC for up to 1.1-MHz signal bandwidth, digitally controlled crystal oscillator, and a line driver capable of delivering +13 dBm to the line. The IC has been fabricated in a mixed-signal 0.6-μm DPTM BiCMOS technology with a chip area of 29 mm² and a power consumption of only 800 mW, using 3.3-V supply for all blocks, except 12-V supply for the line driver. The high level of integration together with the low power consumption can be considered a benchmark for full-rate ADSL analog front end ICs     

An integrated Doppler-radar transceiver front end using two FETactive antennas

An integrated X-band Doppler-radar transceiver front end has been developed. This front end consists of two adjacently spaced field-effect transistor (FET) active antennas, with one of them being biased to oscillate as its transmitter and the other being biased not to oscillate, but to act as its mixer. This design has the advantage of lower noise at low Doppler frequencies as compared to a self-oscillating mixer scheme. The circuit can be used in low-power Doppler-radar systems to detect slow-moving objects such as pedestrians, intruders, automobiles, etc., with high sensitivity     

A 12-bit integrated analog front end for broadband wirelinenetworks

An integrated transceiver for broadband wireline networks is presented. The transceiver includes a receive data path, a transmit data path, and auxiliary functions including serial port interface, clock and reference generation blocks, and voltage regulator control circuitry. The receive data path provides constant input impedance and is composed of two variable gain amplifier (VGA) blocks, a tuned analog 4-pole filter, a 12-b analog-to-digital converter (ADC) sampling at 32 MHz, and a digital high-pass filter. Filter tuning using switched-capacitor arrays occurs in the background, with no effect on signal reception. The transmit data path contains digital interpolation filters and a 12-b digital-to-analog converter (DAC) sampling at 128 MHz. The chip was implemented in double-poly triple-metal 0.35-μm CMOS technology. Measured performance for both receive and transmit data paths meets target specifications with no noticeable crosstalk     

HF/VHF零中频接收机前端电路分析设计

以零中频接收机的射频前端在HF/VHF存在的问题为重点,深入研究零中频结构的射频前端结构,并通过电路设计提出解决方案,设计了基于软件无线电原理的HF、VHF双频段射频前端。通过模拟仿真,论证方案的可实现性以及所选器件能够满足设计方案的指标要求。     

基于GA的智能天线系统前端扇区阵列设计

使用遗传算法(Genetic Algorithm)设计了智能天线系统前端的扇区天线阵列。该天线阵列用于TD-SCDMA基站系统中。依据智能天线系统扇区覆盖模式(即广播波束)对方向图的要求，利用GA的全局搜索性能，综合了阵列结构及单元激励相位。对该阵列结构使用GA模拟了智能天线系统工作模式(业务波束)下所要求方向图的阵列激励幅度和相位。给出了实际的智能天线系统前端扇区天线阵列结构，对智能天线技术的应用具有重要意义。     

一种应用于GNSS接收机的无电感多模射频前端

本文设计了一种应用于GNSS接收机的无电感多模射频前端。与传统低噪声放大器结构不同,本设计使用了无电感电流模式以及利用噪声消除技术的低噪声放大器。其高阻输入的射频放大器进一步放大信号并将单端信号转为差分信号。后级无源混频器将信号下变频到中频并将信号传输到下一级的模拟电路模块。文中还有本振缓冲器实现压控振荡器的二分频和25%占空比的方波新号的产生用于控制混频器开关。测试结果表明该射频前端在1.2V电源电压下仅消耗6.7mA电流,并获得了良好的综合性能。射频前端的输入回损为-26dB,而1.43dB的低噪声系数也保证了良好的接收灵敏度。在射频前端电压增益为48dB情况下,测得的输入1dB压缩点为-43dBm。该电路采用了55nm标准CMOS工艺实现,面积非常小,仅仅为220 μm×280 μm左右。     

An integrated LMS adaptive filter of TX leakage for CDMA receiver front ends

The theory and practical implementation of a continuous-time LMS adaptive filter of the TX leakage in CDMA receivers are described. The filter works by injecting a matched out-of-phase copy of the TX leakage into the LNA output. It requires a reference signal coupled from the TX chain, whose I and Q components are appropriately scaled to generate the matched copy. The scale factors are the results of the correlation between the filter output signal and the I/Q components of the reference signal. The filter was designed as part of a 0.25-/spl mu/m CMOS cellular-band receiver. The effect of the DC offsets in the correlators on the TX leakage rejection ratio (TXRR) was minimized by using the sign-data variant of the LMS algorithm and by increasing the gain of the correlating multipliers. The loop stability margin was improved by swapping the I and Q reference inputs of the scaling multipliers. Without a significant group delay of the TX leakage relative to the reference signal, the filter achieved the maximum TXRR of 28 dB, which was limited by the reference signal coupling. The group delay introduced by the SAW duplexer reduced the minimum TXRR to 10.8 dB. The filter degraded the LNA noise factor and gain by 1.3 dB and 1.7 dB, respectively.