用新的电路形式提高HBT光调制器驱动电路的传输速率及性能

在传统光调制器驱动电路中,所用HBT截止频率的大小要达到驱动电路传输速率的4倍以上.文中在输出级采用共射共基HBT形式后,其器件的截止频率只需大于电路传输速率的2倍即可,从电路设计的角度降低了对所用器件的要求.文中分析了新的电路结构提高传输速率的原因并给出了模拟结果.同时新的电路结构也具有良好的热稳定性.     

InP基MOCVD及MBE外延生长HBT的制备与分析

设计并研制了用于光电集成(OEIC)的InP基异质结双极晶体管(HBT),介绍了工艺流程及器件结构。分别采用金属有机化学气相沉积(MOCVD)及分子束外延(MBE)生长的外延片,并在外延结构、工艺流程相同的条件下,对两种生长机制的HBT直流及高频参数进行和分析。结果表明,采用MOCVD生长的InP基HBT,直流增益为30倍,截止频率约为38GHz;MBE生长的HBT,直流增益达到100倍,截止频率约为40GHz。这表明,MBE生长的HBT外延层质量更高,在相同光刻条件下,所对应的HBT器件的性能更好。     

两种不同结构InGaP/GaAs HBT的直流特性分析

InGaP/GaAs异质结双极晶体管(HBT)是当前微波毫米波领域中具有广阔发展前景的高速固态器件,其直流特性是器件重要参数之一.本文采用Medici软件对两种InGaP/GaAs外延结构HBT的直流特性和高频特性进行了模拟计算,并实际制备出了两种材料结构的大尺寸(发射极面积100μm×100μm)双台面InGaP/GaAs HBT器件,对其直流特性进行了测试和分析,两种外延结构的器件共射直流增益分别为50和350,模拟得其最大截止频率分别为8和10GHz.     

化合物半导体器件与电路的研究进展

介绍了GaAs,InP和GaN等几种重要化合物半导体电子器件的特点、应用和发展前景。回顾了GaAs,InP和GaN材料的材料特性及其器件发展历程与现状。分别讨论了GaAs基HEMT由PHEMT渐变为MHEMT结构和性能的变化,GaAs基HBT在不同电路应用中器件的特性,InP基HEMT与HBT的器件结构及工作特性,GaN基HEMT与HBT的器件特性参数。总体而言,化合物半导体器件与电路在高功率和高频电子器件方面发展较快,GaAs,InP和GaN材料所制得的各种器件电路工作在不同的频率波段,其在相关领域发展潜力巨大。     

截止频率为45GHz的新颖电极结构的自对准HBT设计、制作和表征

文章采用二维异质结构器件模拟程序和异质结双极晶体管电路模拟程序,对新近提出的自对准AlGaAs/GaAs异质结双极晶体管(HBT)的设计、制作和模拟制定了系统的研究方法。所研制的HBT有一突变的发射极-基极异质结,并且采用一种新颖结构——在两个发射极电极之间夹入一个基极电极。对已制成的3×8μm~2双发射极HBT进行了测量,其电流增益截止频率f_T=45GHz,最高振荡频率f_(max)=18.5GHz。分频器电路模拟结果指出,研制成的HBT的速度是两个基极电极之间夹入一个发射极电极的普通HBT的1.4倍。     

共射-共基电路的高频响应分析及PSPICE仿真

对共射-共基组合放大电路的高频响应进行了详细的分析,给出了上限截止频率的简单计算方法,从密勒效应的角度对比了单管共射放大电路与共射-共基组合放大电路的上限截止频率,并利用PSPICE软件进行了仿真,仿真结果也验证了理论分析的正确性。     

截止频率为238GHz的亚微米InGaAs/InP异质结双极晶体管

研制成功了一种无微空气桥的亚微米InP基异质结双极晶体管(HBT).发展了小于100nm的发射极侧向腐蚀工艺,实现了亚微米的InP基HBT.发射极宽度的减小有效提高了频率特性,发射极面积为0.8μm×15μm的HBT的电流增益截止频率达到了238GHz.发展了基极-集电极的侧向过腐蚀工艺,有效减小了结面积,提高了最大振荡频率.Kirk电流密度达到了3.1mA/μm2.据我们所知,电流增益截止频率是目前国内三端器件中最高的,Kirk电流密度是国内报道的HBT中最高的.这对于HBT器件在超高速电路中的应用具有十分重要的意义.     

截止频率为238GHz的亚微米InGaAs/InP异质结双极晶体管

研制成功了一种无微空气桥的亚微米InP基异质结双极晶体管（HBT) . 发展了小于100nm的发射极侧向腐蚀工艺,实现了亚微米的InP基HBT. 发射极宽度的减小有效提高了频率特性,发射极面积为0.8μm×15μm的HBT的电流增益截止频率达到了238GHz. 发展了基极-集电极的侧向过腐蚀工艺,有效减小了结面积,提高了最大振荡频率. Kirk电流密度达到了3.1mA/μm2. 据我们所知,电流增益截止频率是目前国内三端器件中最高的,Kirk电流密度是国内报道的HBT中最高的. 这对于HBT器件在超高速电路中的应用具有十分重要的意义.     

高功率纳秒级激光二极管高侧驱动电路

纳秒级高功率的激光发射系统对激光雷达的探测性能产生重要影响。本文对普遍使用的激光二极管低侧栅极驱动电路进行修改得到高侧栅极驱动方式,使之能够适用于共阴极激光发射电路。该高侧驱动方式采用了一个半桥驱动器,两个GaN FET作为核心器件来控制激光二极管的发光。文中分析了该拓扑结构中电压、电容、电阻、电感等因素对流经激光器电流波形的影响。经过实验测试,在高重复频率下该电路能够产生3.1 ns脉冲宽度,约65 W的峰值功率,能够作为激光雷达的发射模块对场景进行扫描成像。     

两种不同结构InGaP/GaAs HBT的直流特性分析

InGaP/GaAs异质结双极晶体管(HBT)是当前微波毫米波领域中具有广阔发展前景的高速固态器件,其直流特性是器件重要参数之一.本文采用Medici软件对两种InGaP/GaAs外延结构HBT的直流特性和高频特性进行了模拟计算,并实际制备出了两种材料结构的大尺寸(发射极面积100μm×100μm)双台面InGaP/GaAs HBT器件,对其直流特性进行了测试和分析,两种外延结构的器件共射直流增益分别为50和350,模拟得其最大截止频率分别为8和10GHz.     

准平面型InAlAs/InGaAs异质结双极晶体管和单片集成激光器驱动电路

提出和制作了准平面型InAlAs/InGaAs异质结双极晶体管。该管主要采用硅离子注入法在半绝缘磷化铟衬底中形成隐埋型集电区以代替台面型集电区。晶体管的实测结果如下:h_(fe)=100,f_T=10GHz(V_(CE)=3V,I_c=10mA)。作为单片光电集成方面的实例,研制成功了由三个InGaAs/InAlAsHBT和一个电阻组成的激光器驱动电路,其电流调制速率高达4Gbit/s。     

两级运放中共模反馈电路的分析与设计

在两级共源共栅CMOS运算放大器中,设计了一种新的共模反馈电路。这种电路克服了一般共模反馈电路存在的限制输出摆幅的缺点,在稳定电路直流工作点的同时,能有效提高电路的输出摆幅。通过对共模电路结构的分析,证明了其功能原理的正确性。基于0.18μm(3V)CMOS工艺库,用Hspice软件对电路结构进行了仿真验证。结果显示,电路低频增益达到120dB,功耗不到0.24mW。     

用于12 bit 40 MS/s低功耗流水线ADC的采样保持电路

设计了一个可降低12 bit 40 MHz采样率流水线ADC功耗的采样保持电路。通过对运放的分时复用,使得一个电路模块既实现了采样保持功能,又实现了MDAC功能,达到了降低整个ADC功耗的目的。通过对传统栅压自举开关改进,减少了电路的非线性失真。通过优化辅助运放的带宽,使得高增益运放能够快速稳定。本设计在TSMC0.35μm mix signal 3.3 V工艺下实现,在40 MHz采样频率,输入信号为奈奎斯特频率时,其动态范围(SFDR)为85 dB,信噪比(SNDR)为72 dB,有效位数(ENOB)为11.6 bit,整个电路消耗的动态功耗为14 mW。     

超高速宽带运算放大器的设计与研制

本文叙述了新型超高速宽带运算放大器的电路设计,并对其制造工艺作了简单的介绍。电路设计是围绕高速宽带这一中心进行的。采用场效应管作输入级来提高放大器的输入动态范围,共射-共基的放大形式使中间级具有好的频率特性,还设计了输出级的大电流保护电路。根据新设计电路的特点,采用薄膜混合集成工艺。研制的运算放大器达到了较高的水平,其转换速率达到300V/μs,增益带宽乘积达100MHz。     

A current-mode bit-block circuit applicable to low-voltage, low-power pipeline video-speed A/D converters

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 m device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.     

GigaHertz MUX-DEMUX Chip with HF BIST

Full functional test at speed, in-situ is an ideal choice for use for detection of errors in circuit behaviour for high speed broadband communication circuits and to avoid test set-up disturbances on high frequency signals. This article presents a novel technique to solve the high frequency test of Gbit/s data rate Time-Division Multiplexer/Demultiplexer circuits. This in-situ test technique is based on conventional pseudo-random sequence generation and signature analysis. By linear feedback interconnect and reusable architecture the multiplexer/demultiplexer circuits can operate as generator/analyser with minimal degeneration of bit shift rate. Circuit simulation showed that the system operates correctly with a clock frequency up to 3 GHz in a silicon bipolar technology with a current gain cut-off frequency f _T = 15 GHz.     

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5 V; and ultra-low-power consumption of mere 10 μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18 μm CMOS technology are included as well to validate the functionality of the proposed circuit.     

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m².     

一个用于12位40-MS/s低功耗流水线ADC的MDAC电路设计

文中设计了一个用于12位40MHz采样率低功耗流水线ADC的MDAC电路.通过对运放的分时复用,使得一个电路模块实现了两级MDAC功能,达到降低整个ADC功耗的目的.通过对MDAC结构的改进,使得该模块可以达到12bit精度的要求.通过优化辅助运放的带宽,使得高增益运放能够快速稳定.本设计在TSMC0.35μmmixsignal3.3V工艺下实现,在40MHz采样频率下,以奈奎斯特采样频率满幅(Vpp=2V)信号输入,其SINAD为73dB,ENOB为11.90bit,SFDR为89dB.整个电路消耗的动态功耗为9mW.     

幅频特性的数学分析

根据数控装置检测系统中传感器信号电路工作要求,以共射电压放大电路为例,分别考虑耦合电容、旁路电容、结间电容和分布电容对不同信号频率的作用,分析了电路的低频特性和高频特性,给出了上下限截止频率的解析式.由此得出,电路其他参数一定时,在低频段,下限截止频率与耦合电容、旁路电容成反比,在高频段,上限截止频率与等效输入输出电容成反比,从而为传感器系统设计提供理论依据.