Ballistic magnetotransport in a suspended two-dimensional electron gas with periodic antidot lattices

The magnetoresistance of suspended semiconductor nanostructures with a two-dimensional electron gas structured by periodic square antidot lattices is studied. It is shown that the ballistic regime of electron transport is retained after detaching the sample from the substrate. Direct comparative analysis of commensurability oscillations of magnetoresistance and their temperature dependences in samples before and after suspension is performed. It is found that the temperature dependences are almost identical for non-suspended and suspended samples, whereas significant differences are observed in the nonlinear regime, caused by direct current passage. Commensurability oscillations in the suspended samples are more stable with respect to exposure to direct current, which can be presumably explained by electron–electron interaction enhancement after detaching nanostructures from the high-permittivity substrate.     

MOSFET衬底电流模型在深亚微米尺寸下的修正

建立精确的衬底电流模型是分析ＭＯＳＦＥＴ器件及电路可靠性和进行ＭＯＳＦＥＴ电路设计所必需的．在分析载流子输运的基础上建立了一个常规结构深亚微米ＭＯＳＦＥＴ衬底电流的解析模型,模型公式简单．对模型进行了验证,研究了衬底掺杂浓度与栅氧化层厚度对拟合因子的影响,并分析了模型中拟合因子的物理意义．     

GaN HFET沟道层中的慢输运电子态和射频电流崩塌

从电极偏置环境、二维异质结能带及沟道电子状态的研究出发,发现了沟道中存在具有不同输运特性的高能正常电子和低能慢电子,建立起新的慢电子电流崩塌模型。在器件射频工作中通过正常输运电子到慢电子的转换过程解释了射频电流崩塌行为。沟道中的慢电子是产生射频电流崩塌的真正缘由。运用这一慢电子电流崩塌模型解释了目前用耗尽模型不能解释的大量实验结果。最后提出了通过异质结构优化设计来消除慢电子,解决电流崩塌难题的新途径。     

Temperature dependence of MOSFET substrate current

Hitherto, theoretical models for MOSFET substrate current predicted that substrate current is a strong function of temperature. However, experimental data presented in this and previous studies show that the ratio of substrate current to drain current is insensitive to temperature over the range 77 to 300 K. The authors propose a modified model for an electron mean-free path (MFP) in the substrate current based on the concept of energy relaxation. The different between the energy and momentum relaxation MFP is clarified, and it is shown that a substrate current model with modified MFP can explain the temperature dependence of the substrate current     

A simplified computer analysis for n-well guard ring efficiency in CMOS circuits

Based on solving the 2-D continuity and current transport equations for electrons injected into the substrate of a n-well CMOS, a quantitative evaluation of n-well guard ring efficiency in terms of the escape electron current is presented. Simulation results show that in the worst-case condition Auger recombination inherent in the heavily-doped substrate of epi-CMOS is responsible for the enhancement of n-well guard ring efficiency. Also, our simulations show that the substrate doping should be as high as possible and the epi-layer thickness should be as thin as possible. Thus a narrow well-type guard ring can be used in order to make efficient use of epi-CMOS for suppressing the escape electron current to a low level so as to preclude latch-up.     

Investigation of Self-Heating Effects in Submicrometer GaN/AlGaN HEMTs Using an Electrothermal Monte Carlo Method

An electrothermal Monte Carlo (MC) method is applied in this paper to investigate electron transport in submicrometer wurtzite GaN/AlGaN high-electron mobility transistors (HEMTs) grown on various substrate materials including SiC, Si, GaN, and sapphire. The simulation method is an iterative technique that alternately runs an MC electronic simulation and solves the heat diffusion equation using an analytical thermal resistance matrix method. Results demonstrate how the extent of the thermal droop in the I_d-V_ds characteristics and the device peak temperature depend upon both the biasing conditions and the substrate material type. Polarization effects are considered in the simulations, as they greatly influence electron transport in GaN/AlGaN HEMTs by creating a highly concentrated two-dimensional electron gas (2DEG) at the GaN/AlGaN interface. It is shown that a higher 2DEG density provides the devices with a better current handling capability but also increases the importance of the thermal effects     

Hot Electrons and Hot Spins at Metal–Organic Interfaces

A model is developed to describe the electron transport properties of hot electron devices based on organic semiconductors. For the first time, the simulations cover all the different processes the carriers experience in the device, which allows disentangling various effects on the transport characteristics. The model is compared to experimental measurements and excellent agreement is found. In addition, the model includes the electron spin and is thus able to describe a hot spin transistor. In this device, a spatial variation of the spin diffusion length is found, which scales inversely proportional to the variation of the electron density. The spin current can be increased by increasing the hot electron energy and by decreasing the image charge barrier without changing the spin diffusion length. Unprecedented insight into the effect of interfacial disorder at the metal–organic interface on charge and spin transport is provided. Finally, conditions are established, where majority and minority spin carriers propagate in opposite directions, increasing the spin current relative to the charge current and the occurrence of pure spin currents is analyzed.     

Potential design and transport property of 0.1-μm MOSFET withasymmetric channel profile

This paper describes potential design and transport property of a 0.1-μm n-MOSFET with asymmetric channel profile, which is formed by the tilt-angle ion-implantation after gate electrode formation. The relation between device performance and transport property of the asymmetric 0.1-μm device is explored by Monte Carlo simulations, and measured electrical characteristics. The self-consistent Monte Carlo device simulation coupled with a process simulator reveals higher electron velocity at the source end of the channel and velocity overshoot at the source side of the channel, and the smaller high-energy tail of the distribution in the drain. This transport property creates high drain current, large transconductance, and low substrate current of the 0.1-μm n-MOSFET with asymmetric channel profile     

Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion

This paper reports a closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted (FD) SOI NMOS devices with lightly-doped drain (LDD) structure. As verified by the two-dimensional (2-D) simulation results, the analytical drain current model considering energy transport and self-heating provides an accurate prediction of the drain current behavior of the 0.25-/spl mu/m FD SOI NMOS device with and without an LDD structure. From the analytical model, with the LDD structure, the device has a smaller effective electron mobility at a low drain voltage, where lattice temperature is dominant, and a higher effective mobility at a high drain voltage, where electron temperature dominates, as compared to the non-LDD device.     

Experimental evidence of inelastic tunneling in stress-inducedleakage current

We propose a new experimental technique to study the transport properties of stress-induced leakage current (SILC). Based on the carrier separation measurement for p-channel MOSFETs, the quantum yield of impact ionization for electrons involved in the SILC process is evaluated directly from the change in the source and gate currents of p-MOSFETs before and after stressing. Since the relationship between the electron energy and the quantum yield is established for direct and FN tunneling currents, the electron energy of electrons involved in the SILC process can be determined from the quantum yield. The results reveal that the measured energy of electrons in the SILC process is lower roughly by 1.5 eV than the energy expected in the elastic tunneling process. Trap-assisted inelastic tunneling model is proposed as a conduction mechanism of SILC accompanied by energy relaxation. It is shown, through the evaluation of the substrate hole current in n-channel MOSFETs, that the contribution of trap-assisted valence electron tunneling, another possible mechanism to explain the energy relaxation, to SILC is small     

Hot-electron injection into the oxide in n-channel MOS devices

In recent years, interest in hot-electron injection current in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short-channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses effects of trapping and local heating, allowing full characterization of parameter, voltage, and temperature dependence down to gate current levels of 10^-16A. Based on this characterization, a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinchoff region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.     

Theoretical analysis of an Al0.15Ga0.85As/In0.15Ga0.85As pseudomorphic HEMT using an ensembleMonte Carlo simulation

The calculations presented include the full details of the two-dimensional electron gas, nonstationary transport effects, real-space transfer, and the effects of the two-dimensional electric field profile. As a test of the accuracy with which the calculations successfully model a real device, the calculated current-voltage characteristic is compared to the experimentally measured data for a comparable device. Excellent agreement is obtained between the theory and experiment. The effect of velocity overshoot and real-space transfer on the device performance is investigated as a function of gate and drain bias. It is found that at under certain gate-bias conditions, real-space transfer into both the AlGaAs and GaAs layers occurs, leading to an enhanced substrate leakage current as well as lowered overall speed of performance     

Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.     

Tunneling transport through passivated CdS nanocrystal arrays grown by the Langmuir-Blodgett method

Tunneling electron transport through CdS nanocrystal arrays fabricated by the Langmuir-Blodgett method are studied by scanning electron spectroscopy. The effect of the matrix-annealing atmosphere on tunneling transport through the nanocrystal arrays is studied. Electron capture at traps in the case of nanocrystals annealed in vacuum is detected by tunneling current-voltage characteristics analyzed using a model relating the data of tunneling spectroscopy, photoluminescence, and quantum-mechanical calculation. Analysis shows that the nanocrystal surface is passivated by an ammonia monolayer upon annealing in an ammonia atmosphere. It is found that the substrate and surrounding non-passivated nanocrystals have an effect on the electron polarization energy.     

Effect of Si nanoparticles on electronic transport mechanisms in P-doped silicon-rich silicon nitride/c-Si heterojunction devices

We successfully fabricated hetero-junction (H-J) devices from P-doped silicon-rich SiN_x embedded with Si nanoparticles on a p-type crystalline Si substrate at low temperature. High-resolution transmission electron microscopy (HRTEM) analysis indicates that the thin films contain nano-crystallites. The H-J devices showed a good rectification ratio at room temperature. Three distinct regions of temperature dependent J-V characteristics curve can be identified, where different current density variations are indicated. In the low voltage range, the current across the interface of H-J follows an ohmic behavior. In the intermediate range of voltage, the current transport mechanism shows a transition from the phosphorus diffusion to tunneling dominant due to the silicon nanoparticle size and interface of HJ device changed, while the space-charge-limited current (SCLC) dominates the conduction mechanism in the high voltage range and the density of trapping states also affects the electron transport proceeding. At last, the proper size of silicon nanoparticle can reduces the interface charge density of H-J, which is confirmed via the numerical C-V matching technique and we propose a new energy band diagram to fit the HJ device embedded by the silicon nanoparticles.     

Photo-carrier generation as the origin of Fowler-Nordheim-inducedsubstrate hole current in thin oxides

The widely accepted anode-hole injection model assumes that the breakdown of oxide films during electrical stress is due to backflow of holes created in the anode by hot electrons. This explanation has been supported by the observation of a substrate hole current during Fowler-Nordheim (FN) substrate electron injection in n-type MOSFETs gate. In this paper, we reexamine the origin of the FN-induced substrate hole current. Based on direct experiments performed on nMOSFETs, we concluded that not the anode hole injection, but the generation of electron-hole pairs in the substrate by FN-induced photons in the gate, is the dominant source of the substrate hole current. Consequently, the generally accepted explanation of oxide degradation based on the anode hole injection model might therefore have to be revised     

Parametric studies and optimization of the beta-voltaic cell—I. Short-circuit current

Based on an experimentally verified model, the effects of various parameters on the short-circuit current of the beta-voltaic cell are demonstrated. The parametric variables used include electron minority-carrier lifetime and resistivity in the substrate, substrate thickness, surface recombination velocity, Curie content and junction depth. Computed results indicate that with a nominal source curie content of 2·8 Ci/cm², a short-circuit current of 80 μA/cm² can be achieved when the substrate resistivity is greater than 0·5 Ωcm, substrate thickness greater than 180 μm and an electron lifetime greater than 10 μsec. An increase of current to 90 μA/cm² is possible when the back contact is also irradiated by a similar source; under this condition the optimum substrate thickness is 125 μm. A reduction of the surface recombination velocity at the back contact to 10⁴ cm/sec increases the optimum current to 114 μA/cm² with a substrate of 75 μm in thickness.     

Investigation of the Correlation Between Temperature and Enhancement of Electron Tunneling Current Through $hbox{HfO}_{bf 2}$ Gate Stacks

A model is established to describe the temperature dependence of the electron tunneling current through HfO₂ gate stacks based on analyzing the coupling between the longitudinal and transverse components of electron thermal energy caused by the difference of the effective electron mass between the HfO₂ gate stacks and silicon. By analyzing the three-dimensional Schrodinger equation for a MOS structure with HfO₂ gate stacks, a reduction in the barrier height is resulted from the large effective electron mass mismatch between the gate oxide and the gate (substrate). The calculated electron tunneling currents agree well with the experimental data over a wide temperature range. This coupling model can explain the temperature dependence of the electron tunneling current through HfO₂ gate stacks very well. The numerical results also demonstrate that the temperature dependence of the electron tunneling current strongly depends on the effective electron mass of HfO₂. This temperature sensitivity of the electron tunneling current can be proposed as a novel method to determine the effective electron mass of the gate oxide.     

Definition of curve fitting parameter to study tunneling and trapping of electrons in Si/ultra-thin SiO2/metal structures

The tunneling of electrons through metal–oxide–silicon (MOS) structures with ultra-thin oxide is modeled using a linear model for the electron potential energy, an approach which simplifies the computation of both the interface potential and the field penetration distance in the substrate. The one-particle quantum problem is split into finding the metastable states induced by the internal field penetration in the substrate and the running states in the gate region. The two states are assumed to be connected by the condition for the continuity of the probability density at the substrate–dielectric interface. The electron probability current and the total gate current density are obtained for different gate voltages. As the model yields excellent fittings with experimental current–voltage (I–V) data for MOS structures, it was further applied to constant current stressing analysis in order to obtain values for important electron trapping parameters in the oxide. The resultant estimates of the electron trapping cross-section fall in the range of other independent determinations in the literature.     

Leakage current in single electron device due to implanted gallium dopants by focus ion beam

Focus ion beam (FIB) technology has been employed to fabricate quantum dot based devices such as the single electron transistor (SET) on a silicon substrate with Cr/Au/Al₂O₃ film stack. It was discovered that the dwell time of FIB gallium beam on an area impacted the dosage of gallium ions implanted into the insulating substrate, creating a highly doped region which could lead to device leakage current. This work focus on the potential electron transport possible when an over-dosed gallium rich Al₂O₃ layer will lead to leakage current between otherwise electrically isolated contact pads. Using the Keithley 4200 semiconductor parametric analyzer (SPA) and the energy dispersive X-ray spectrometer (EDS) analysis; we demonstrate the detrimental effect of leakage current in the range of pA, observed between drain/source electrodes due to the high dose of gallium implanted into the insulating Al₂O₃. The optimized FIB etching parameters to produce a high quality of device functionality with no leakage current is also demonstrated.