Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology

A novel test structure for contact resistance measurement of bonded copper interconnects in three-dimensional integration technology is proposed and fabricated. This test structure requires a simple fabrication process and eliminates the possibility of measurement errors due to misalignment during bonding. Specific contact resistances of bonding interfaces with different interconnect sizes of approximately 10/sup -8/ /spl Omega/-cm/sup 2/ are measured. A reduction in specific contact resistance is obtained by longer anneal time. The specific contact resistance of bonded interconnects with longer anneal time does not change with interconnect sizes.     

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.     

Correlation of electromigration lifetime distribution to failure mode in dual Damascene Cu/SiLK interconnects

The electromigration cumulative percent lifetime probability of dual Damascene Cu/SiLK interconnects was fitted using three, individual lognormal functions where the functional populations were grouped by void growth location determined from focused ion beam failure analysis of all 54 of the stressed structures. The early, first mode failures were characterized by small voids in the bottom of the vias. The intermediate mode failures had voids in the line and via bottom while the late mode failures had voids that formed in the line only. The three, individual lognormal functions provided good fits of the data. Failure mode population separation using comprehensive failure analysis suggested that only the first mode failures should be used in the prediction of the chip design current.     

Polymer residue chemical composition analysis and its effect on via contact resistance in dual damascene copper interconnects process integration

During via and trench plasma etching in dual damascene copper interconnects process integration, polymer residues and copper damage were created as by-products of the dry-etch process. The polymer residue chemical composition and copper damage were analyzed by Auger electron spectroscopy. Analysis result indicated that besides copper, carbon, oxygen, and nitrogen and trace amounts of chlorine and sulphur were also observed. The polymer residue and copper damage are the important reasons of cause higher via contact resistance and lower via yield. It could be reduced and eliminated effectively using optimized plasma etch recipe, improved polymer residue removal methods and improved pre-treatment before metal deposition and so on.     

Effects of Ti addition on via reliability in Cu dual damascene interconnects

We investigated the effects of a Ti addition on the reliability and the electrical performance of Cu interconnects, comparing three different ways of Ti addition such as A) Ti layer insertion under Ta-TaN stacked barrier metal, B) Ti layer insertion between a Ta-TaN barrier and Cu, and C) the Ti doping from the surface of the electrochemical-plated (ECP) Cu film. The structure-A drastically suppresses the stress-induced voiding (SIV) under the via connected to a wide lower line due to adhesion improvement by Ti at the via-bottom, while the electromigration (EM) is not improved. In the structure-B, by contrast, the EM is improved but the SIV resistance is degraded. The Ti doping from the bottom surface of Cu film restricts the grain growth and increases the tensile stress, enhancing the SIV. The structure-C improves not only the SIV but also the EM resistance. The oxygen gettering effect of Ti during the ECP-Cu annealing is a reason for the reliability improvements of the SIV and the EM. The improvement of adhesiveness at the interface between the via and the lower Cu line, and the oxygen gettering from Cu by Ti play an important role in suppressing the SIV and the EM.     

Microstructure and reliability of copper interconnects

The effects of texture and grain structure on the electromigration lifetime of Cu interconnects are reported. Using different seed layers, (111)- and (200)-textured CVD Cu films with similar grain size distributions are obtained. The electromigration lifetime of (111) CVD Cu is about four times longer than that of (200) CVD Cu. For Damascene CVD Cu interconnects, the electromigration lifetime degrades for linewidths in the deep submicron range because the grains are confined as a result of conformal deposition in narrow trenches. In contrast, electroplated Cu has relatively larger grains in Damascene structure, resulting in longer electromigration lifetime than CVD Cu and no degradation for linewidths in the deep submicron range     

Thermomechanical response and stress analysis of copper interconnects

This study is devoted to thermomechanical response and modeling of copper thin films and interconnects. The constitutive behavior of encapsulated copper film is first studied by fitting the experimentally measured stress-temperature curves during thermal cycling. Significant strain hardening is found to exist. Within the continuum plasticity framework, the measured stress-temperature response can only be described with a kinematic hardening model. The constitutive model is subsequently used for numerical thermomechanical modeling of Cu interconnect structures using the finite element method. The numerical analysis uses the generalized plane strain model for simulating long metal lines embedded within the dielectric above a silicon substrate. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. Salient features are compared with those in traditional aluminum interconnects. Practical implications in the reliability issues for modern copper/low-k dielectric interconnect systems are discussed.     

Texture investigation of copper interconnects with a different line width

To understand the effect of line width on textural and microstructural evolution of Cu damascene interconnect, three Cu interconnects samples with different line widths are investigated. According to x-ray diffraction (XRD) results, the (111) texture is developed in all investigated lines. Scattered {111}〈112〉 and {111}〈110〉 texture components are present in 0.18-μm-width interconnect lines, and the {111}〈110〉 texture was developed in 2-μm-width interconnect lines. The directional changes of the (111) plane orientation with increased line width were investigated by XRD. In addition, microstructure and grain-boundary character distribution (GBCD) of Cu interconnect were measured using electron backscattered diffraction (EBSD) techniques. This measurement demonstrated that a bamboo-like microstructure is developed in the narrow line, and a polygranular structure is developed in the wider line. The fraction of ∑3 boundaries is increased as the line width increases but is decreased in the blanket film. A new interpretation of textural evolution in damascene interconnect lines after annealing is suggested, based on the state of stress and growth mechanisms of Cu deposits.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

Analysis of thermal stresses in metal interconnects with multilevel structures

The evolution of thermal stresses in aluminum interconnects was analyzed numerically. Particular attention was devoted to the effects of multilevel arrangement, which have been largely ignored in past studies. Two-dimensional models based on long metal lines with different aspect ratios and cross-sectional arrangements were employed. The metallization, taken to include thin refractory layers sandwiching the aluminum conductor, was embedded within silicon oxide dielectric on top of the silicon substrate. A thermal cooling process was simulated by recourse to the finite element method. It was found that the incorporation of refractory layers increases the stress in aluminum lines. The line aspect ratio, rather than the multilevel nature, plays the most important role in affecting the thermal stress. Issues related to interconnect stress modeling and reliability implications are discussed.     

Local textures and grain boundaries in voided copper interconnects

We have characterized grain boundary structures and local textures in stress voided copper lines. Grain boundary misorientations as well as the tilt and twist character of boundaries were measured using electron backscatter diffraction in the scanning electron microscope in conjunction with focused ion beam images. We have summarized data for a number of boundaries immediately adjacent to voids and made comparisons to boundaries from regions that remained intact. These data were acquired from the same lines, and so represent measurements from material with identical histories. Significant local variations in microstructure were observed. Local <111> textures of grains near voids were of lower strength than those away from voids. Grain boundaries intersecting voids were of higher angle character and had significant twist components. These results suggest that local regions associated with more favorable kinetics are more susceptible to void formation and growth.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

Integration and electrical characterization of carbon nanotube via interconnects

Carbon nanotubes (CNTs) are considered a promising material for interconnects in the future generations of microchips because of their low electrical resistance and excellent mechanical stability. In particular, CNT-based contacts appear advantageous when compared with current tungsten or copper technologies and could therefore find an application as metal contacts interconnecting the transistors with the back end of line of the microchip. In this work, the integration of vertical CNT bundles in sub-micron contact holes is evaluated at wafer scale and the major integration challenges encountered in the practical realization of the process are discussed. Nickel PVD films were used to selectively grow CNT into the contact holes at temperatures as low as 400 °C, which is the thermal budget available for contacts. The height of the contacts and the length of the CNT are controlled by a chemical mechanical polishing step (CMP) after embedding the CNT into SiO₂. Ti/Au metal pads are then formed onto the CNT bundles by PVD and lift-off. The integrated CNT are electrically characterized and an annealing treatment was found to improve the CNT-via resistance. As the electrical properties of the CNT can be evaluated, the structure and the process presented constitute a test vehicle for the development of high-quality CNT-contacts.     

TaN-TiN binary alloys and superlattices as diffusion barriers for copper interconnects

Binary alloys and superlattices of TaN-TiN thin films were grown on Si(100) substrates with a TiN buffer layer using pulsed laser deposition. A special target assembly was used to manipulate the concentrations of these binary component films. The 60% TaN resulted in a TaN (3 nm)/TiN (2 nm) superlattice, while 30% and 70% TaN generated uniform Ta_xTi_1−xN alloys. X-ray diffraction (XRD), transmission electron microscopy (TEM), and scanning transmission electron microscopy (STEM) confirmed the single-crystalline nature of these films. Four-point probe resistivity measurements suggest that these alloy and superlattice films have a lower resistivity than pure single-crystalline TaN films. The Cu-diffusion characteristic studies showed that these materials would have the potential as high-temperature diffusion barriers for Cu in ultra-large-scale integration technology.     

Relationship between microstructure and electromigration damage in unpassivated PVD copper damascene interconnects

The microstructure of unpassivated PVD copper interconnects has been determined by electron backscatter diffraction technique (EBSD) inside a scanning electron microscope (SEM), and the appearance and growth of voids and hillocks during the electromigration testing has been observed in situ inside the SEM. The EBSD measurement indicates a strong <111 > texture for the tested line and a high angle boundary fraction of more than 70%. The comparison of the EBSD maps and the SEM images of the defect formation due to electromigration shows that the voids are formed mainly at the sidewall and after blocking grains. These images indicate that the diffusion paths are both the interface and the grain boundaries.     

Electromigration characterization of damascene copper interconnects using normally and highly accelerated tests

We have completed a set of experiments on damascene Chemical Vapor Deposition Copper (CVD-Cu) interconnects using Wafer Level and Package Level Reliability (WLR and PLR) tests. Two line widths have been extensively characterized : W=4 and 0.6 μm. For both line widths, the activation energy values extracted using WLR and PLR data are good in agreement demonstrating that the active diffusion paths remain the same over the wide range of used measurement conditions : Ea=0.65eV for W = 4μm, Ea = 0.7-0.8eV for W = 0.6μm. spite of Ea experimental values lower than the reference values of the literature.     

Integration and characterization of gas cluster processing for copper interconnects electromigration improvement

Basic physical properties as well as electrical and reliability performance of Infusion™ processing were evaluated. This approach, proposed as an alternative to CuSiN and electrolessly deposited Co-alloys, was shown to join the benefits of these two techniques without well-known associated drawbacks. Indeed, it is a uniform process, acting as an efficient Cu diffusion barrier, which does not require specific integration development. Different processes were introduced in a multi-level interconnect stack using ULK/USG stack as IMD, showing excellent electrical properties, and three times electromigration time-to-failure improvement with respect to standard SiCN barrier. However, it was shown that existing process conditions lead to some introduction of N atoms into ULK dielectric, showing there is still some room for process optimization in architectures using un-capped ULKs, to keep the benefits of EM improvement and aggressive effective dielectric constant.     

Technology and reliability constrained future copper interconnects.I. Resistance modeling

A realistic assessment of future interconnect performance is addressed, specifically, by modeling copper (Cu) wire effective resistivity in the light of technological and reliability constraints. The scaling-induced rise in resistance in the future may be significantly exacerbated due to an increase in Cu resistivity itself, through both electron surface scattering and the diffusion barrier effect. The impact of these effects on resistivity is modeled under various technological conditions and constraints. These constraints include the interconnect operation temperature, the effect of copper-diffusion barrier thickness and its deposition technology, and the quality of the interconnect/barrier interface. Reliable effective resistivity trends are established at various tiers of interconnects, namely, at the local, semiglobal, and global levels. Detailed implications of the effect of resistivity trends on performance are addressed in the second part of this work     

Technology and reliability constrained future copper interconnects.II. Performance implications

For pt. I see ibid., vol.49, no.4, pp.590-7 (2002). This work extends the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics. As quantified in part I of this work, the effective resistivity of copper is not only significantly larger than its ideal, bulk value but also highly dependent on technology and reliability constraints. Performance is quantified under various technological conditions in the future. In particular, wire delay is extensively addressed. Further, the impact of optimal repeater insertion to improve these parameters is also studied using realistic resistance trends. The impact of technologically constrained resistance on power penalty arising from repeater insertion is briefly addressed. Where relevant, aforementioned results are contrasted with those obtained using ideal copper resistivity     

Nanotwin formation and its physical properties and effect on reliability of copper interconnects

Ultra-fine grained copper with a large amount of nano-scale twin boundaries has high mechanical strength and maintains normal electrical conductivity. The combination of these properties may lead to promising applications in future Si microelectronic technology, especially as interconnect material for air-gap and free-standing copper technologies. Based on first principles calculations of total energy and in-situ stress measurements, high stress followed by stress relaxation during the Cu film deposition seems to have contributed to nanotwin formation. Nanoindentation studies have shown a larger hardness for copper with a higher nanotwin density. The effect of Cu nanotwin boundaries on grain growth was investigated by scanning electron microscopy (SEM), electron backscatter diffraction (EBSD) and transmission electron microscopy (TEM). The presence of a high density of nanotwin boundaries may improve the reliability of Cu interconnects.