Relation between defect generation, stress induced leakage current and soft breakdown in thin (<5 nm) oxides

The normalized stress induced leakage current (SILC) measured when the oxide is subjected to low level constant-current stresses shows a tendency towards saturation at large charge fluences. To investigate the origin of this saturation, the degradation of the oxide has been analyzed using two independent methods: SILC data analysis and a two-step stress test. The results show that, although under low stress currents the SILC saturation is observed, the degradation (i.e., the generation of defects) proceeds until the soft breakdown (SBD) event takes place. The implications for the use of SILC data as degradation monitor are analyzed.     

Assessment of temperature and voltage accelerating factors for 2.3–3.2 nm SiO2 thin oxides stressed to hard breakdown

The temperature and voltage acceleration for a large database of time dependent dielectric breakdown in 2.3 and 3.2 nm SiO₂ oxides is investigated. All results deal with the time to hard breakdown which is defined when a typical high current limit (1 mA) at operating voltage is reached rather than detecting the first current change as is conventionally done. Using an accurate experimental error evaluation, long range data are compared for consistency to the predictions of various state-of-the-art extrapolation models used to qualify these oxides, to point out which one describes the data best. The activation energies corresponding to the dominant degradation mechanisms are extracted over a temperature range from 50 °C to 125 °C for N type substrate stressed in accumulation regime. The voltage extrapolation models are compared for P and N type substrate with positive stress polarity on the gate. It is verified that a TDDB power voltage law is well predictive for both P substrate in inversion regime and N substrate in accumulation regime.     

On stress induced leakage current in 5 and 3 nm thick oxides

The stress induced leakage current (SILC) in Si/SiO₂ structures with thin gate oxides has a steady-state component which increases drastically when the oxide thickness decreases. It is generally agreed that the SILC is due to electron tunnelling trough stress-induced traps. However, it was observed that the SILC, created by Fowler–Nordheim injection, decays continuously when, after stress, the samples are positively or negatively biased at a low voltage. The decay is irreversible as long as the gate oxide is not biased at a high voltage. The present article adds complementary observations. It shows, first that the above phenomenon is observed in 3.5 nm thick oxides, secondly, that this phenomenon is stable as long as the temperature stays below 200°C, and thirdly, that during the SILC decay, the interface state density does not diminish.     

Measurement and modeling of the annealing kinetics of stress induced leakage current in ultra-thin oxides

The annealing properties of the stress induced leakage current (SILC) for 55 and 65 Åthick oxides are investigated. It is demonstrated that the SILC is a fully reversible degradation process and that its generation kinetics are nearly unchanged after successive stressing/annealing cycles. The activation energy and diffusion coefficient of the annealing process has been extracted and shown to be independent of oxide thickness. Moreover the annealing kinetics are quantitatively simulated using a drift-diffusion model with the experimentally extracted parameters.     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

Electrical characterization and quantum modeling of MOS capacitors with ultra-thin oxides (1.4–3 nm)

Electrical characterization of MOS capacitors with ultra-thin oxides (1.4–3 nm) has been carried out. The validity of the correction to C–V data, needed to take into account the series resistance and leakage current, is discussed. The gate current in accumulation and in depletion regions has been investigated and properly modeled based on detailed analysis of tunneling from the polygate.     

A model of the stress induced leakage current in gate oxides

A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress     

Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.     

High field stress at and above room temperature in 2.3 nm thick oxides

It was predicted recently that oxide reliability will limit the oxide scaling at about 2.4 nm and it is known that MOS devices are increasingly required to operate at elevated temperatures. It is therefore important to carefully study the oxide degradation under electrical stress in such oxides at and above room temperature. In this article, it is shown that in 2.3 nm thick oxides, the degradation can be evaluated by monitoring the gate current when the substrate is in depletion and new results are presented on the gradual degradation in these oxides.     

Hot hole stress induced leakage current (SILC) transient in tunneloxides

The mechanisms and transient characteristics of hot hole stress induced leakage current (SILC) in tunnel oxides are investigated. Positive oxide charge assisted tunneling is found to be a dominant SILC mechanism in a hot hole stressed device. The SILC transient is attributed to oxide hole detrapping and thus annihilation of positive charge assisted tunneling centers. Our characterization shows that the leakage current transient in a 100-Å oxide obeys a power law time dependence f^-n with the power factor n significantly less than one. An analytical model accounting for the observed time dependence is proposed     

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices

Double gate (DG) FETs have emerged as the most promising technology for sub-50 nm transistor design. However, analysis and control of the gate tunneling leakage in DGFET is necessary to fully exploit their advantages. In this paper we have modeled (numerically and analytically) and analyzed gate-to-channel leakage in different DGFET structures, viz., doped body symmetric device (SymDG) with polysilicon gates, intrinsic body symmetric device with metal gates (MGDG) and intrinsic body asymmetric device (AsymDG) with different front and back gate materials. It is observed that, use of (near-mid-gap) metal gate and intrinsic body can result in 3–4× reduction in gate-to-channel leakage compared to the SymDG structure.     

Tunneling leakage current in ultrathin (<4 nm) nitride/oxidestack dielectrics

The leakage current in high-quality ultrathin silicon nitride/oxide (N/O) stack dielectric is calculated based on a model of one-step electron tunneling through both the nitride and the oxide layers. The results show that the tunneling leakage current in the N/O stack is substantially lower than that in the oxide layer of the same equivalent oxide thickness (EOT). The theoretical leakage current in N/O stack has been found to be a strong function of the nitride/oxide EOT ratio: in the direct tunneling regime, the leakage current decreases monotonically as the M/O ratio increases, while in the Fowler-Nordheim regime the lowest leakage current is realized with a N/O EOT ratio of 1:1. Due to the asymmetry of the N/O barrier shape, the leakage current under substrate injection is higher than that under gate injection, although such a difference becomes smaller in the lower voltage regime. Experimental data obtained from high quality ultrathin N/O stack dielectrics agree well with calculated results     

Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop

A newly integrated pulsed laser system has been utilized to investigate the effects of voltage stress on single event upset (SEU) of flip flop chain manufactured in 65 nm bulk CMOS technology. Laser mappings of the flip flop chain revealed that the SEU sensitive regions increased with laser energy. Post-processing of the data from the laser mapping facilitated the plotting of the cross-section versus laser energy curve. We found a clear shift in the cross-section curves after voltage stress of 130 h. Comparisons of data revealed at least a doubled increase in sensitive areas after voltage stress. During the voltage stress, various electrical parameters were monitored and changes were observed. It was found that the increase in SEU sensitivity is related to electrical parameter changes and SPICE simulation results concur likewise.     

Voltage acceleration and t63.2 of 1.6–10 nm gate oxides

Gate oxide reliability data collected over a considerable period of time were compiled to assess the voltage acceleration and the time to breakdown as function of oxide thickness. These data cover a range from 1.6 to 10 nm and can be used as benchmark for technologies that are still using gate oxide in this thickness range. The data form well-defined bands for each of the voltage acceleration models. The functional dependence of the parameter on oxide thickness depends strongly on the voltage acceleration model. The accuracy of the voltage acceleration parameters determined for the different acceleration models is studied. The time to breakdown at one voltage spans many time-decades if the data covering the entire thickness range are plotted in one graph. Therefore, the use of a model-free value, the voltage to get 63.2% breakdown at a certain fixed time, is proposed for plotting the data taken in the wide oxide thicknesses range, instead of normalizing the time to breakdown to a certain voltage using one of the voltage acceleration models. Based on the results a self-consistent test of the voltage acceleration models is introduced. This parameter also supports the t_bd power law and therefore the hydrogen release model when plotting the voltage acceleration parameter of the exp(V)-model versus the inverse model-free gate voltage to get 63.2% breakdown at a fixed time.     

Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p+ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C–V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q_bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D_it, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p+ poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.     

A function-fit model for the hard breakdown I–V characteristics of ultra-thin oxides in MOS structures

A function-fit model for the hard breakdown current–voltage characteristics of ultra-thin oxides in metal–oxide–semiconductor structures based on the smoothing function concept is presented. The model is intended to capture the diode-like and resistance-like behaviours observed at low and high applied biases, respectively, by means of a simple, continuous and derivable function. These features make the proposed expression suited for circuit simulation environments. The effect of temperature on the model parameters is also analysed.     

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs

Design automation tools have been developed to suppress CDE-induced latchup in CMOS ASICs. The tools govern the placement of I/Os and cores subject to CDE and automate the insertion of well and substrate contacts with varying periodicities around CDE susceptible cells according to rules derived from an analytical latchup model.     

Polarization-Insensitive GaInNAs–GaInAs MQW-SOA With Low Noise Figure and Small Gain Tilt Over 90-nm Bandwidth (1510–1600 nm)

rdquoWe developed a broadband polarization-insensitive multiquantum-well (MQW) semiconductor optical amplifier (SOA) for application as an optical switch in broadcast-and-select-type optical packet switching systems. We adopted a GalnNAs-GalnAs MQW structure active layer to decrease the noise figure (NF) around the gain peak wavelength together with a small gain tilt in the C-band. The device exhibited a smaller NF on the shorter wavelength side of the gain peak compared with a GalnNAs strained-bulk SOA. The reduced NF resulted in a large effective gain bandwidth of up to 90 nm (1510-1600 nm). The device also exhibited the small gain tilt (<1.2 dB) and small polarization-dependent gain (<0.8 dB) in the C-band.