软硬件协同设计语言System C在SoC设计中的应用

软硬件协同设计是未来VLSI设计的发展趋势.作为新的系统级VLSI设计标准,System C是一种通过类对象扩展的基于C/C++建模平台,支持系统级软硬件协同设计、仿真和验证.文章讨论了SystemC复杂芯片设计中的设计流程、设计优势,并给出具体设计实例.     

一种基于SystemC的软硬件协同设计方法

随着集成电路工艺的飞速发展,传统的设计方法已不能满足设计高集成度的复杂数字系统的要求。软硬件协同设计成为嵌入式系统设计的新方法。SystemC是一种兼容C++的系统建模语言,它同时支持RTL级、行为级和系统级描述,使其成为软硬件协同设计平台的基础。     

嵌入式系统的软硬件协同设计

协同设计改变了传统的设计反复修改系统方案的缺点，通过综合分析系统软硬件功能，最大限度地挖掘系统软硬件之间的并发性，将软硬件开发结合得更紧密，可以大大提高设计效率，使设计出来的系统工作在最佳工作状态。本文将系统地阐述软硬件协同设计技术。     

软硬件协同的SOC设计方法

软硬件协同设计是一种正在发展中的设计方法。本文首先分析了它在SOC设计中的必要性，其次给出了软硬件协同设计的基本流程，并探讨了其优点和现存的技术难点。最后给出了设计及验证实例。     

一种软硬件协同设计工具原型及其设计描述方法

软硬件协同设计工具不但需具有软硬件功能划分的能力,而且应可实现系统级设计到软硬件基本结构的综合。提出一种利用进程代数为高层设计语义基础,可重用现有软硬件设计工具资源的软硬件协同设计工具的实现方案框架,重点讨论其中的设计描述问题。采用这种基于语言变换的软硬件协同设计工具方案有利于对系统的活性、安全性、接口一致性等性质进行高层仿真与形式验证,具有可用性、易扩展好等优点。     

SOC设计中的软硬件协同设计

软硬件协同设计是一种全新的发展中的设计理论,它是现有集成电路设计理论的完善,是建立在现有理论之上的一个更高层次的设计理论．它必将与现有理论一起共同纽成更为完善的理论体系;文章从SOC设计的需要角度简要介绍了软硬件协同设计这一理论体系,并给出了设计实例。     

基于遗传算法的软硬件协同设计探索

软硬件协同设计的目标结构包括一个CPU和多个ASIC,它们通过一条总线进行通信.本文介绍一种用于多目标、多模式系统综合的协同设计的新方法.各个工作模式具有不同的运行概率.在满足设计约束的条件下,我们应用遗传算法对系统的速度和功耗两个目标进行优化.遗传算法是全局算法,它能避免陷入局部最小.     

软硬件协同验证大幅缩短SoC开发周期

SoC的开发周期在不久的将来会大幅缩短。业界的整机厂商和半导体厂商开始加速采用以C语言为基础的软硬件协同验证的SoC开发方法(见图1）。NEC电子、索尼等领先公司在这方面已经积累了一定的经验，实际产品也在不断增加中。紧跟其后的佳能、东芝，ROHM．     

基于Nios的FFT算法软硬件协同设计

在深入研究Nios自定制指令的软硬件接口的基础上,利用Matlab/DSP Builder建立快速傅里叶变换FFT核心运算指令基本模型,然后用Altera公司提供的Singacompiler工具对其进行编译,产生Quartus Ⅱ能够识别的VHDL源程序,并将此程序在Nios中自定制成相关的FFT运算指令.利用自定制的FFT运算指令,在Nios中利用C语言编写基于Nios的FFT算法程序,实现了FFT运算的软硬件协同设计.经测试表明,将FFT算法加入到Nios嵌入式处理器指令集中,可以帮助系统完成复杂的数据处理任务,增强Nios系统的实时处理能力.该设计方法打破了软硬件间的屏降,大大加快了系统的功能验证.     

MSTP芯片的软硬件协同验证平台设计

MSTP是基于SDH/SONET网络的多业务传输平台,是下一代城域网解决方案,目前已经成为数据传输技术的新热点之一。介绍了一种MSTP芯片的软硬件协同验证平台,该平台由作者参与设计完成并应用于MSTP芯片的各部分功能模块验证。该平台的硬件部分包括一块基于大容量FPGA的母板和一块基于单片机的子板;软件部分包括运行于FPGA的MSTP各功能模块测试矢量组,运行于单片机的读写控制程序以及运行于控制计算机的配置、管理、监控程序。该平台具有低成本高效率的特点。到目前为止,已经在该平台上成功验证了MSTP中的大部分功能模块。     

PUFPass: A password management mechanism based on software/hardware codesign

Secure passwords need high entropy, but are difficult for users to remember. Password managers minimize the memory burden by storing site passwords locally or generating secure site passwords from a master password through hashing or key stretching. Unfortunately, they are threatened by the single point of failure introduced by the master password which is vulnerable to various attacks such as offline attack and shoulder surfing attack. To handle these issues, this paper proposes the PUFPass, a secure password management mechanism based on software/hardware codesign. By introducing the hardware primitive, Physical Unclonable Function (PUF), into PUFPass, the random physical disorder is exploited to strengthen site passwords. An illustration of PUFPass in the Android operating system is given. PUFPass is evaluated from aspects of both security and preliminary usability. The security of the passwords is evaluated using a compound heuristic algorithm based PUF attack software and an open source password cracking software, respectively. Finally, PUFPass is compared with other password management mechanisms using the Usability-Deployability-Security (UDS) framework. The results show that PUFPass has great advantages in security while maintaining most benefits in usability.     

Privacy-preserving telecardiology sensor networks: toward a low-cost portable wireless hardware/software codesign.

Recently, a remote-sensing platform based on wireless interconnection of tiny ECG sensors called Telecardiology Sensor Networks (TSN) provided a promising approach to perform low-cost real-time cardiac patient monitoring at any time in community areas (such as elder nursing homes or hospitals). The contribution of this research is the design of a practical TSN hardware/software platform for a typical U.S. healthcare community scenario (such as large nursing homes with many elder patients) to perform real-time healthcare data collections. On the other hand, due to the radio broadcasting nature of MANET, a TSN has the risk of losing the privacy of patients' data. Medical privacy has been highly emphasized by U.S. Department of Health and Human Services. This research also designs a medical security scheme with low communication overhead to achieve confidential electrocardiogram data transmission in wireless medium.     

Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed

This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such as the dependency of task communication speed on interconnect parasitic. The codesign flow executes three consecutive steps: 1) combined partitioning and scheduling: besides partitioning and scheduling, this step also identifies the minimum speed constraints for each data link; 2) IP core placement, bus architecture synthesis, and routing: IP cores are placed using a hierarchical cluster growth algorithm; bus architecture synthesis identifies a set of possible building blocks and then assembles them for minimizing bus length and complexity; poor solutions are pruned using a special table structure and select-eliminated method; and 3) rescheduling for the best bus architecture. This paper offers extensive experiments for the proposed codesign method, including bus architecture synthesis for a network processor and a JPEG SoC.     

用互联网思维做硬件

本文重点分析物联网应用中智能硬件的特点以及其设计过程中需要解决的问题,并由此引出并介绍一种新颖的解决方案,可以克服传统硬件设计的各种弊端,达到如同开发互联网软件那样去实现智能硬件产品的目的。本文网络版地址：http：//www.eepw.com.cn/article/276355.htm     

Incremental hardware estimation during hardware/software functionalpartitioning

To aid in the functional partitioning of a system into interacting hardware and software components, fast yet accurate estimations of hardware size are necessary. We introduce a technique for obtaining such estimates in two orders of magnitude less time than previous approaches without sacrificing substantial accuracy, by incrementally updating a design model for a changed partition rather than re-estimating entirely     

节能型软件满足功率智能型硬件的需要

节能型RTOS能够动态地均衡性能与效率 随着对移动和有线设备的能源效率需求的增长,系统开发人员会越来越多地使用功率智能型硬件解决方案,而更加节能的代码能使之如虎添翼. 最前沿的功率智能型硬件技术就是多核SoC,它能够工作在各种各样的频率及电压下.还有一些CPU和外设也支持多种功耗模式.我们已经看到硬件方面的进展,但是要真正地从这些进展中得到好处,还需要一种新型的操作系统.