Robust Sub-harmonic Mixer at 340 GHz Using Intrinsic Resonances of Hammer-Head Filter and Improved Diode Model

This paper presents a sub-harmonic mixer at 340 GHz based on anti-parallel Schottky diodes (SBDs). Intrinsic resonances in low-pass hammer-head filter have been adopted to enhance the isolation for different harmonic components, while greatly minimizing the transmission loss. The application of new DC grounding structure, impedance matching structure, and suspended micro-strip mitigates the negative influences of fabrication errors from metal cavity, quartz substrate, and micro-assembly. An improved lumped element equivalent circuit model of SBDs guarantees the accuracy of simulation, which takes current-voltage (I/V) behavior, capacitance-voltage (C/V) behavior, carrier velocity saturation, DC series resistor, plasma resonance, skin effect, and four kinds of noise generation mechanisms into consideration thoroughly. The measurement indicates that with local oscillating signal of 2 mW, the lowest double sideband conversion loss is 5.5 dB at 339 GHz; the corresponding DSB noise temperature is 757 K. The 3 dB bandwidth of conversion loss is 50 GHz from 317 to 367 GHz.     

A 400–500 GHz Balanced SIS Mixer with a Waveguide Quadrature Hybrid Coupler

We have developed a 400–500 GHz low-noise balanced SIS (Superconductor Insulator Superconductor) mixer, which is based on a waveguide RF quadrature hybrid coupler. The RF quadrature hybrid was designed and fabricated as a broadband hybrid with good performance at 4 K. The fabricated RF quadrature hybrid was measured at room temperature with a submillimeter vector network analyzer to check amplitude and phase imbalance between two output ports. Then the balanced mixer was assembled with the RF hybrid, two DSB mixers, and a 180° IF hybrid. Several important parameters such as noise temperature, LO power reduction, and IF spectra were measured. The LO power reduction is defined as how much LO power the balanced mixer saves compared with a typical single-ended mixer. The measured noise temperature of the balanced mixer was ~ 55 K at the band center which corresponds to ~ 3 times the quantum noise limit (hf/k) in DSB, and ~ 120 K at the band edges. The noise performance over LO frequency was almost the same as that of the worse DSB mixer used in the balanced mixer. In addition the LO power required for the balanced mixer is ~ 11 dB less than that of the single-ended mixers.     

A 1 V power amplifier for 81–86 GHz E-band

The design and layout of a two stage SiGe E-band power amplifier using a stacked transformer for output power combination is presented. In EM-simulations with ADS Momentum, at E-band frequencies, the power combiner consisting of two individual single turn transformers performs significantly better than a single 2:1 transformer with two turns on the secondary side. Imbalances in the stacked transformer structure are reduced with tuning capacitors for maximum gain and output power. At 84 GHz the simulated loss of the stacked transformer is as low as 1.35 dB, superseding the performance of an also presented alternative power combiner. The power combination allows for a low supply voltage of 1 V, which is beneficial since the supply can then be shared between the power amplifier and the transceiver, thereby eliminating the need of a separate voltage regulator. To improve the gain of the two-stage amplifier it employs a capacitive cross-coupling technique not yet seen in mm-wave SiGe PAs. Capacitive cross-coupling is an effective technique for gain enhancement but is also sensitive to process variations as shown by Monte Carlo simulations. To mitigate this two alternative designs are presented with the cross coupling capacitors implemented either with diode coupled transistors or with varactors. The PA is designed in a SiGe process with f _T  = 200 GHz and achieves a power gain of 12 dB, a saturated output power of 16 dBm and a 14 % peak PAE. Excluding decoupling capacitors it occupies a die area of 0.034 mm².     

A High Linearity and Low Power 3.1–10.6GHz CMOS Up-Conversion Mixer for UWB Applications

This paper proposed a full band up-mixer implemented in 0.18μm COMS process for UWB wireless systems. The linearity, noise figure and other performance are improved by using current bleeding technique and inserting a LC network on common source nodes of the switches stage. The inductance peaking technique is adopted to flatten conversion gain over the 14 sub-bands of UWB system. The up-converting mixer converts an input of 264MHz intermediate frequency to an output of 3.1–10.6GHz radio frequency signal. From the post simulation results, the proposed up-mixer achieves conversion gain of 10±1dB and the IIP3 of 7.19dBm and power consumption of 2.4mW at 1.2V power supply.     

Development of a 385–500 GHz Sideband-Separating Balanced SIS Mixer

A submillimeter (385–500 GHz) low-noise sideband-separating balanced SIS (Superconductor Insulator Superconductor) mixer (Balanced 2SB mixer) with high IRR (Image Rejection Ratio) has been successfully developed, whose SSB (Single SideBand) noise temperature is ～ 200 K (10hf/k) with an image rejection ratio of ≥?～10 dB. Balanced mixers have become a promising technology which would break through the limitation especially in terahertz receivers and heterodyne arrays. However, though there are examples in microwave with relatively worse noise performance, submillimeter and terahertz balanced mixers have rarely been developed in spite of their astronomical importance. The developed balanced 2SB mixer is not only the first one demonstrated at submillimeter frequency range, but also has very low noise, high IRR, wide detectable frequencies (385–500 GHz), and a flat IF output spectrum. The balanced 2SB mixer is composed of three RF hybrids, four DSB (Double SideBand) mixers, two 180° IF hybrids, and an IF quadrature hybrid. Several important performance indicators such as noise temperature, IRR, required LO (Local Oscillator) power, and IF spectra were measured. The measured LO power required for the balanced 2SB mixer was typically ~ 14 dB less than that of the single-ended mixers.     

A 0.5–2.5 GHz 910 uW complementary LNA employing positive–negative feedback

A 0.5–2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S₁₁ < ?10 dB in the 0.5–2.5 GHz band. The noise figure (NF) is 3.9–5.0 dB and the IIP3 is 3.1–3.6 dBm. The power consumption is only 910 uW.     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

A 0.4–3.3 GHz low-noise variable gain amplifier with 35 dB tuning range, 4.9 dB NF,and 40 dBm IIP2

This work presents a low-noise variable gain amplifier (LNVGA) in which the IIP2 is very high, and the gain control is applied to improve the system dynamic range, even with the limitations of the CMOS technology. Two stages compose the LNVGA, a low-noise amplifier, that keeps the noise figure (NF) at low values, and a variable voltage attenuator (VVA), that provides the gain variation. We have applied on the VVA the phase cancellation technique, in which the addition of two out-of-phase signals controls the gain. This technique provides a large gain tuning range only if the paths of the two signalsto be added are well balanced; hence, a precise 180 degrees phase difference is required. In this desing we propose an active balun with small imbalance, which creates those signals. The LNVGA was implemented in 130 nm CMOS with a 1.2 V supply. The measurement results show a 35 dB gain tuning range, varying from 10 to ? 25 dB, a 4.9 dB minimum NF, a ? 10 dBm IIP3, and an IIP2 as high as + 40 dBm.     

Oscillateurs à TEC accordables par varactor dans la bande 18–40 GHz

This paper describes the design, analysis and experimental results of 18–26 GHz fundamental and 26–40 GHz doubler voltage controlled oscillator. They use field effect transistors and hyperabrupt GaAs varactor diodes. The interest of such circuits are a good integration, a high speed frequency tuning capability and a high frequency of oscillation allowing to achieve ultra wide bandVco by frequency transposition at lower frequencies.     

A 4.6 GHz cascade switched biasing LC–QVCO using source-body resistor

This paper presents a 4.6 GHz LC quadrature voltage-controlled oscillator (QVCO) in which the phase noise performance is improved by two methods: cascade switched biasing (CSB) technique and source-body resistor. The CSB topology can reduce the resonator loss caused by MOSFET resistance. Meanwhile, it can maintain the benefits of conventional switched biasing technique. The source-body resistors are utilized to reduce the noise contribution of the substrate related to the cross coupled MOSFETs. The proposed QVCO has been implemented in standard 0.18 μm CMOS technology. With the two methods mentioned above, it consumes 4.9 mW under 1 V voltage supply and achieves a phase noise of ?120.3 dBc/Hz at 1 MHz frequency offset from the carrier of 4.56 GHz. The figure of merit is 186.5 dBc/Hz and the tuning range is from 4.2 G to 5 GHz (17.3 %). When the QVCO operates at 0.8 V voltage supply, the power consumption is 2.88 mW and the phase noise is ?115.7 dBc/Hz at 1 MHz frequency offset from the carrier of 4.58 GHz.     

A 0.4–2.3 GHz broadband power amplifier extended continuous class-F design technology

A 0.4–2.3 GHz broadband power amplifier (PA) extended continuous class-F design technology is proposed in this paper. Traditional continuous class-F PA performs in high-efficiency only in one octave bandwidth. With the increasing development of wireless communication, the PA is in demand to cover the mainstream communication standards’ working frequencies from 0.4 GHz to 2.2 GHz. In order to achieve this objective, the bandwidths of class-F and continuous class-F PA are analysed and discussed by Fourier series. Also, two criteria, which could reduce the continuous class-F PA’s implementation complexity, are presented and explained to investigate the overlapping area of the transistor’s current and voltage waveforms. The proposed PA design technology is based on the continuous class-F design method and divides the bandwidth into two parts: the first part covers the bandwidth from 1.3 GHz to 2.3 GHz, where the impedances are designed by the continuous class-F method; the other part covers the bandwidth from 0.4 GHz to 1.3 GHz, where the impedance to guarantee PA to be in high-efficiency over this bandwidth is selected and controlled. The improved particle swarm optimisation is employed for realising the multi-impedances of output and input network. A PA based on a commercial 10 W GaN high electron mobility transistor is designed and fabricated to verify the proposed design method. The simulation and measurement results show that the proposed PA could deliver 40–76% power added efficiency and more than 11 dB power gain with more than 40 dBm output power over the bandwidth from 0.4–2.3 GHz.     

A low power CMOS phase-switching prescaler for 1.8–2.4 GHz wireless communications

A divide-by-31/32 phase switching prescaler with a simple divide-by-4 multi-phase ring counter is presented. By using this divide-by-4 unit, a low power consumption is obtained while a wide range operation is maintained. Fabricated with a standard 0.18 μm CMOS technology, the prescaler can work properly from 1.8 to 3.1 GHz with a maximum current dissipation of 1.3 mA from a 1.8 V supply voltage. It can cover most of wireless communication standards in 1.8/1.9 GHz and 2.4 GHz bands.     

A 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction technique

In this Letter, 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 ps_rms at 1.5 GHz operation, and 3.991 ps_rms at 400 MHz operation. The ADPLL occupies 0.088 mm², and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.     

WHB41型18～40GHz混频组件

ＷＨＢ４１型１８～４０ＧＨｚ混频组件南京电子器件研究所已研制成１８～４０ＧＨｚ下变频器组件。该组件由１８～４０ＧＨｚ宽带双平衡混频器，１６ＧＨｚＧａＡｓＦＥＴＤＲＯ（第１本振），４２ＧＨｚＧａＡｓＧｕｎｎＤＲＯ（第２本振）和１６～４２ＧＨＺ本振切换混...     

18—40GHz小型天线的扩展设计

为了满足舰船或飞机上最小空间的需要,成熟的微波技术正用于毫米波频谱的低波段,以便实现低造价和短的研制周期。     

A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications

A 2.4GHz CMOS monolithic transceiver front-end for IEEE 802.11b wireless LAN applications is presented.The receiver and transmitter are both of superheterodyne structure for good system performance.The front-end consists of five blocks:low noise amplifier,down-converter,up-converter, pre-amplifier,and LO buffer.Their input/output impedance are all on-chip matched to 50Ω except the down-converter which has open-drain outputs.The transceiver RF front-end has been implemented in a 0.18μm CMOS process.When the LNA and the down-converter are directly connected,the measured noise figure is 5.2dB,the measured available power gain 12.5dB,the input 1dB compression point -18dBm,and the third-order input intercept point -7dBm.The receiver front-end draws 13.6mA currents from the 1.8V power supply.When the up-converter and pre-amplifier are directly connected,the measured noise figure is 12.4dB,the power gain is 23.8dB,the output 1dB compression point is 15dBm,and the third-order output intercept point is 16dBm.The transmitter consumes 276mA current from the 1.8V power supply.     

A highly linear and fully-integrated FMCW synthesizer for 60 GHz radar applications with 7 GHz bandwidth

A highly linear and fully-integrated frequency-modulated continuous-wave (FMCW) generator based on a fractional-N phase-locked loop (PLL) that is able to synthesize modulation schemes in 57–64 GHz range is proposed in this paper. The fractional-N PLL employs Colpitts voltage-controlled oscillator (VCO) at 60 GHz with 13.5% tuning range. Automatic amplitude and frequency calibrations are implemented to avoid drifts due to process, voltage and temperature variations and to set the center frequency of the VCO. Five-stage multi-modulus divider is used for division ratio switching, controlled by the sigma-delta (\(\Sigma \Delta\)) modulator MASH 1-1-1. The frequency sweep (chirp) bandwidth and duration are fully programmable via serial peripheral interface allowing up to 16 different chirps in complex modulation scheme. The PLL reference signal is 250 MHz provided by external low-noise signal generator which is also used for digital modules clock. The overall PLL phase noise is lower than ?80 dBc/Hz at 10 kHz offset and the chirp linearity is better than 0.01%. The complete FMCW synthesizer is implemented and verified as a stand-alone chip in a commercially available SiGe HBT 130 nm BiCMOS technology. The total chip area is \(2.04\,\text {mm}^2\), and the total power consumption is 280 mW.     

A 6–9 GHz UWB balun-LNA employing current-reuse with preamplifier and CCC buffer

This paper presents a high-gain and low-power balun-LNA for ultra-wideband receiver operating in the upper band (6–9 GHz). Common gate (CG) preamplifier in front of the active balun can provide input matching and suppress noise from the follow-up stages. Active balun shares bias current with the CG stage to reduce power consumption. Capacitor-cross-coupled buffer is cascaded for signal amplitude and phase correction. The balun-LNA is fabricated in TSMC 130 nm CMOS technology and it consumes 5.5 mA current from a 1.3-V supply including buffer. This balun-LNA can achieve wideband gain from 6.5 to 9.0 GHz and the maximum gain is 23 dB. The input return loss is better than 20 dB from 6.5 to 9.0 GHz. The core area of the LNA is 0.53 mm². Simulated noise figure of the LNA is under 3.2 dB.