Optical detector to monitor plasma etching

A simple photodetector has been developed to monitor plasma etching of polysilicon, pyrolytic silicon nitride and reactive plasma deposited silicon nitride.     

Investigation of the Process of Plasma Through Etching of HkMG Stack of Nanotransistor with a 32-nm Critical Dimension

The processes of plasma etching of stack layers to form a structure of a metal gate of a nanoscale transistor with a dielectric with a high level of dielectric permittivity (HkMG) are investigated. A resist mask formed by fine-resolution electron-beam lithography is used in the etching. The plasma etching of the stack’s layers is carried out in one technological etching cycle without a vacuum break. The sequential anisotropic etching process of the stack of polysilicon, tantalum nitride, and hafnium nitride, as well as the etching process of the gate insulator based on hafnium oxide with a high degree of selectivity in relation to the underlying crystalline silicon, which guarantees the complete removal of the layer of hafnium oxide and the minimal loss of the silicon layer (not more than 0.5 nm), is investigated.     

Isotropic etch for SiO2 microcantilever release with ICP system

Inductively coupled plasma (ICP) system has been widely used for anisotropic silicon etching because it offers high aspect ratio with a vertical side wall. The isotropic etching capability of the ICP system, however, has not gained much attention, even though it possesses advantages in profile control and high etching rate over wet isotropic etching or conventional RIE (reactive ion etching). We report here an isotropic dry etching process to release microcantilever beams. Investigations have covered chamber pressure, plasma source power, substrate power, SF₆ (sulfur hexafluoride) flow rate relating to Si etching rate, undercutting rate, and isotropic ratio. The SiO₂ (silicon dioxide) cantilevers were successfully released from the Si substrate and the optimized silicon etching rate was 9.1 μm per minute. The etching profiles were analyzed by scanning electron micrographs (SEM).     

Ultra uniform arrays of micro patterns on large area substrate by employing wet chemical etching

A wet chemical selective etching process is presented to delineate ultra-uniform micro patterns in the form of arrays of sensor chips of 4 mm×4 mm size in the matrix of 9×9 on a 3″ diameter silicon substrate with uniform physical and electrical characteristics. The selective etching of thin film is confined to the top area by masking its outer edges. This leads to uniform etching of the entire film leading to ultra-uniform delineation of arrays of micro patterns. The process has been verified over the selective etching of doped polysilicon in defining the polysilicon resistors and subsequently has been applied on realizing Ti/Au interconnecting lines using wet chemical etchant. Experimental results are presented with physical and electrical characteristics of the patterned structures in the statistical form over the substrate surface. SEM analysis is carried out for physical dimension measurement and standard deviation of 0.0040 is observed in polysilicon micro patterning. The process is competitive with reactive ion etching (RIE) in terms of yield, reliability and repeatability with cost effectiveness in a production environment. Methodology of ultra-uniform etching on entire substrate area is developed in support of the experimental results. The ratio of Top Surface Area (TSA) and Total Exposed Surface Area (TESA) is shown as crucial parameter for the uniform etching of thin films.     

Optimization of ohmic contact and adhesion on polysilicon in MEMS-NEMS wet etching process

This paper presents the optimization of polysilicon doping and metallization to form ohmic contact with etching resistance. Indeed, polysilicon doped by ion implantation and ohmic contacts are an important and interesting part of integrated circuit technology or MEMS and NEMS. LPCVD-polysilicon doping parameters, such as ion energy, dose, and annealing were investigated. In particular a superficial implantation realized after a deep implantation enables one to slightly decrease the polysilicon resistivity while the contact resistance is reduced. And ohmic contacts with wet etching resistance were realized by depositing the different metallization stacks. We demonstrate that ohmic contact pad Cr/Pt/Au has provided a good adhesion on LPCVD-polysilicon after wet etching.     

Impact of polysilicon dry etching on 0.5 μm NMOS transistorperformance: the presence of both plasma bombardment damage and plasmacharging damage

Two types of damage mechanisms resulting from polysilicon gate dry etching are identified in 0.5 μm NMOS transistors. One type of damage is found to be active even after full processing and to result in positive charge at the edge of the gate oxide. It is found to have no correlation with polysilicon antenna ratio and to be attributable to direct plasma bombardment. The other type of damage is found to be passivated after full processing but it is activated by electrical stress. After activation, this damage is an increasing function of polysilicon antenna ratio as well as overetch percentage. This second type of damage is attributable to plasma charging     

Influence of the nature of the mask on polysilicon gate patterning in high density plasmas

High density plasma etching processes of polysilicon gates on thin gate oxide (4.5 nm) have been studied for sub-quarter micron device fabrication. The influence of the mask material on the etching performance has been investigated using either a photoresist mask or an oxide hard mask. Trenching phenomena can be observed at the edges of the gates with both types of mask. When using a photoresist mask, severe defects are formed in the gate oxide near the polysilicon gate, showing that the gate oxide has been preferentially etched during the process. We show that these defects can be attributed to the trenching induced by the main etching step of the process, which is transferred into the gate oxide before the overetch starts. The transfer of the trenching effect depends strongly on the polysilicon-to-oxide selectivity which is shown to be dependent on the presence of carbon in the process chamber. When replacing the photoresist mask by an oxide hard mask the polysilicon-to-oxide selectivity can be improved by a factor of greater than three. Therefore, the use of an oxide hard mask results in a larger process window without creating undesirable defects in the active areas of the devices.     

Advantages of plasma etch modeling using neural networks overstatistical techniques

Due to the inherent complexity of the plasma etch process, approaches to modeling this critical integrated circuit fabrication step have met with varying degrees of success. Recently, a new adaptive learning approach involving neural networks has been applied to the modeling of polysilicon film growth by low-pressure chemical vapor deposition (LPCVD). In this paper, neural network modeling is applied to the removal of polysilicon films by plasma etching. The plasma etch process under investigation was previously modeled using the empirical response surface approach. However, in comparing neural network methods with the statistical techniques, it is shown that the neural network models exhibit superior accuracy and require fewer training experiments. Furthermore, the results of this study indicate that the predictive capabilities of the neural models are superior to that of their statistical counterparts for the same experimental data     

Effects of plasma etching chemistry and post-processing on themechanical adhesion and electrical contact of double polysilicon layerstructures

Double polysilicon layer structures separated by a silicon nitride layer are frequently used as structural multilayers in surface micromachining. In this paper the effect of three types of plasma etching chemistries for nitride patterning and post-processing on the characteristics of both mechanical adhesion and electrical contact resistance between the two polysilicon layers is investigated. It was found that all three chemistries yielded good mechanical adhesion between the two polysilicon layers. Both the chemistry based on CF₄ /SF₆, with a poor selectivity (0.7) of etching nitride over the underlying polysilicon layer, and the chemistry based on CHF ₃/CF₄, with a selectivity of 3, provided good electrical contact. The chemistry based on CHF₃/N₂, which yielded a selectivity of 15, on the other hand, resulted in a polymer film between the two polysilicon layers, resulting in electrical insulation. This polymer film can be effectively removed by using post-processing, which involves in-situ oxygen plasma treatment. Therefore, a chemistry such as that based on CHF₃/CF₄ can be applied when the lower polysilicon thickness allows a moderate selectivity, whereas the CHF₃/N ₂ chemistry is favored when high-selectivity is required. The latter, however, requires in-situ post-processing     

Electron cyclotron resonance plasma etching of HgTe-CdTe superlattices grown by photo-assisted molecular beam epitaxy

In order to form HgTe-CdTe superlattice diode arrays, a well-controlled etch process must be developed to form mesa structures on HgTe-CdTe superlattice layers. Wet etch processes result in nonuniform, isotropic etch profiles, making it difficult to control etch depth and diode size. In addition, surface films such as a Te-rich layer may result after wet etching, degrading diode performance. Recently, a dry etch process for HgTe-CdTe superlattice materials has been developed at Martin Marietta using an electron cyclotron resonance plasma reactor to form mesa diode structures. This process results in uniform, anisotropic etch characteristics, and therefore may be a better choice for etching superlattice materials than standard wet etch processes. In this paper, we will present a comparison of etch processes for HgTe-CdTe superlattice materials using electron microscopy, scanning tunneling microscopy, surface profilometry, and infrared photoluminescence spectroscopy to characterize both wet and dry etch processes.     

硅化钨/多晶硅复合栅的反应离子刻蚀工艺研究

本文介绍用SF_6+O_2,SF_6+Cl_2作腐蚀剂,反应离子刻蚀(RIE)的硅化钨/多晶硅复合栅工艺。着重研究了各工艺参数的改变对硅化钨和多晶硅刻蚀结果的影响,和刻蚀复合栅结构的最佳工艺条件。     

A general simulator for VLSI lithography and etching processes: Part II—Application to deposition and etching

The extension of the general process simulator SAMPLE to plasma etching and metallization is described. The etching algorithm is divided into isotropic, anisotropic, and direct milling components and is suitable for modeling wet etching, plasma etching, reactive ion etching, and ion milling. Separate deposition algorithms are used for CVD, sputtering, and planetary deposition. With the extension, it is possible to use a simple keyword repertoire to simulate a sequence of photolithography, etching, and deposition steps to obtain device cross sections at each stage of fabrication.     

微波等离子体刻蚀技术研究

以Corial 200M型干法刻蚀机的三种刻蚀模式为基础,分析了微波等离子体刻蚀技术的优缺点．并讨论了下电极结构对干法刻蚀形貌、一致性和重复性的影响。利用微波等离子体刻蚀技术与反应离子刻蚀技术相结合,实现了SiO2各向同性刻蚀,成功应用于质量控制和失效分析等环节。     

1-µm MOS process using anisotropic dry etching

Anisotropic and selective etching of silicon has been obtained using a planar-reactive sputter-etching system and CCl3F gas. The Si to SiO2etch-rate ratio was 5 : 1. This etch process in CCl3F was interpreted as mainly involving physical reaction as opposed to etching in SF6. The influence of reactive sputter etching on junction leakage and threshold voltage shift, in comparison with a conventional wetetch process, could not be observed in the electrical characteristics of polysilicon gate MOS devices. An all dry-etched MOS process, consisting of an anisotropic etching for Si3N4, polysilicon, SiO2, and aluminum, was applied to the fabrication of a 1-kbit static RAM with 1-µm minimum geometry. It was confirmed that this anisotropic etching technology was useful for very fine-geometry patterning and could be applied to a 1-µm MOSLSI manufacturing process.     

Advanced etching of silicon based on deep reactive ion etching for silicon high aspect ratio microstructures and three-dimensional micro- and nanostructures

Different processes involving an inductively coupled plasma reactor are presented either for deep reactive ion etching or for isotropic etching of silicon. On one hand, high aspect ratio microstructures with aspect ratio up to 107 were obtained on sub-micron trenches. Application to photonic MEMS is presented. Isotropic etching is also used either alone or in combination with anisotropic etching to realize various 3D shapes.     

颗粒对CCD光刻图形完整性的影响分析

分析了薄膜淀积工艺、光刻工艺和刻蚀工艺过程中引入的颗粒对光刻图形完整性的影响。采用三相三次多晶硅工艺,光刻制备沟阻或多晶硅时,颗粒阻碍曝光和刻蚀,引起沟阻或多晶硅连条,使CCD的像元划分和信号电子的定向转移遭受破坏,降低器件成品率。     

High density, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging

A novel micro-electromechanical system (MEMS) package has been developed based on modular, reconfigurable components such as substrate, cap, bond region and through-wafer electrical interconnect (TWEI). The paper presents the details of the process for the fabrication of high density, high aspect ratio TWEIs that includes deep dry etching holes through the substrate, depositing an insulation layer and depositing a conductive layer. Two different processes to make the TWEI have been developed: Post-Process where the TWEI is fabricated after the fabrication of MEMS devices and Pre-Process where the TWEI is fabricated before the fabrication of MEMS device. For both processes, the interconnect holes are created by an anisotropic etching process-inductively coupled plasma (ICP) etching. For the post-process, a silicon dioxide layer was deposited in a plasma enhanced chemical vapor deposition (PECVD) chamber to insulate the interconnect holes. For the pre-process, the PECVD process was replaced with a thermal oxide growth step to ensure a more conformal oxide coating. Three different ways to deposit a conductive layer after deposition of an insulation layer have been practiced: sputtering Cu, electroplating Cu and low-pressure chemical vapor deposition (LPCVD) of phosphorus doped polysilicon. The electrical performance of the TWEIs achieved in each way was measured, analyzed and discussed.     

The honeycomb-shape capacitor structure for ULSI DRAM

A way to increase the charge stored in polysilicon capacitors using surface modulation technology is proposed. Asperities on the polysilicon surface are achieved by reactive ion etching (RIE) of the polysilicon, using the oxide at the grain boundary as a mask. The fabricated polysilicon electrode has a honeycomb shape. With this structure, the capacitance is increased by four times for a polysilicon storage electrode of 250-nm thickness. The leakage current is comparable to that of convection stacked capacitors (STCs)     

Dual-polarity, single-resist mixed (e-beam/photo) lithography

A lithographic process is described which involves electron-beam exposure of the small geometries of an integrated circuit pattern and optical exposure of the large geometries onto the same resist layer. A single development step produces both electron and optical images. With the use of a diazo-type resist, either positive or negative e-beam images can be obtained, so that suitable selection of the photomask tone allows complete flexibility in the choice of polarity of the composite pattern. Using AZ-2415, e-beam defined features as small as 0.4 µm joining large optically defined pads have been produced in doped polysilicon by plasma etching.     

A novel technology to reduce the antenna charging effects duringpolysilicon gate electron-cyclotron-resonance etching

A novel technique, which uses Cl₂/O₂ mixed gas in the electron cyclotron resonance (ECR) etching system, has been proposed to remove the antenna charging effect of the MOS capacitors with 5-nm-thick oxides during polysilicon gate etching. The Cl₂ /O₂ can cause the trenching effect and prevents the gate oxide from the charging damage. Furthermore, the ECR system can provide high polysilicon/oxide selectivity so that the Si substrate under gate oxide is not directly bombarded by the ions. Consequently, the E_bd degradation of the MOS capacitors disappears as the trenching effect is apparent by using moderate Cl₂/O₂ mixed gas