EV8AQ160型ADC在2.5 Gsps双通道高速信号采集系统中的应用

针对某高速实时频谱仪中的高速模数转换器(ADC)的应用,基于信号采集系统硬件平台,介绍了一种最大采样率可达5 Gbps的高速8位A/D转换器EV8AQ160。该器件内部由4路并行的ADC构成,各路ADC可并行工作也可交错工作。详细描述了EV8AQ160在交错模式下的工作原理,介绍了其在某双通道高速信号采集系统中的应用,给出了EV8AQ160与Xilinx公司Virtex-6 FPGA的接口设计方案以及系统结构框图,并用ISE的在线逻辑分析仪(ChipScope Pro)测试了ADC性能。把ADC输出的数据存储在DDR3中,然后进行FFT变换,进而分析ADC的信噪比及有效位数,实测表明整体指标达到设计要求。     

LSB split capacitor SAR ADC with 99.2% switching energy reduction

A highly energy efficient capacitor switching technique in a successive approximation register (SAR) analog to digital converter (ADC) for biomedical applications is presented. The proposed scheme based on new switching method, which combine the LSB split capacitive technique and monotonic method can reduce the average switching energy by 99.2% compared to the conventional SAR architecture. Besides reducing energy in each comparison cycle, the suggested method also achieves an 8× reduction in total capacitance used in the digital to analog converter over the conventional one with the same resolution. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.     

基于FLI32626H芯片的平板电视ADC快速校正方法

目前平板电视的使用还是以模拟信号输入为主，电视整机表现好坏与模拟通道信号采集使用的ADC模块密切相关，ADC校正的准确与否直接影响到后端处理及显示效果。提出一种基于Genesis FLI32626H数字化处理电视芯片，快速校正平板电视各模拟通道ADC的软件方法，实际应用证明使用该方法有效缩短了校正时间且校正效果良好，该方法也适用于多款同类型数字化处理电视芯片，具有一定的普遍性。     

Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation

The paper describes the implementation of a novel Analog-to-Digital-Converter (ADC) test technique for next generation low cost massive parallel ADC testing using a Field Programmable Gate Array (FPGA) on tester load board. The goal is to test the ADC which is embedded in an automotive micro controller with only pure digital tester sources. Therefore, the analog test stimulus for the ADC is generated by using ΔΣ-modulation technique off-line and analog filtering on load board. The digital test response is analyzed by a FPGA in real time by comparing the measured data with a reference signal. The modular concept of FPGA evaluation allows for quick and flexible reaction on changing production test requirements. Simply by reprogramming the FPGA with a new module there is no need of any hardware reconfigurations. Measurements with a high precision reference ADC in laboratory environment show that the method is ready for production.     

A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2with mixed-signal chopping and calibration

This paper describes a two-step analog-to-digital converter (ADC) with a mixed-signal chopping and calibration algorithm. The ADC consists primarily of analog blocks, which do not suffer from the matching limitations of active devices. The offset on two residue amplifiers limits the accuracy of the ADC. Background digital offset extraction and analog compensation is implemented to continuously remove the offset of these critical analog components. The calibrated two-step ADC achieves -70 dB THD in the Nyquist band, with a 2.5-V supply. The ADC is realized in standard single-poly 5-metal 0.25-μm CMOS, measures 1.0 mm² , and dissipates 295 mW     

Adaptive prediction and cancellation digitization method for wideband multistandard software radio base-station receivers

In this study, a new method for digitizing a combination of different analog signals occupying significantly different bandwidths and having a very high dynamic range is proposed and analyzed. Since it is based upon signal-prediction/cancellation principles, it is referred to as adaptive prediction and cancellation digitization (APCD) method and is applied to various families of signals simultaneously received by a multistandard software radio (SWR) base-station receiver. It is shown theoretically and by means of computer simulations that the APCD method can effectively reduce the high dynamic range of the signals before digitization takes place. Hence, the stringent analog-to-digital-converter (ADC) resolution requirements imposed by the operation of such SWR base-station receivers can be significant relaxed. The signal dynamic-range reduction is achieved by applying appropriate signal processing techniques, e.g., autoregressive (AR) and periodic autoregressive (PAR) prediction. Such techniques allow accurate prediction and subsequent cancellation of high-power narrowband signals present among the composite received analog signal. As these signals usually have cyclostationary statistical characteristics, analysis and performance evaluation of AR and PAR predictors, when used to predict cyclostationary signals, were presented. A new adaptive algorithm for implementing the PAR predictor is also proposed, and its validity is justified by theoretical analysis as well as by various performance evaluation results obtained by means of computer simulations.     

A CMOS 6-b, 400-MSample/s ADC with error correction

A CMOS 6-bit 400-MSample/s (MS/s) flash analog/digital converter (ADC) using an additional comparator for background autozeroing has been developed. Additionally, an error-correction technique detects and corrects errors after thermometer code zero-to-one transition detection, improving the error rate from 10E-4 to 10E-8 at 400 MS/s with a 200-MHz analog input. This ADC was fabricated in a single-poly, double-metal, 0.35-μm CMOS technology and occupies 1.6×0.75 mm. The power consumption is 190 mW at 400 MS/s with 3.0 V power supply. This ADC has a two-clock cycle latency     

A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration

We present a new noise shaping method and a dual-polarity calibration technique suited for successive approximation register type analog to digital converters (SAR–ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR–ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3 μW power with 1.8 V supply.     

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64μA quantization range and a 5 V supply voltage/±256μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46dB, DNL/INL are -0.005 to +0.027 LSB/-0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.     

ADC模拟输入阻抗测试及窄带网络匹配技术

讨论了高速流水线ADC模拟输入前端的一般结构及其等效模型,在此基础上介绍了该类型ADC模拟输入端的阻抗测量原理和一种适用于窄带应用的ADC模拟输入端谐振匹配网络设计方法。最后,以某14位250 MS/s无缓冲ADC为例,详细介绍了模拟输入阻抗测量以及匹配设计步骤,并给出匹配优化后的测试结果。     

A CMOS image sensor with analog two-dimensional DCT-basedcompression circuits for one-chip cameras

This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable quantization level analog-to-digital converter (ADC). The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed. The small and low-power nature of the analog design allows us to achieve low-power, low-cost, one-chip digital video cameras. The 8×8-point analog 2-D DCT processor is designed with fully differential switched-capacitor circuits to obtain sufficient precision for video compression purposes. An imager array has a dedicated eight-channel parallel readout scheme for direct encoding with the analog 2-D DCT processor. The variable level quantization after the 2-D DCT can be performed by the ADC at the same time. A prototype CMOS image sensor integrating these core circuits for compression is implemented based on triple-metal double-polysilicon 0.35-μm CMOS technology. Image encoding using the implemented analog 2-D DCT processor to the image captured by the sensor is successfully performed. The maximum peak signal-to-noise ratio (PSNR) is 36.7 dB     

A power-adaptable A/D converter with integrated data compression

A novel adaptable analog/digital converter (ADC) that combines analog/digital conversion and entropy-coding for integrated data compression and low-power operation is reported. The converter has high flexibility of operation in terms of adaptable resolution, conversion rate and input signal statistics. This feature allows to adaptively react to changes of the situation and to put the device in each case into the optimum configuration. The ADC has been realized in a 0.6 μm CMOS technology with a peak resolution of 12 bit and 200 kS/s maximum sampling rate. A comprehensive power model of the converter is presented that reflects precisely the power consumption determined from experiments. The model is very useful for optimizing the converter configuration in the node of a wireless sensor network for specific situations. A feasible real-life application is demonstrated.     

自动切换转换通道的A/D转换器AD7938及其应用

AD7938是AD公司推出的新型12位高速8输入通道模数转换器，片内自带顺序管理器，能智能切换转换通道，通道接入方式可设定为8路单端、4路差分、4路或7路准差分等4种方式，支持字和字节模式的并行接口，内置2．5V参考电压源，模拟、数字电源分开供电且可不同，软件设定输入电压范围和输出数据格式，功耗很低并具待机、停机模式，使用非常灵活方便。本文介绍了其功能特性和使用方法，并介绍了其与EZ-USB AN2131QC接口，应用于基于USB接口的数据采集卡中的方法。     

A 1-V 5-bit 0.5 GS/s time-based flash ADC in 0.18 µm CMOS technology

A novel low-voltage rail-to-rail parallel time-based analog-to-digital converter (ADC) is proposed. The proposed ADC works like a conventional flash ADC except that the process is performed in the time-domain. Since the operation of analog integrated circuits at low supply voltages is limited, converting the voltage signals to the time domain improves the efficiency of the circuit. In this paper, a constant-delay ladder is utilized to make the reference delay-times to compare with the input signal. A 1-V 5-bit 500 MS/s ADC has been designed and simulated in 0.18 µm CMOS technology consumed 3.66 mW. The simulation results show 0.3lsb and 0.2lsb for INL and DNL respectively. Signal-to-noise and distortion ratio (SNDR) of the proposed ADC is 26.7 dB at Nyquist frequency. The rail-to-rail operation and linearity of the voltage-to-time converter (VTC) improved the efficiency of the ADC comparing to the similar time-based ADCs. The figure-of-merit (FoM) of the ADC is about 0.31 (pJ/conv.step).

     

多通道高速ADC电路PCB设计技术浅谈

ADC是将模拟信号转换为数字信号的芯片,它在电路系统中的作用决定了它必然和其它大量数字电路一起使用,所以在其PCB设计中除了需要考虑一般PCB设计中要注意的问题之外,还要在多方面引起特别注意,尤其是在高速应用中。本文就针对多通道高速ADC电路设计的特点,以E2V公司的EV10AQ190芯片为例,重点讨论了包含多通道高速ADC的硬件电路设计中印刷电路板布局时所必须引起注意的问题,包括数字地和模拟地。数字电源和模拟电源的处理,ADC输入信号的隔离问题,采样时钟的处理和输出信号的阻抗匹配等问题。     

Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC

This paper presents a prototype of 14 bit 80 kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redundancy of non-binary ADC tolerates the non-idealities of analog components such as capacitor mismatch and finite amplifier DC gain, the design consideration of this high accuracy ADC can be only focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier without any high accuracy analog components. The proposed proof-of-concept cyclic ADC has been designed and fabricated in TSMC 90 nm CMOS technology. Measured SNDR = 81.9 dB is achieved at Fs = 80 kSPS with a simple radix-value estimation technique. No other complicated digital calibration is used to compensate the non-linearity of ADC caused by MOM capacitors and a poor gain of the amplifier as low as 66 dB. Measured DNL is ? 0.6/+ 0.67 LSB and INL is ? 1.2/+ 1.6 LSB. Prototype ADC dissipates 8mW at supply voltage is 3.3 V in analog circuits.     

光学Sigma-Delta模数转换器的研究进展

采用光学模数转换技术已经成为高转换速率、高比特精度模数转换器(ADC)的发展趋势.光学Sigma-Delta ADC作为一种光学ADC,具有转换精度高和模拟电路简单等显著优点.介绍了光学Sigma-Delta ADC的基本原理,详细阐述了几种典型的光学Sigma-Delta ADC的系统结构,对不同结构的光学Sigma-Delta ADC的优缺点进行了归纳总结.     

Ultra-wideband analog-to-digital conversion via signal expansion

We consider analog to digital (A/D) conversion, based on the quantization of coefficients obtained via the projection of a continuous time signal over a set of basis functions. The framework presented here for A/D conversion is motivated by the sampling of an input signal in domains which may lead to significantly less demanding A/D conversion characteristics, i.e., lower sampling rates and lower bit resolution requirements. We show that the proposed system efficiently parallelizes the analog to digital converter (ADC), which lowers the sampling rate requirements by increasing the number of basis functions on which the continuous time signal is projected, leading to a tradeoff between sampling rate reduction and system complexity. Additionally, the A/D conversion resolution requirements can be reduced by optimally assigning the available number of bits according to the variance distribution of the coefficients obtained from the signal projection over the new A/D conversion domain. In particular, we study A/D conversion in the frequency domain, where samples of the continuous signal spectrum are taken such that no time aliasing occurs in the discrete time version of the signal. We show that the frequency domain ADC overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. The proposed A/D conversion method is compared with conventional ADCs based on pulse code modulation (PCM). Fundamental figures of merit in A/D conversion and system tradeoffs are discussed for the proposed ADC. The signal-to-noise and distortion ratios of the frequency domain ADC are presented, which quantify the impact of the most critical impairments of the proposed ADC technique. We also consider application to communications receivers, and provide a design example of a multi-carrier UWB receiver.     

A 12-bit 10-MS/s SAR ADC with a weighted sampling time technique applied to C-DAC

This paper presents a low power 12-bit 10-MS/s successive approximation register (SAR) analog-to-digital convert (ADC) for bio-signal signal processing in wearable sensor systems. A weighted sampling time technique applied to a capacitor digital to analog converter (C-DAC) is employed to reduce the power consumption of the conventional SAR ADC with minimum performance sacrifice. The proposed technique helped reduce its energy consumed by MSB, MSB-1, MSB-6, and MSB-7 capacitors by more than 40% compared with that of the conventional C-DAC. Another technique, a voltage scaling method is also employed to lower the power supply voltage from 1.2 to 0.6 V for all the digital logics except the output registers, such that it results in a power reduction of 70%. The proposed ADC is implemented with the standard CMOS 65 nm 1-poly 6-metal n-well process. The ADC achieves DNL/INL of?±?1.2LSB/?±?1.5LSB, ENOB of 10.3-b, power consumption of 31.2 μW, and Walden FoM of 2.7fJ/step.

     

A dual 4-bit 2-Gs/s full Nyquist analog-to-digital converter usinga 70-ps silicon bipolar technology with borosenic-poly process andcoupling-base implant

A dual 4-b analog-to-digital converter (ADC) with Nyquist operation to 2 gigasamples/second (Gs/s) and -29-dBc distortion at 1 GHz is presented. A novel evaluation method using an integral digital-to-analog converter is introduced. A trench-isolated, self-aligned, double-polysilicon bipolar process is used for the chip fabrication. This ADC has a resolution of 3.73 effective bits at 1-GHz analog input signal, without the use of a preceding sample-and-hold. Low-frequency untrimmed distortion is -48 dBc (not including quantizing error), and is independent of the sample rate of 2 Gs/s