Leakage Power Analysis and Reduction for Nanoscale Circuits

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.     

估计CMOSVLSI芯片的功耗

介绍了估计ＣＭＯＳＶＬＳＩ芯片的功耗的基本方法和功耗对封装的要求。     

CMOS VLSI芯片中的电源总线噪声

本文介绍了ＣＭＯＳ ＶＬＳＩ芯片中电源总线噪声产生机理和对电路正常操作的影响。通过ＶＬＳＩ芯片版图设计技巧和对输出驱动器进行噪声限制,达到对电源总线噪声的有效控制。     

The VLSI Control Structure of a CMOS Microcomputer

By implementing novel microprogram control structures in CMOS, the designers of the 8-bit HD-6301 achieved high performance and low power consumption.     

纳米级CMOS电路的漏电流及其降低技术

随着CMOS工艺的进一步发展，漏电流在深亚微米CMOS电路的功耗中变得越来越重要。因此，分析和建模漏电流的各种不同组成部分对降低漏电流功耗非常重要，特别是在低功耗应用中。本文分析了纳米级CMOS电路的各种漏电流组成机制并提出了相应的降低技术。     

Majorization Minimization Technique for Optimally Solving Deep Dictionary Learning

The concept of deep dictionary learning (DDL) has been recently proposed. Unlike shallow dictionary learning which learns single level of dictionary to represent the data, it uses multiple layers of dictionaries. So far, the problem could only be solved in a greedy fashion; this was achieved by learning a single layer of dictionary in each stage where the coefficients from the previous layer acted as inputs to the subsequent layer (only the first layer used the training samples as inputs). This was not optimal; there was feedback from shallower to deeper layers but not the other way. This work proposes an optimal solution to DDL whereby all the layers of dictionaries are solved simultaneously. We employ the Majorization Minimization approach. Experiments have been carried out on benchmark datasets; it shows that optimal learning indeed improves over greedy piecemeal learning. Comparison with other unsupervised deep learning tools (stacked denoising autoencoder, deep belief network, contractive autoencoder and K-sparse autoencoder) show that our method supersedes their performance both in accuracy and speed.     

VLSI数据库系统的物理设计和实现技术

在VLSI芯片的设计过程中,所牵涉到的设计数据的数量是巨大的,数据库管理系统则起着十分重要和不可替代的作用。本文依据VLSI设计过程的特点和要求以及设计数据的类型与特征,研讨适用于VLSI CAD系统中的数据库管理系统的物理设计和实现问题,同时给出一个实际设计的VLSI数据库系统的数据模型和组织方式以及物理结构。     

深亚微米CMOS电路漏电流快速模拟器

随着工艺的发展 ,功耗成为大规模集成电路设计领域中一个关键性问题 降低电源电压是减少电路动态功耗的一种十分有效的方法 ,但为了保证系统性能 ,必须相应地降低电路器件的阈值电压 ,而这样又将导致静态功耗呈指数形式增长 ,进入深亚微米工艺后 ,漏电功耗已经能和动态功耗相抗衡 ,因此 ,漏电功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫 诸如HSPICE的精确模拟器可以准确估计漏电功耗 ,但仅仅适合于小规模电路 首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应 ,然后提出了快速模拟器的漏电模型 ,最后通过对ISCAS85& 89基准电路的实验 ,说明了在精度许可 (误差不超过 3% )的前提下 ,模拟器获得了成百倍的加速 ,同时也解决了精确模拟器的内存爆炸问题     

低功耗CMOS静态随机存储器设计技术

针对目前低功耗CMOS静态存储器的需求,简要介绍了存储器的结构和操作过程,分析了存储器功耗的主要来源,给出了相应的低功耗电路的设计方法,并对各种低功耗电路设计技术进行了总结。     

计算机伪信息泄漏技术的研究

简要叙述了计算机的防信息泄漏措施,介绍了伪信息泄漏技术,详细分析了白噪声法、相关噪声法和相关视频信号法。     

Crossing Minimization for Symmetries

We consider the problem of drawing a graph with a given symmetry such that the number of edge crossings is minimal. We show that this problem is NP-hard, even if the order of orbits around the rotation center or along the reflection axis is fixed. We devise an O(m log m) algorithm for computing a crossing minimal drawing if inter-orbit edges may not cross orbits, showing in particular that intra-orbit edges do not contribute to the NP-hardness of the crossing minimization problem for symmetries.     

微机电磁信息泄漏与防护技术

当今型计算机已广泛应用于国防军事领域，正府机要部门等。叙述了耿防止运中电磁信息的射，传导方式泄漏，在印电路板要部门等     

利用防火墙技术处理局域网安全漏洞

因局域网越来越多地遭到黑客的攻击,其安全性成为一个至关重要的问题。本文基于网络体系结构、TCP／IP协议存在安全漏洞、防火墙技术的分析和探讨,指出防火墙技术能处理许多TCP／IP协议的安全漏洞     

嵌入式系统中CMOS图像传感器接口技术

提出了CMOS（互补金属氧化物半导体）图像传感器在嵌入式系统中的接口技术，通过设计软件驱动使嵌入式处理器能够控制CMOS图像传感器图像数据自动采集。并对CMOS图像传感器采集的数据进行插值和自动白平衡处理。此接口模块已经成功地应用于二维条码识读器的图像采集模块中，取得了良好的效果。     

嵌入式系统中CMOS图像传感器接口技术

提出了CMOS(互补金属氧化物半导体)图像传感器在嵌入式系统中的接口技术,通过设计软件驱动使嵌入式处理器能够控制CMOS图像传感器图像数据自动采集.并对CMOS图像传感器采集的数据进行插值和自动白平衡处理.此接口模块已经成功地应用于二维条码识读器的图像采集模块中,取得了良好的效果.     

Minimization Problems for Parity OBDDs

Parity Ordered Binary Decision Diagrams (⊕OBDDs) are a data structure for boolean functions that extends the well-known OBDDs and reduces the representation size for several functions. Both data structures share the problem that the representation size strongly depends on the chosen variable order. For ⊕OBDDs the number of edges and thus the representation size is also influenced by the choice of the basis of the represented vector space. In this paper the hardness of some minimization problems for ⊕OBDDs is proven, namely, that there is no polynomial time approximation scheme for minimizing the number of nodes by choosing the variable order and for minimizing the number of edges, where the variable order may be changed or is fixed, unless P=NP.     

Computer Vision for Nanoscale Imaging

The main goal of Nanotechnology is to analyze and understand the properties of matter at the atomic and molecular level. Computer vision is rapidly expanding into this new and exciting field of application, and considerable research efforts are currently being spent on developing new image-based characterization techniques to analyze nanoscale images. Nanoscale characterization requires algorithms to perform image analysis under extremely challenging conditions such as low signal-to-noise ratio and low resolution. To achieve this, nanotechnology researchers require imaging tools that are able to enhance images, detect objects and features, reconstruct 3D geometry, and tracking. This paper reviews current advances in computer vision and related areas applied to imaging nanoscale objects. We categorize the algorithms, describe their representative methods, and conclude with several promising directions of future investigation.     

A Spill Code Minimization Technique—Application in the Metrowerks StarCore C Compiler

Graph coloring algorithms have been shown to be an efficient and effective means of performing register allocation. The power of these algorithms lies in their strong coloring heuristics and their ability to abstract away disparate allocation problems such as data-flow constraints, conforming to calling conventions, and target machine restrictions. However, even optimal algorithms cannot color every graph, and often some live ranges must be spilled to memory to make room for others. In this paper, we present a new approach of reducing spill code, which can be used to complement virtually any register allocation algorithm, and provides a good support to implement cheaper spill methods like spilling to another register (from a different class) and rematerialization (reloading the register from a constant or expression). This algorithm was partially implemented into the Metrowerks StarCore C compiler where it has proven its efficiency in terms of both cycle count and code size.