Leakage Power Analysis and Reduction for Nanoscale Circuits

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.     

估计CMOSVLSI芯片的功耗

介绍了估计ＣＭＯＳＶＬＳＩ芯片的功耗的基本方法和功耗对封装的要求。     

The VLSI Control Structure of a CMOS Microcomputer

By implementing novel microprogram control structures in CMOS, the designers of the 8-bit HD-6301 achieved high performance and low power consumption.     

CMOS VLSI芯片中的电源总线噪声

本文介绍了ＣＭＯＳ ＶＬＳＩ芯片中电源总线噪声产生机理和对电路正常操作的影响。通过ＶＬＳＩ芯片版图设计技巧和对输出驱动器进行噪声限制,达到对电源总线噪声的有效控制。     

面向VLSI的门级单粒子效应评估技术

由于空间辐射环境充满了各类射线和高能粒子，非常容易诱发集成电路发生单粒子效应，因此有必要开发对应的评估技术，分析单粒子效应对超大规模集成电路（VLSI）的影响。以ISCAS89测试基准电路为主要研究对象，提出了一种适用于VLSI的单粒子效应评估技术，可以通过脚本自动生成仿真和测试文件，实现任意节点的故障注入，并可以在任何一种支持硬件描述语言的EDA仿真工具上进行评估。分别对使用三模冗余技术、自刷新寄存器技术加固后的电路和原始电路进行了对比评估。评估结果符合逻辑，验证了门级单粒子效应评估测试技术的有效性。通过提出的评估技术，可以快速评估电路的抗辐射能力，提高查找设计缺陷、对电路进行针对性加固的效率，对于提高集成电路的安全性和稳定性有着重要的应用价值。     

纳米级CMOS电路的漏电流及其降低技术

随着CMOS工艺的进一步发展，漏电流在深亚微米CMOS电路的功耗中变得越来越重要。因此，分析和建模漏电流的各种不同组成部分对降低漏电流功耗非常重要，特别是在低功耗应用中。本文分析了纳米级CMOS电路的各种漏电流组成机制并提出了相应的降低技术。     

Majorization Minimization Technique for Optimally Solving Deep Dictionary Learning

The concept of deep dictionary learning (DDL) has been recently proposed. Unlike shallow dictionary learning which learns single level of dictionary to represent the data, it uses multiple layers of dictionaries. So far, the problem could only be solved in a greedy fashion; this was achieved by learning a single layer of dictionary in each stage where the coefficients from the previous layer acted as inputs to the subsequent layer (only the first layer used the training samples as inputs). This was not optimal; there was feedback from shallower to deeper layers but not the other way. This work proposes an optimal solution to DDL whereby all the layers of dictionaries are solved simultaneously. We employ the Majorization Minimization approach. Experiments have been carried out on benchmark datasets; it shows that optimal learning indeed improves over greedy piecemeal learning. Comparison with other unsupervised deep learning tools (stacked denoising autoencoder, deep belief network, contractive autoencoder and K-sparse autoencoder) show that our method supersedes their performance both in accuracy and speed.     

VLSI数据库系统的物理设计和实现技术

在VLSI芯片的设计过程中,所牵涉到的设计数据的数量是巨大的,数据库管理系统则起着十分重要和不可替代的作用。本文依据VLSI设计过程的特点和要求以及设计数据的类型与特征,研讨适用于VLSI CAD系统中的数据库管理系统的物理设计和实现问题,同时给出一个实际设计的VLSI数据库系统的数据模型和组织方式以及物理结构。     

深亚微米CMOS电路漏电流快速模拟器

随着工艺的发展 ,功耗成为大规模集成电路设计领域中一个关键性问题 降低电源电压是减少电路动态功耗的一种十分有效的方法 ,但为了保证系统性能 ,必须相应地降低电路器件的阈值电压 ,而这样又将导致静态功耗呈指数形式增长 ,进入深亚微米工艺后 ,漏电功耗已经能和动态功耗相抗衡 ,因此 ,漏电功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫 诸如HSPICE的精确模拟器可以准确估计漏电功耗 ,但仅仅适合于小规模电路 首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应 ,然后提出了快速模拟器的漏电模型 ,最后通过对ISCAS85& 89基准电路的实验 ,说明了在精度许可 (误差不超过 3% )的前提下 ,模拟器获得了成百倍的加速 ,同时也解决了精确模拟器的内存爆炸问题     

Leakage current estimation of CMOS circuit with stack effect

Leakage current of CMOS circuit increases dramatically with the technology scaling down and has become a critical issue of high performance system. Subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakages are considered three main determinants of total leakage current. Up to now, how to accurately estimate leakage current of large-scale circuits within endurable time remains unsolved, even though accurate leakage models have been widely discussed. In this paper, the authors first dip into the stack effect of CMOS technology and propose a new simple gate-level leakage current model. Then, a table-lookup based total leakage current simulator is built up according to the model. To validate the simulator, accurate leakage current is simulated at circuit level using popular simulator HSPICE for comparison. Some further studies such as maximum leakage current estimation, minimum leakage current generation and a high-level average leakage current macromodel are introduced in detail. Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage current estimation methods are very accurate and efficient.     

低功耗CMOS静态随机存储器设计技术

针对目前低功耗CMOS静态存储器的需求,简要介绍了存储器的结构和操作过程,分析了存储器功耗的主要来源,给出了相应的低功耗电路的设计方法,并对各种低功耗电路设计技术进行了总结。     

一种CMOS图像传感器列FPN抑制技术

介绍CMOS图像传感器列并行读出电路中,采用CDS电路以抑制像素FPN、复位噪声等,但导致列FPN的工作原理.为了消除列FPN,提出了一种仪器放大器配置的精确平衡差分输出的读出电路结构,再结合CDS技术,可有效地抑制像素和列FPN,改善图像质量.     

计算机伪信息泄漏技术的研究

简要叙述了计算机的防信息泄漏措施,介绍了伪信息泄漏技术,详细分析了白噪声法、相关噪声法和相关视频信号法。     

占空比优化的1.25GHz CMOS锁相环

半速率高速串行接口同时使用时钟的正/负边沿作为发送数据的定时基准,数据码元的定时长度直接由时钟的占空比决定,因此锁相环的输出时钟的占空比显得尤为重要。本文基于0.13μmCMOS工艺设计实现了一款1.25GHz的高频锁相环。该锁相环基于环形振荡器结构,使用互补相位调节技术实现输出时钟的占空比平衡。流片测试结果表明,该锁相环能够稳定输出1.25GHz的高频时钟,实测输出时钟的占空比能够稳定在49.86%～52.89%的范围内,平均占空比为51.21%。     

Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology

This work concentrate on the design of low power substitution box architecture with enhanced galois field based transform towards multiplier in advanced cryptographic encryption core. Basic components such as AND, XOR, XNOR are being used for the designing process. Initially tree based XNOR gates are picked up and then the AND gates are replaced by NAND gated with less number of transistor in it. Here, logical method is carried out, which is actually considered as better method for re-sizing of transistor. This will further decrease the overall delay and power consumption. The less delay can be obtained by 4-input XOR gate architecture. The implementation results with an 180 nm CMOS standard library show that the proposed AES core can reduce the area and power consumption significantly.     

微机电磁信息泄漏与防护技术

当今型计算机已广泛应用于国防军事领域，正府机要部门等。叙述了耿防止运中电磁信息的射，传导方式泄漏，在印电路板要部门等     

利用防火墙技术处理局域网安全漏洞

因局域网越来越多地遭到黑客的攻击,其安全性成为一个至关重要的问题。本文基于网络体系结构、TCP／IP协议存在安全漏洞、防火墙技术的分析和探讨,指出防火墙技术能处理许多TCP／IP协议的安全漏洞     

Crossing Minimization for Symmetries

We consider the problem of drawing a graph with a given symmetry such that the number of edge crossings is minimal. We show that this problem is NP-hard, even if the order of orbits around the rotation center or along the reflection axis is fixed. We devise an O(m log m) algorithm for computing a crossing minimal drawing if inter-orbit edges may not cross orbits, showing in particular that intra-orbit edges do not contribute to the NP-hardness of the crossing minimization problem for symmetries.     

嵌入式系统中CMOS图像传感器接口技术

提出了CMOS（互补金属氧化物半导体）图像传感器在嵌入式系统中的接口技术，通过设计软件驱动使嵌入式处理器能够控制CMOS图像传感器图像数据自动采集。并对CMOS图像传感器采集的数据进行插值和自动白平衡处理。此接口模块已经成功地应用于二维条码识读器的图像采集模块中，取得了良好的效果。