fmax为107GHz的AlGaN/GaN HFET

UCLA,JPL和Epitronics报道了在半绝缘4H-SiC衬底上生长的非掺杂沟道Al0.30Ga0.70N/GaN HFET,器件没有制作空气桥,获得的fmax达到了107GHz的新记录.该器件包括一个100nm AlN缓冲层、1.25nm的未掺杂GaN、3nm的未掺Al0.30Ga0.70N和n型重掺杂(Si=1×1019cm-3)的30nm的Al0.30Ga0.70N层.栅长为0.2μm,由于在AlGaN层中的Al含量高和n型掺杂重,获得的源漏欧姆接触电阻为0.15Ω*mm.除了优越的频率特性,该器件的跨导为260mS/mm(栅的反向偏置电压为3.5V),饱和电流密度为1.2A/mm.     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.     

用第一性原理研究F掺杂β-Ga2O3的电子结构和光学性质

研究F掺杂浓度对β-Ga2O3的几何结构、电子结构和光学性质的影响。F掺杂β-Ga2O3在富Ga条件下容易制备,随F掺杂浓度的提高,F掺杂β-Ga2O3的稳定性增强,结构参数变大。F掺杂β-Ga2O3是一种n型半导体材料,导带中的占据态由Ga 4s、Ga 4p和O 2p态组成,占据态随F掺杂浓度的增加而增加。随F掺杂浓度的提高,F掺杂β-Ga2O3的禁带宽度收缩,占据态展宽。F掺杂β-Ga2O3的吸收谱呈现陡峭的带边吸收和宽的吸收带。随F掺杂浓度的提高,F掺杂β-Ga2O3的带边吸收蓝移,宽带吸收的强度增强。宽带吸收是由导带中的占据态向空态带内跃迁产生的。     

Ge/SiGe异质结构肖特基源漏MOSFET

制备了氧化铪(HfO2)高k介质栅Si基Ge/SiGe异质结构肖特基源漏场效应晶体管(SB-MOSFET)器件,研究了n型掺杂Si0.16Ge0.84层对器件特性的影响,分析了n型掺杂SiGe层降低器件关态电流的机理。使用UHV CVD沉积系统,采用低温Ge缓冲层技术进行了材料生长,首先在Si衬底上外延Ge缓冲层,随后生长32 nm Si0.16Ge0.84和12 nm Ge,并生长1 nm Si作为钝化层。使用原子力显微镜和X射线衍射对材料形貌和晶体质量进行表征,在源漏区沉积Ni薄膜并退火形成NiGe/Ge肖特基结,制备的p型沟道肖特基源漏MOSFET,其未掺杂Ge/SiGe异质结构MOSFET器件的空穴有效迁移率比相同工艺条件制备的硅器件的高1.5倍,比传统硅器件空穴有效迁移率提高了80%,掺杂器件的空穴有效迁移率与传统硅器件的相当。     

超宽禁带半导体Ga2O3微电子学研究进展

半导体材料Ga2O3是继宽禁带半导体材料SiC/GaN之后新兴的直接带隙超宽禁带氧化物半导体,其禁带宽度为4.5~4.9eV,击穿电场强度高达8MV/cm(是SiC及GaN的2倍以上),物理化学稳定性高,在发展下一代电力电子学和固态微波功率电子学领域具有较大的潜力。自2012年第一只Ga2O3场效应晶体管诞生以来,Ga2O3微电子学的研究呈现快速发展态势。本文综述了β-Ga2O3单晶材料和外延生长技术以及β-Ga2O3二极管和β-Ga2O3场效应管等方面的研究进展,介绍了β-Ga2O3材料和器件的新工艺、新器件结构以及性能测试结果,分析了相关技术难点和创新思路,展望了Ga2O3微电子学未来的发展趋势。     

GaAs基InAlAs/InGaAsMHEMT直流特性研究

报道了用 MBE技术生长的 Ga As基 In Al As/In Ga As改变结构高电子迁移率晶体管 (MHEMT)的制作过程和器件的直流性能。对于栅长为 0 .8μm的器件 ,最大非本征跨导和饱和电流密度分别为 3 5 0 m S/mm和1 90 m A/mm。源漏击穿电压和栅反向击穿电压分别为 4V和 7.5 V。这些直流特性超过了相同的材料和工艺条件下 Ga As基 PHEMT的水平 ,与 In P基 In Al As/In Ga As HEMT的性能相当     

新型双异质结双平面掺杂功率PHEMT

设计并制作了双异质结双平面掺杂的Al0.24Ga0.76As/In0.22Ga0.78As/Al0.24Ga0.76As功率PHEMT器件,采用双选择腐蚀栅槽结构,有效提高了PHEMT器件的输出电流和击穿电压.对于1μm栅长的器件,最大输出电流为500mA/mm,跨导为275mS/mm,阈值电压为-1.4V,最大栅漏反向击穿电压达到了33V.研究结果表明,在栅源间距一定时,栅漏间距对于器件的输出电流、跨导和击穿电压有很大关系,是设计功率PHEMT的关键之一.     

( NH4) 2Sx 溶液改善GaAs MESFETs 击穿特性的机理研究

使用（NH4）2Sx溶液对GaAs MESFETs进行处理。处理后，器件各栅偏压下的源漏饱和电流降低了，栅漏击穿电压有了显著提高。我们认为负电荷表面态影响着栅边缘的电场，负电荷表面态密度的增大会提高器件的击穿电压，这就是（NH4）2Sx溶液处理可改善GaAs MESFET击穿电压的原因。     

新型双异质结双平面掺杂功率PHEMT

设计并制作了双异质结双平面掺杂的Al0 .2 4 Ga0 .76 As/ In0 .2 2 Ga0 .78As/ Al0 .2 4 Ga0 .76 As功率PHEMT器件,采用双选择腐蚀栅槽结构,有效提高了PHEMT器件的输出电流和击穿电压.对于1μm栅长的器件,最大输出电流为5 0 0 m A/ mm ,跨导为2 75 m S/ m m,阈值电压为- 1 .4 V,最大栅漏反向击穿电压达到了33V .研究结果表明,在栅源间距一定时,栅漏间距对于器件的输出电流、跨导和击穿电压有很大关系,是设计功率PHEMT的关键之一.     

High Transconductance MISFET With a Single InAs Nanowire Channel

Metal-insulator field-effect transistors (FETs) are fabricated using a single n-InAs nanowire (NW) with a diameter of d = 50 nm as a channel and a silicon nitride gate dielectric. The gate length and dielectric scaling behavior is experimentally studied by means of dc output- and transfer-characteristics and is modeled using the long-channel MOSFET equations. The device properties are studied for an insulating layer thickness of 20-90 nm, while the gate length is varied from 1 to 5 mum. The InAs NW FETs exhibit an excellent saturation behavior and best breakdown voltage values of V _BR > 3 V. The channel current divided by diameter d of an NW reaches 3 A/mm. A maximum normalized transconductance g_m /d > 2 S/mm at room temperature is routinely measured for devices with a gate length of les 2 mum and a gate dielectric layer thickness of les 30 nm.     

8.5 m/spl Omega/ /spl middot/ cm/sub 2/ 600-V double-epitaxial MOSFETs in 4H-SiC

The most important issue in realizing a 4H-SiC vertical MOSFET is to improve the poor channel mobility at the MOS interface, which is related to high on-resistance. This letter focuses on a novel 4H-SiC vertical MOSFET device structure where a low acceptor concentration epitaxial layer is used as a channel. We call this structure a double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p/sup $/epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 m/spl Omega//spl middot/cm/sup 2/ at a gate voltage of 15 V and a blocking voltage of 600 V. This on-resistance is the lowest so far reported for a vertical MOSFET with a blocking voltage of 600 V.     

Source-field-plated Ga2O3 MOSFET with a breakdown voltage of 550 V

Ga_2O_3 metal–oxide–semiconductor field-effect transistors(MOSFETs) with high-breakdown characteristics were fabricated on a homoepitaxial n-typed β-Ga_2O_3 film, which was grown by metal organic chemical vapor deposition(MOCVD) on an Fedoped semi-insulating(010) Ga_2O_3 substrate. The structure consisted of a 400 nm unintentionally doped(UID) Ga_2O_3 buffer layer and an 80 nm Si-doped channel layer. A high k HfO_2 gate dielectric film formed by atomic layer deposition was employed to reduce the gate leakage. Moreover, a source-connected field plate was introduced to enhance the breakdown characteristics. The drain saturation current density of the fabricated device reached 101 mA/mm at V_gs of 3 V. The off-state current was as low as 7.1 ×10^-11 A/mm, and the drain current I_ON/I_OFF ratio reached 10~9. The transistors exhibited three-terminal off-state breakdown voltages of 450 and 550 V, corresponding to gate-to-drain spacing of 4 and 8 μm, respectively.     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

GaN MOS device using SiO/sub 2/-Ga/sub 2/O/sub 3/ insulator grown by photoelectrochemical oxidation method

We report on a SiO/sub 2/-Ga/sub 2/O/sub 3/ gate insulator stack directly grown on n-type GaN by the photoelectrochemical oxidation method. The resultant MOS devices are fabricated using standard photolithography and liftoff techniques. The effect of annealing temperature on the SiO/sub 2/-Ga/sub 2/O/sub 3//n-type GaN MOS devices is investigated. The properties of high breakdown field, low gate leakage current, and low interface state density are investigated for the MOS devices.     

利用CsN3n型掺杂电子传输层改善OLED器件性能的研究

为了能够有效地提高电子的注入和传输能力,改善有机电致发光器件的性能,本文利用CsN₃作为n型掺杂剂,对有机电子传输材料Bphen进行n型电学掺杂,制备了结构为ITO/MoO₃（2 nm）/NPB（50 nm）/Alq₃（30 nm）/Bphen（15 nm）/Bphen：CsN₃（15 nm,x%,x=10,15,20）/Al（100 nm）的器件。实验结果表明,CsN₃是一种有效的n型掺杂剂,以掺杂层Bphen：CsN₃ 作为电子传输层,可以有效地降低电子的注入势垒,改善器件的电子注入和传输能力,从而降低器件的开启电压,同时提高了器件的亮度和发光效率。在掺杂浓度为10%时器件的性能最优,开启电压仅为2.3 V,在7.2 V的驱动电压下,达到最大亮度29 060 cd/m²,是非掺杂器件的2.5倍以上。当驱动电压为6.6 V时,达到最大电流效率3.27 cd/A。而当掺杂浓度进一步提高时,由于Cs扩散严重,发光区形成淬灭中心,造成器件的效率下降。     

新型基区结构高反压功率晶体管的优化

依据电参数指标要求,针对高压-高增益硅功率晶体管基区结构和终端结构进行优化研究。提出了一种可用于改善集电极-发射极击穿电压(V_(BRCEO))和电流放大倍数(β)矛盾关系的带埋层的新型基区结构,并针对埋层基区结构对高压-高增益硅功率晶体管电性能及可靠性的影响进行了研究。仿真结果表明:新型基区结构不仅可以很好地折中晶体管β与V_(BRCEO)之间的矛盾关系,而且还能在较大的埋层基区宽度、埋层基区掺杂峰值浓度范围内使晶体管获得较低且一致性较好的饱和压降;具有新型基区结构的晶体管在改善正偏的情况下抗二次击穿能力具有明显优势。由仿真得到的器件结构参数,研制出的样片的β,V_(BRCEO)和集电极-基极击穿电压(V_(BRCBO))均满足电参数指标要求。     

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO2

A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm²/V.s and drain breakdown voltage exceeding 15 V.     

A GaAs MOSFET with a liquid phase oxidized gate

Low leakage current density (as low as 10^-8 A/cm² at an applied voltage of 5 V) and high breakdown electrical field (larger than 4.5 MV/cm) of the liquid phase chemical-enhanced oxidized GaAs insulating layer enable application to the GaAs MOSFET. The oxide layer is found to be a composite of Ga₂O₃, As, and As₂O₃. The n-channel depletion mode GaAs MOSFET's are demonstrated and the I-V curves with complete pinch-off and saturation characteristics can be seen. A transconductance larger than 30 mS/mm can be achieved which is even better than that of MESFET's fabricated on the same wafer structure