6.5 kV SiC光控晶闸管的研制

基于Sentaurus TCAD软件,研制了一款6.5 kV SiC光控晶闸管.通过优化雪崩击穿模型,对多层外延材料的规格及渐变终端技术进行研究,有效抑制了芯片表面峰值电场,实现了6.5 kV的耐压设计;此外结合实际应用需求,对器件的开通特性进行了仿真模拟.在4英寸(1英寸=2.54 cm)SiC工艺平台制备了6.5 kV SiC光控晶闸管,并对器件性能进行了测试.测试结果显示,芯片击穿电压超过6.5 kV,在4 kV电源电压以及365 nm波长紫外光触发的条件下,器件导通延迟约为200 ns,脉冲峰值电流约为2.1 kA,最大导通电流变化率(di/dt)达到6.3 kA/μs,测试结果与仿真模拟结果基本一致.     

考虑温度影响的SiC MOSFET动态性能分析与优化

SiC器件的高开关速度使其瞬态过程的非理想特性大为增加,对杂散参数也更为敏感,容易激发高频振荡和过冲.为充分发挥其高开关速度优势,提升系统控制性能,首先,建立SiC MOSFET开关瞬态解析模型,提取了开关过程的关键动态性能参数电流变化率(di/dt)和电压变化率(dv/dt);其次,通过理论分析,明确了di/dt和dv/dt的关键影响因子为驱动电阻、栅源电容、栅漏电容和温度.然后,在Simplorer软件中搭建双脉冲测试电路,定量分析了不同驱动参数和温度对di/dt和dv/dt的影响规律.结果 表明:驱动参数对di/dt和dv/dt具有不同的控制效果,并且di/dt和dv/dt在开通、关断过程分别体现正温度特性和负温度特性.最后,以150℃环境为例,通过减小关断电阻补偿温度影响,实现了在不增大电应力的前提下,关断损耗降低了8.37％.     

一种高di/dt栅控晶闸管的三重扩散工艺优化

传统栅控晶闸管(MCT)的制造工艺中存在阱区浓度调整与器件性能最大化之间的矛盾,提出了一种具有高电流上升率的制造工艺的优化,实现了具有更高正向电流能力与低阈值电压的MCT器件。结果表明该工艺制造的MCT在脉冲放电应用中电流上升率(di/dt)较传统工艺所制造的器件提高15%,最大工作温度降低33%,热逸散速度提高36%。     

低导通压降MOS控制晶闸管的研制

基于6英寸(1英寸≈2.54 cm)半导体工艺平台研制了一款低导通压降的MOS控制晶闸管(MCT)。通过对MCT正向阻断状态和导通状态的理论分析，阐述p基区结构参数影响正向阻断特性和导通特性的机理。采用Silvaco TCAD软件建立静态特性模型并进行p基区结构参数仿真设计，得到最优掺杂浓度和厚度。结合仿真结果指导工艺参数优化制备MCT芯片，并对封装后器件性能进行了测试。测试结果表明，优化后器件正向阻断电压超过1 600 V,脉冲峰值阳极电流为3 640 A,导通压降在满足2.0 V设计值的基础上降低至1.7 V,正向阻断特性和导通特性均得到提高。     

新型亚纳秒高功率半导体开关器件

介绍了一种基于半导体内部的等离子体波理论而设计制造的全固态高功率半导体开关器件--快速离化器件(FID),阐述了FID器件的工作机理.采用传统的电力电子器件的制造工艺技术,研制出了新型亚纳秒快速离化器件.FID器件采用无感裸芯片封装技术,寄生参数小.单个FID器件工作电压＞2 kV,导通时间＜1 ns,工作电流高迭10 kA,抖动＜20 ps,di/dt超过100 kA/μs,重复频率400 kHz.具有极易串并联、导通触发脉冲可同步产生、工作特性高度稳定、体积小、重量轻等优点,FID可与DSRD组合应用,当采用MARX电路连接时,可以获得几十千伏以上的高压快速脉冲.FID器件脉冲发生器具有广阔的应用前景.     

基于VLD技术的MCT器件仿真分析

针对在脉冲功率领域有一定应用的栅控晶闸管(MCT)器件,提出了一种基于VLD(横向变掺杂)技术的MCT(VMCT)器件新工艺并通过仿真比较出新工艺的优势。VLD技术是指通过调整掩模版窗口的大小调节杂质掺杂浓度,进而优化MCT中NPN晶体管的电流放大系数a,通过仿真确定了新工艺的杂质注入剂量。仿真结果表明采用新工艺的VMCT器件比采用常规工艺MCT(CMCT)电流能力更强,是CMCT的2倍;和CMCT相比,VMCT器件的耐压和关断电压都保持不变,但是VMCT在工艺流程中比MCT节省一张掩模版。     

用于IGCT的具有很高SOA能力的大面积快恢复二极管

为IGCT的应用而开发的大面积(>50cm2)4.5kV快恢复硅二极管具有很低的漏电流以及直至140℃的高安全工作区SOA。为了获得软的反向恢复特性和在2.8kV下100FIT的抗宇宙射线辐射能力,对硅器件的设计及少子寿命控制进行了优化。此外,用离子辐照在阳极缓冲层反向偏置空间电荷区RBSOA中造成的缺陷峰值与电子辐照相结合的方法,可以塑造通态等离子体的形状、减小反向恢复损耗。除了低的漏电流之外,新设计还提供了非常坚固的阳极,在反向恢复期间没有di/dt扼流线圈的情况下,阳极能够承受高达10kA/μs的di/dt。本文还给出了低能电子辐照与高能电子辐照二极管一些主要参数的比较,这些参数有漏电流、正向压降的温度系数、正向压降V_F与反向恢复损耗E_(rec)的关系曲线、反向恢复软度以及浪涌电流等。     

6.5 kV SiC MOSFET的优化及开关特性

优化设计了电力系统用6.5 kV SiC MOSFET,测得该器件的导通电流为25 A,阻断电压为6 800 V,器件的巴利加优值(BFOM)达到925 MW/cm²。基于感性负载测试电路测试了器件的高压开关瞬态波形。在此基础上,借助仿真软件构建6.5 kV SiC MOSFET芯片级和器件级仿真模型,通过改变器件元胞结构、阱区掺杂浓度、栅极电阻、寄生电感等参数,研究了6.5 kV SiC MOSFET开关瞬态过程和电学振荡影响因素。结果表明,减小结型场效应晶体管(JFET)宽度有利于提高器件dV/dt能力,而源极寄生电感和栅极电阻是引起栅极电压振荡的重要因素。研究结果有助于分析研究6.5 kV SiC MOSFET在智能电网应用中的开关特性,使得基于SiC MOSFET的功率变换器系统具有更低的损耗、更高的频率和更高的可靠性。     

ESD作用下晶闸管dV/dt触发导通规律研究

针对电磁脉冲作用下晶闸管（silicon controlled rectifier,SCR）意外导通事故频发的问题,选择静电放电（electrostatic discharge,ESD）作为典型电磁脉冲源,对比分析了小电流SCR的ESD敏感度特性,确定了ESD作用下SCR的失效模式为门极电压作用失效、阴阳极断路.采用理论和试验相结合的方法得出了SCR意外导通的开启时间仅与阳极电压和器件本身特性有关的结论,并进一步通过方波电磁脉冲注入的对比试验,揭示了ESD作用下SCR因dV/dt触发导通的开启时间只与ESD注入电压有关:注入电压越高,开启时间越短.     

RSD关断时间检测方法的改进研究

在脉冲功率的重频应用中,开关的关断特性是至关重要的,其关断时间直接决定了可以获得的最高重复频率。文中通过软件仿真分析了影响反向开关晶体管RSD(reversely switched dynistor)关断时间的因素,同时为了更准确地测得RSD的关断时间,在对其关断时间检测电路原理研究的基础上,提出了一种采用IGBT代替晶闸管(Thyristor)作为预充回路开关的改进测量方法。仿真结果表明RSD的关断时间随着器件少子寿命、主电流下降率dI/dt和工作电压的增大而增大。实验测得了正向阻断电压为2 000 V的RSD在IGBT开通时间分别为20μs、40μs和50μs下的电压电流波形及关断时间。     

Experimental and numerical study of the emitter turn-off thyristor(ETO)

The emitter turn-off thyristor (ETO) is a new family of high power semiconductor devices that is suitable for megawatt power electronics application. ETOs with voltage and current ratings of 4-6 kV and 1-4 kA, have been developed and demonstrated. And those power levels are the highest in silicon power devices and are comparable to those of the gate turn-off thyristor (GTO). Compared to the conventional GTO, the ETO has much shorter storage time, voltage controlled turn-off capability, and much larger reverse biased safe operation area (RBSOA). Furthermore, ETOs have a forward-biased safe operation area (FBSOA) that enables it to control the turn-on di/dt similar to an insulated gate bipolar transistor (IGBT). These combined advantages make the ETO based power system simpler in terms of dv/dt snubber, di/dt snubber, overcurrent protection, resulting in significant savings in the system cost. This paper presents experimental and numerical results that demonstrate the advantages of the ETO     

High-energy pulse-switching characteristics of thyristors

Experiments were conducted to study the high energy, high di/dt pulse-switching characteristics of silicon controlled rectifiers (SCRs) with and without the amplifying gate. High di/dt, high-energy single-shot experiments were first done. Devices without the amplifying gate performed much better than the devices with the amplifying gate. A physical model is presented to describe the role of the amplifying gate in the turn-on process, thereby explaining the differences in the switching characteristics. The turn-on area for the failure of the devices was theoretically estimated and correlated with observations. This allowed calculation of the current density required for failure. Since the failure of these devices under high di/dt conditions was thermal in nature, a simulation using a finite-element method was performed to estimate the temperature rise in the devices. The results from this simulation showed that the temperature rise was significantly higher in the devices with the amplifying gate than in the devices without the amplifying gate. From these results, the safe operating frequencies for all the devices under high di/dt conditions was estimated. These estimates were confirmed by experimentally stressing the devices under high di/dt repetitive operation     

Power Converter EMI Analysis Including IGBT Nonlinear Switching Transient Model

It is well known that very high dv/dt and di/dt during the switching instant is the major high-frequency electromagnetic interference (EMI) source. This paper proposes an improved and simplified EMI-modeling method considering the insulated gate bipolar transistor switching-behavior model. The device turn-on and turn-off dynamics are investigated by dividing the nonlinear transition by several stages. The real device switching voltage and current are approximated by piecewise linear lines and expressed using multiple dv/dt and di/dt superposition. The derived EMI spectra suggest that the high-frequency noise is modeled with an acceptable accuracy. The proposed methodology is verified by experimental results using a dc-dc buck converter     

Switching dynamics of IGBTs in soft-switching converters

Next generation of power semiconductor devices will be designed and optimized to meet the specific application requirements. Mixed-mode simulations are used to study the carrier dynamics in punch-through and nonpunch-through Insulated Gate Bipolar Transistor (IGBT) structures during soft- and hard-switching conditions. The simulation results are shown to qualitatively predict the measured bump in the tail current with varying output dv/dt conditions and excessive forward conduction voltage under varying di/dt conditions. A new physical effect termed “conductivity modulation lag” is shown to occur during turn-on under soft-switching conditions. This mechanism is caused by the fact that minority carrier injection into the base of the bipolar transistor significantly lags behind the rate at which drift region conductivity can be modulated. The proposed phenomenon leads to an inductive effect that results in dynamic voltage saturation during turn-on and causes excessive forward voltage drop     

MOS-gated thyristors (MCTs) for repetitive high power switching

Certain applications for pulse power require narrow, high current pulses for their implementation. This work was performed to determine if MOS controlled thyristors (MCTs) could be used for these applications. The MCTs were tested as discharge switches in a low inductance circuit delivering 1 μs pulses at currents between roughly 3 kA and 11 kA, single shot and repetitively at 1, 10, and 50 Hz. Although up to 9000 switching events could be obtained, all the devices failed at some combination of current and repetition rate. Failure was attributed to temperature increases caused by average power dissipated in the thyristor during the switching sequence. A simulation was performed to confirm that the temperature rise was sufficient to account for failure. Considerable heat sinking, and perhaps a better thermal package, would be required before the MCT could be considered for pulse power applications     

Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors

As the characteristics of insulated gate transistors [like metal-oxide-semiconductor field-effect transistors and insulated gate bipolar transistors (IGBTs)] have been constantly improving, their utilization in power converters operating at higher and higher frequencies has become more common. However, this, in turn, leads to fast current and voltage transitions that generate large amounts of electromagnetic interferences over wide frequency ranges. In this paper, a new active gate voltage control (AGVC) method is presented. It allows us to control the values of di/dt at turn-on and dv/dt at turn-off for insulated gate power transistors, by acting directly on the input gate voltage shape. In an elementary switching cell, it enables us to strongly reduce over-current generated by the reverse recovery of the free-wheeling diode at turn-on, and oscillations of the output voltage across the transistor at turn-off. In the following sections, the AGVC in open and closed-loop for IGBT is presented, and its performance is compared with that of a more conventional method, i.e., increasing the gate resistance. Robustness of the AGVC is estimated under variations of dc-voltage supply and transistor switched current.     

Multiple Slope Switching Waveform Approximation to Improve Conducted EMI Spectral Analysis of Power Converters

An improved and simplified electromagnetic interference (EMI) modeling method based on multiple slope approximation of device-switching transitions for EMI analysis of power converters is presented. The traditional noise source modeling method, which uses single slope for rise and fall transition, is studied, and the criteria for reasonable modeling in the frequency range is analyzed. The turn-on and turn-off dynamics are investigated by dividing the nonlinear transitions into several stages based on an insulated gate bipolar transistor (IGBT) behavior circuit model. Real device-switching voltage and current waveforms are approximated by piece-wise linear lines and modeled by multiple dv/dt and di/dt slopes. The predicted EMI spectra suggest that high-frequency EMI noise is modeled with an acceptable accuracy. The proposed method was verified experimentally for a dc-dc buck converter     

Controlled turn-on thyristors

In a one or more amplified stage thyristor design it is possible to control the peak current level of all but the final stage with impedance built into the p-base zone. This impedance reduces both the current and the duty cycle of the protected amplifying stage effectively protecting it from undesirable temperature rises during turn-on. A further bonus and perhaps equally important is the fact that the amplifying stage and its current control impedance can be used to reduce and essentially fix the voltage level at which the following stage turns on. This results in a lower voltage, lower stress turn-on of the following stage, and a device essentially protected from di/dt turn-on failure. This paper describes several aspects of controlled turn-on in the context of a 2.6- and 6-kV light triggered thyristor. In particular we discuss selection of the resistor value, the problem of unwanted current control resistor modulation by device current as well as some factors affecting the proper wattage of such resistors. We also discuss the role current control resistors can play in controlling avalanche current from known locations on the device.     

A Novel Method of Active Power Noise Cancellation in I/O Buffers

This paper presents a scheme to reduce the on-die voltage noise that occurs due a buffer switching event. Both output and input buffer switch events are addressed. A generic power delivery network (PDN) model with parasitic inductance is assumed. A change in current ( ${rm di}/{rm dt}$) across the inductor is considered the primary cause of the voltage noise. On-die decoupling capacitance is traditionally added to the power delivery network to address this problem and to limit the droop. The method described in the paper shows a principally different approach. The maximum ${rm di}/{rm dt}$ is managed to reduce the voltage noise. It is proposed to send to a buffer a current waveform from an external supply or to recycle charge from a locally charged capacitance when the ${rm di}/{rm dt}$ occurs, thus substantially reducing the on-die voltage noise. Alternatively, at a given acceptable level of voltage noise the on-die capacitance can be reduced, providing significantly lower product cost. This paper provides theoretical and modeling background of the proposed schemes and includes simulation results on several performance characteristics.      

Low-loss high-speed switching devices, 2300-V 150-A static induction thyristor

Focussing attention to the performance of high-speed high off-state voltage and large current provided in the buried-gate-type static induction (SI) thyristor, a 2300-V 150-A low-voltage-drop high-speed medium-power SI thyristor was developed. Irrespective of the magnitude of switching current, the SI thyristor has the characteristics of fast turn-on time and less on-gate current compared to that of the GTO thyristor. The characteristics of this SI thyristor obtained as the result of manufacturing this prototype were such that the forward blocking voltage was 2300 V at a gate reverse voltage of -5 V, the reverse blocking voltage was 2350 V, and the forward voltage drop was 1.4 V at an anode current of 150 A and 2.2 V at an anode current of 450 A. The switching characteristics were such that the turn-on time was 1.5 µs when an anode current IAof 150 A becomes ON, turnoff time was 2.5 µs at IA= 100 A and 3.6 µs at IA= 200 A. This SI thyristor is able to break the anode current of 1000 A at a gate current of 95 A. Performance exceeding 1100 A/µs was confirmed for the di/dt capability and even for dv/dt, and these normally can be operatable even at 100 times higher current compared with maximum average current.