A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.     

Large Coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFETs formed by slight oxidation process

We propose a new fabrication technique of room-temperature operating silicon single-electron transistors (SETs). The devices are in the form of ultranarrow wire channel MOSFETs, where a sub-10-nm channel is formed by wet etching and slight thermal oxidation. Large Coulomb blockade (CB) oscillations whose peak-to-valley current ratio at room temperature is as high as 6.8 are observed in the fabricated ultranarrow wire channel MOSFETs. It is found that larger CB oscillations are obtained in the ultranarrow wire channel SETs than in the point-contact channel SETs. It is considered that the potential fluctuations induced during the channel formation processes give rise to multiple-dot SET structures in the ultranarrow wire channel MOSFETs.     

Realization of multiple valued logic and memory by hybrid SETMOS architecture

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.     

Advances in the modeling of single electron transistors for the design of integrated circuit

Single electron transistor (SET) has become a promising candidate for the key device of logic circuit in the near future. The advances of recent 5 years in the modeling of SETs are reviewed for the simulation of SET/hybrid CMOS-SET integrated circuit. Three dominating SET models, Monte Carlo model, master equation model and macro model, are analyzed, tested and compared on their principles, characteristics, applicability and development trend. The Monte Carlo model is suitable for SET structure research and simulation of small scale SET circuit, while the analytical model based on combination with master equation and macro model is suitable to simulate the SET circuit at balanceable efficiency and accuracy.     

Single-electron transistors based on gate-induced Si island for single-electron logic application

The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induced tunnel junctions, and controls the phase of the Coulomb oscillation. The capacitance between the sidewall gate and the Si island extracted from the Coulomb oscillation phase shift of the SETs with sidewall depletion gates on a silicon-on-insulator nanowire was independent of the Si island size, which is consistent with the device structure. The Coulomb oscillation phase shift of the fabricated SETs has the potential for a complementary operation. As a possible application to single-electron logic, the complementary single-electron inverter and binary decision diagram operation on the basis of the Coulomb oscillation phase shift and the tunable tunnel junctions were demonstrated.     

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than /spl omega/W; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.     

Design of a Robust Analog-to-Digital Converter Based on Complementary SET/CMOS Hybrid Amplifier

As a solution to the high speed, ultralow power, and extremely compact ADC circuit block, a complementary single-electron transistor (SET)/CMOS hybrid amplifier-based analog-to-digital converter (ADC) is proposed. It is implemented with a physics-based SPICE model including nonideal effects in real Si-based SET_s such as the tunnel barrier lowering effect, parasitic MOSFET_s operation, and the phase shift of Coulomb oscillation by the bias of a gate other than a main control gate. Its core scheme is the combination of both the amplification of SET current by MOSFET_s and the suppression of a Coulomb blockade oscillation valley current by the differential amplification. In addition, the transient operation of SET/CMOS hybrid circuit-based ADC_s fully accounting for nonideal effects of real SET_s is successfully demonstrated for the first time. Compared with the previous SET-based ADC_s, our ADC makes features of the immunity to nonideal effects, large voltage swing of the output signal, and high load drivability.     

High yield assembly and electron transport investigation of semiconducting-rich local-gated single-walled carbon nanotube field effect transistors

We report the fabrication and electron transport investigation of individual local-gated single-walled carbon nanotube field effect transistors (SWNT-FET) with high yield using a semiconducting-rich carbon nanotube solution. The individual semiconducting nanotubes were assembled at the selected position of the circuit via dielectrophoresis. Detailed electron transport investigations on 70 devices show that 99% display good FET behavior, with an average threshold voltage of 1 V, subthreshold swing as low as 140 mV/dec, and on/off current ratio as high as 8 × 10(5). The high yield directed assembly of local-gated SWNT-FET will facilitate large scale fabrication of CMOS (complementary metal-oxide-semiconductor) compatible nanoelectronic devices.     

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “ quantization threshold”) that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studied for the current-biased negative differential resistance (NDR) circuit and hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.      

Fabrication and characterization of Si quantum dots and SiO(2) tunnel barriers grown by a controlled oxidation process

The control of the growth of silicon dioxide (SiO(2)) and the formation of quantum dots (QDs) play an important role in the fabrication of single-electron transistors (SETs). In this work, SET?structures were fabricated using a systematic oxidation technique known as the pattern-dependent oxidation (PADOX) process. For comparison, two oxidation processes using conventional furnace and rapid thermal processing (RTP) were used. The oxidation temperature for both oxidation processes was set at 1000?°C and the oxygen flow rate in the furnace was set at 1?l?min(-1). The nanostructures were characterized using AFM, SEM and TEM to determine the quality and the stoichiometry of the Si QDs and the oxides. The oxidation rate using a furnace is 0.36?nm?s(-1), significantly lower than the RTP value which is 2.16?nm?s(-1). Meanwhile, the oxygen contents in SiO(2) grown by furnace and RTP are approximately the?same.     

A molybdenum disulfide/carbon nanotube heterogeneous complementary inverter

We report a simple, bottom-up/top-down approach for integrating drastically different nanoscale building blocks to form a heterogeneous complementary inverter circuit based on layered molybdenum disulfide and carbon nanotube (CNT) bundles. The fabricated CNT/MoS(2) inverter is composed of n-type molybdenum disulfide (MOS(2)) and p-type CNT transistors, with a high voltage gain of 1.3. The CNT channels are fabricated using directed assembly while the layered molybdenum disulfide channels are fabricated by mechanical exfoliation. This bottom-up fabrication approach for integrating various nanoscale elements with unique characteristics provides an alternative cost-effective methodology to complementary metal-oxide-semiconductors, laying the foundation for the realization of high performance logic circuits.     

Compact analytical model for room-temperature-operating silicon single-electron transistors with discrete quantum energy levels

A compact and analytical model for silicon single-electron transistors (SETs) considering the discrete quantum energy levels and the parabolic tunneling barriers is proposed. The model is based on a steady-state master equation that considers only the three most probable states derived from ground level and the first excited level for each number of electrons in the dot to reduce the complexity while accounting for the quantum-level spacing and multiple peaks in Coulomb oscillation. Negative differential conductance (NDC) characteristics and aperiodic Coulomb oscillations due to nonuniform quantum-level spacings can be reproduced in this model. The model was compared with measurements, and good agreement was obtained. Simulations of some basic circuits that utilize NDC are successfully carried out by applying our model to the HSPICE circuit simulation. Our model can provide suitable environments for designing CMOS-combined room-temperature-operating highly functional SET circuits.     

Few electron limit of n-type metal oxide semiconductor single electron transistors

We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm(2) is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.     

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.     

Design of a single-chip pH sensor using a conventional 0.6-/spl mu/m CMOS process

A pH sensor fabricated on a single chip by an unmodified, commercial 0.6-/spl mu/m CMOS process is presented. The sensor comprises a circuit for making differential measurements between an ion-sensitive field-effect transistor (ISFET) and a reference FET (REFET). The ISFET has a floating-gate structure and uses the silicon nitride passivation layer as a pH-sensitive insulator. As fabricated, it has a large threshold voltage that is postulated to be caused by a trapped charge on the floating gate. Ultraviolet radiation and bulk-substrate biasing is used to permanently modify the threshold voltage so that the ISFET can be used in a battery-operated circuit. A novel post-processing method using a single layer of photoresist is used to define the sensing areas and to provide robust encapsulation for the chip. The complete circuit, operating from a single 3-V supply, provides an output voltage proportional to pH and can be powered down when not required.     

Novel Hybrid Voltage Controlled Ring Oscillators Using Single Electron and MOS Transistors

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits     

Properties of evaporated titanium thin films and their possible application in single electron devices

The influence of the deposition rate of titanium thin films on their microscopic structure has been investigated by transmission electron microscopy, X-ray diffraction analyses and atomic force microscopy. Furthermore, the resistivity of the films has been characterized by van der Pauw measurements in a temperature range of 5-300 K. Titanium films with a thickness of 10 nm evaporated with a rate of 1 Å/s showed the typical and well known temperature dependency of the resistivity (i.e. decreasing resistivity with falling temperature). In contrast, the resistivity of thin films deposited with a rate of 0.2 Å/s rises with decreasing temperature. Additionally, the resistivity of the films evaporated with the lower rate rises significantly when reducing their film thickness down to 3 nm. Due to this increase of the resistivity we are able to present an alternative and relatively simple approach for the fabrication of single electron transistors (SETs). The presented SET design is based on the evaporated thin titanium films with a deposition rate of 0.2 Å/s onto well defined trenches previously etched into a dielectric layer of thermally grown silicon dioxide. The tunnel junctions originate from a local increase of the resistance of the metallic wire at the edges of the trenches. The devices fabricated in this manner with lateral dimensions in the 50-100 nm range show clear SET features at an operating temperature of up to 77 K. Additionally, the influence of background charges on the Coulomb oscillations in this devices are demonstrated and discussed in comparison with simulated data.     

Single electron transistor fabricated with SOI wafer

The single electron transistor (SET) is the most sensitive device for measuring the charge of electron. It has been proposed by Kane that the SET can be used for readout of calculated results in Si-based quantum computer. We fabricated the SET with SOI substrate utilizing the suspended mask of SiO₂ and Si for the purpose of using it for readout of calculation in Si-Based quantum computer. By using only the above materials for the mask, high temperature processes including ion implantation and activation annealing could be possible and it was never achieved in conventional methods with the suspended mask with photoresist. First, the suspended mask with enough undercut in SOI was made by removing the box oxide of SOI wafer combining with pattern delineation by electron beam lithography, anisotropically reactive ion etching and isotropic wet etching. After forming the suspended mask, Al films were evaporated from two different angles to make an overlap just below the bridge, resulting in completing the SET in the undercut region possible to measure the electron spin. After making the Al/Al₂O₃/Al SET, we measured the I–V characteristic between source and drain at 1.8 K. The Coulomb blockade and the Coulomb oscillation were observed.     

Silicon single electron transistors with SOI and MOSFET structures: the role of access resistances

Coulomb blockade has been widely reported in silicon and metallic structures without intentional tunnel barriers. In particular, a simple constriction in silicon-on-insulator (SOI) allows to build a three-terminal silicon single-electron transistor (SET) operating at moderate temperature. The key parameters are the access resistances confining the electrons and the size of the gate-channel overlap, which sets the Coulomb energy. Thin films of doped silicon with sheet resistance of a few tens of h/e/sup 2/ are well suited for fabricating optimized access resistances. Low doped extensions with typical resistivity 1000 /spl Omega//spl mu/m (at 300 K) are also good candidates. We illustrate this MOS-SET principle in SOI constriction and standard MOSFET of similar size. Although relying on different concepts, the ultimate MOSFET and MOS-SET are shown to be technologically close, differing mostly by the ratio between the channel resistance over the access resistance. Because this ratio is decreasing as the gate length shrinks, single electron effects should become more and more important at high temperature in the subthreshold regime of standard field effect transistor devices.