一种高压功率器件场板技术的改进与设计

为了解决功率器件高击穿电压与减小表面最大电场需求之间的矛盾,提出了一种高压功率器件终端场板改进方法。通过调节金属场板和多晶硅场板的长度,使金属场板覆盖住多晶硅场板,最终使得两者的场强相互削弱,从而减小表面最大电场。采用TCAD(ISE)软件对该结构进行仿真验证,结果表明该结构能够在保证高耐压的前提下减小表面最大电场。基于所提方法,设计出了一种七个场限环的VDMOSFET终端结构,其耐压达到了893.4 V,表面最大电场强度只有2.16×10⁵ V/cm,提高了终端的可靠性。     

一款600V VDMOS终端结构的设计

设计了一款600V VDMOS功率器件的终端保护环结构,采用场限环与复合场板相结合的方式降低硅表面的电场峰值,且表面电场分布均匀.在159μm终端长度上仿真实现了670V的耐压,表面电场最大值为2.36e5V*cm-1,提高了终端的可靠性;工艺简单,同时没有增加额外的掩膜与步骤.     

一款800V VDMOS终端结构的设计

设计了一款800 V VDMOS终端结构,采用场限环(FLR)与场板(FP)相结合的方式,在场限环上添加多晶硅场板与金属场板,有效地降低了表面电场峰值。通过调整终端结构,在135μm的有效终端长度上实现了848 V的击穿电压,最大表面电场为2.34×105 V/cm,小于工业界判断器件击穿场强标准(2.5×105 V/cm),且电场分布比较均匀,终端结构的稳定性和可靠性高。     

4H-SiC台阶型沟槽MOSFET器件

介绍了一种4H-SiC台阶型沟槽MOSFET器件.该结构引入了台阶状沟槽,使用TCAD软件对台阶状沟槽的数量、深度、宽度等参数进行了拉偏仿真,确定了最优台阶结构参数.仿真结果表明,与传统的UMOS器件相比,最优台阶结构参数下的台阶状沟槽MOSFET器件关断状态下的栅氧化层尖峰电场减小了12％,FOM值提升了5.1％.提...     

IGBT多级场板终端结构的仿真和验证

基于现有工艺平台设计一个多级场板终端结构:在有源区最外围元胞和场板之间加一个P-Ring环,可以降低第一级场板边缘下的电场强度;改变第四级场板氧化层厚度,可以调整IGBT击穿电压值;在工艺过程中在淀积第四台阶氧化层之前先淀积一薄层SiOxNy薄膜作为腐蚀阻挡层,可降低对工艺精度的要求,同时提高器件可靠性;多级场板终端结构可以阻止器件表面电荷进入硅表面改变硅表面电势,提高器件的稳定性和可靠性。将此终端用在1 200V NPT Planer IGBT结构上进行流片验证,击穿电压可达1 300V以上。     

漂移区覆盖高k薄膜的高压LDMOS器件优化设计

为了获得高耐压、低导通电阻的横向双扩散MOSFET(LDMOS)器件,综合利用高介电常数(高k)薄膜技术和场板技术,设计出一种漂移区表面采用"高k薄膜+氧化层+场板"结构的功率器件,有效降低了PN结弯角高电场和场板边缘峰值电场。使用器件仿真工具MEDICI进行验证,并分析高k薄膜厚度、氧化层厚度、高k薄膜相对介电常数以及栅场板长度对器件性能的影响,最终实现了耐压达到820V、比导通电阻降至13.24Ω.mm2且性能稳定的LDMOS器件。     

AlGaN/GaN HEMT中电场分布的ATLAS模拟

用Silvaco的ATLAS软件模拟了栅场板参数对AlGaN/GaN HEMT中电场分布的影响.模拟结果表明,场板的加入改变了器件中电势的分布情况,降低了栅边缘处的电场峰值,改善了器件的击穿特性;场板长度(LFP,length of field plate)、场板与势垒层间的介质层厚度t等对电场的分布影响很大.随着LFP的增大、t的减小,栅边缘处的电场峰值Epeak1明显下降,对提高器件的耐压非常有利.通过对相同器件结构处于不同漏压下的情况进行模拟,发现当器件处于高压下时,场板的分压作用更加明显,说明场板结构更适合于制备用作电力开关器件的高击穿电压AlGaN/GaN HEMT.     

硅基双极低噪声放大器的能量注入损伤与机理

针对Si基双极型低噪声放大器(LNA),用脉冲调制150MHz射频信号在其输入端进行了能量注入实验,研究结果表明Si基LNA的噪声系数和增益特性都是注入能量的敏感参数. 样品解剖和电路仿真显示能量作用使LNA内部晶体管出现基极/发射极金属化损伤,基极金-半接触电阻增大导致了LNA噪声系数增大,而Si基双极器件hFE随时间正向漂移损伤模式使LNA增益随注入能量的增加而增大. 研究表明,由于能量作用下损伤效应的复杂性,以往可靠性研究中单纯采用增益的变化来衡量器件与电路的损伤效应的方法是不全面的.     

单区JTE加场板终端结构的优化设计

为了提高芯片面积利用率,采用单区结终端扩展(JTE)与复合场板技术设计了一款700 V VDMOS的终端结构。借助Sentaurus TCAD仿真软件,研究单区JTE注入剂量、JTE窗口长度和金属场板长度与击穿电压的关系,优化结构参数,改善表面和体内电场分布,提高器件的耐压。最终在120.4mm的有效终端长度上实现了838 V的击穿电压,表面最大电场为2.03×10~5 V/cm,小于工业界判断器件击穿的表面最大电场值(2.5×10~5 V/cm),受界面态电荷的影响小,具有较高的可靠性,且与高压深阱VDMOS工艺兼容,没有增加额外的掩膜和工艺步骤。     

一款700 V VDMOSFET结终端结构设计

为了提高功率器件结终端击穿电压,节约芯片面积,设计了一款700 V VDMOSFET结终端结构。在不增加额外工艺步骤和掩膜的前提下,该结构采用场限环-场板联合结终端技术,通过调整结终端场限环和场板的结构参数,在151μm的有效终端长度上达到了772 V的击穿电压,表面电场分布相对均匀且最大表面场强为2.27×105V/cm,小于工业界判断器件击穿场强标准(2.5×105 V/cm)。在保证相同的击穿电压下,比其他文献中同类结终端结构节约面积26%,实现了耐压和可靠性的要求,提高了结终端面积的利用效率。     

A new approach for characterizing structure-dependent hot-carriereffects in drain-engineered MOSFET's

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N_it ) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N_it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N_it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices     

Breakdown voltage improvement for thin-film SOI power MOSFET's by aburied oxide step structure

Numerical simulations are performed to demonstrate that a new SOI power MOSFET structure, namely buried oxide step structure (BOSS), introduces a high electric field peak near the buried oxide step and that this peak reduces the height of the other electric field peaks within thin silicon layer. The relaxation of these peaks results in higher breakdown voltages at much higher impurity concentrations than those in the conventional structure     

Maximum surface and bulk electric fields at breakdown for planar and beveled devices

Techniques previously presented for predicting breakdown voltage on planar devices with and without a field ring and in negative beveled devices are greatly extended so that the peak bulk and surface electric fields at breakdown can now be predicted. In addition, new techniques are described which for the first time allow the peak bulk and surface electric fields to be predicted for all positive and double positive beveled devices. Using this paper it becomes possible to predict peak bulk and surface electric fields as well as breakdown voltage for all planar and beveled devices. This is accomplished by the use or normalization procedures which allow dependencies on the substrate doping, junction depth, surface concentration, junction curvature, and bevel angle to be reduced to a single dependence. It is shown that the positive bevel is most effective in reducing surface electric fields with the negative bevel, double positive bevel, and the field ring for planar devices in decreasing order of effectiveness.     

平面结场板结构表面场分布的二维解析

提出了基于二维泊松方程解的平面结场板结构的二维表面电场解析物理模型 .在该模型基础上 ,分析了衬底掺杂浓度、场板厚度和长度对二维表面场分布的影响 .解析预言的场分布与击穿电压的计算结果与先前的数值分析基本符合 .该模型为场板结构的优化设计提供了理论基础     

Critical factors influencing the voltage robustness of AlGaN/GaN HEMTs

The influence of the electric field on the reliability of AlGaN/GaN HEMTs is investigated in this work. We first demonstrate that at a certain electric field strength at the gate edge the gate characteristics of the device changes. This degradation is irreversible and is strongly influenced by growth parameter. A drain-voltage step-stress method is applied to the devices for investigating different layouts, and a consequent application enabled us to assign parameters mitigating the peak field strength and improve reliability.     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

High-voltage planar devices using field plate and semi-resistivelayers

An improved high-voltage technique based on the use of a field plate combined with semiresistive layers (SIPOS) on oxide is proposed. The field plate and SIPOS (semi-insulating polycrystalline silicon) are shown to have complementary functions. Junction curvature electric field effects are reduced by the presence of the field plate. The silicon surface potential is linearized by a primary SIPOS layer on oxide, thereby reducing the peak electric field at the edge of the field plate. A second high-resistivity SIPOS layer provides an excellent passivation, and also prevents the dielectric breakdown of the underlayer SIPOS film. Moreover, the savings in chip area is about 20% compared to the standard mesa termination. The global yield is 94% for the SIPOS planar transistors and 86% for equivalent devices in mesa technology. The complete fabrication, design, electrical characteristics, and reliability of high-voltage planar transistors are described     

SOI谐振式微型电场传感器的新型制作工艺研究

This paper presents a new fabrication process for the SOI-based novel miniature electric field sensor. This new process uses polyimide film to release the SiO₂ layer.Compared with the CO₂ critical point release method,it significantly improves the device surface cleanliness and shortens the process flow.The impurity on the base layer is analyzed.The problem of peak and butterfly-type contamination occurring on the base layer of the SOI wafer during the DRIE process is discussed and solved by thickening the photoresist layer and coating with polyimide film twice.This new process could fabricate MEMS sensors and actuators such as SOI-based electric field sensors,gyroscopes,and micro mirrors and can be an alternative fabrication process compared to commercial SOIMUMPS fabrication processes.