Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.     

p-channel germanium MOSFETs with high channel mobility

The fabrication and performance of p-channel germanium MOSFETs having a nitrided native oxide gate insulator are reported. A self-aligned dummy-gate process suitable for circuit integration is utilized. Common-source characteristics exhibit no looping and indicate a peak room-temperature channel mobility of 770 cm²/V-s. These results provide further evidence that a high-performance germanium CMOS technology is possible     

High-power InP MISFETs

InP MISFETs with SiO2 as the gate insulator and a deep channel recess have been fabricated. At 9 GHz the highest power output with 4 dB gain was 3.5 W/mm gate width with 33% power added efficiency. This power is more than twice that of the best GaAs MESFET.     

RF performance of diamond MISFETs

A cutoff frequency (f_T) of 11 GHz is realized in the hydrogen-terminated surface channel diamond metal-insulator-semiconductor field-effect transistor (MISFET) with 0.7 μm gate length. This value is five times higher than that of 2 μm gate metal-semiconductor (MES) FETs and the maximum value in diamond FETs at present. Utilizing CaF₂ as an insulator in the MIS structure, the gate-source capacitance is reduced to half that of the diamond MESFET because of the gate insulator capacitance being in series to the surface-channel capacitance. This FET also exhibits the highest f _max of 18 GHz and 15 dB of power gain at 2 GHz. The high-frequency equivalent circuits of diamond MISFET are deduced from the S-parameters obtained from RF measurement     

High-performance WN-gate MISFETs fabricated from MOVPE wafers

WN-gate heterojunction MISFETs with an AlGaAs layer as insulator have been fabricated on MOVPE wafers; they exhibit high transconductance (up to 460 mS/mm) and high Vt uniformity.     

Single-interface and quantum-well heterostructure MISFETs

The physical operation of heterostructure metal-insulator-semiconductor field-effect transistors (H-MISFETs) is described and compared with that of more familiar heterostructure FETs. Undoped, doped-channel, and quantum-well MISFETs based on AlGaAs-GaAs heterostructures are examined. The focus is on quantum-well MISFETs, which differ most from more conventional devices. Results are presented of experiments and simulations carried out to study the physical mechanisms related to charge control, gate leakage, device geometry, short-channel effects, buffer leakage, and electron trapping in the devices, and the advantages of other III-V materials systems are described. The potential advantages of H-MISFETs are discussed in terms of particular circuit applications     

InGaAs enhancement-mode MISFETs using double-layer gate insulator

In this letter we describe the fabrication of enhancement-mode MISFETs on InGaAs grown by liquid-phase epitaxy (LPE) using an anodic Al2O3/anodic native oxide double layer as a gate insulator. The normally-off device of 10 ?m gate length shows the effective channel mobility of 1400 cm2/Vs. The interface state density distribution of this double-layer MIS of InGaAs is also reported. The density of 2 × 1013 cm?2 eV?1 at Ec ?0.057 eV and the minimum of 8 × 1011 cm?2 eV?1 near midgap are measured from C/V characteristics.     

Switching behaviour of Al2O3-n GaAs MISFETs

The switching behaviour of plasma alumina-n GaAs IGFETs is described in quasi normally-off and deep depletion modes. The observations of recovery from the off-state suggest that in each case this is controlled by the thermal generation of minority carriers.     

IGFET circuit performance-n-channel versus p-channel

The n-channel insulated-gate field-effect transistor offers a factor of 2 to 3.4 mobility advantage (depending on crystal orientation and substrate doping level) over p-channel devices. In addition, several advantages result from the fact that the work function difference between an aluminum gate and the silicon substrate is about -0.8 volt for a p substrate compared with about zero for an n substrate. In particular, this results in a low threshold voltage that allows the use of a substrate bias to adjust the threshold voltage over a useful design range resulting in an added flexibility in choice of thresholds and substrate doping, a reduction in the effect of source-substrate bias on device threshold, decreased junction capacitance, and larger parasitic thick-oxide thresholds for a given insulator thickness. The speed, power, and density advantages of the n-channel device are illustrated for logic and memory circuits using representative n- and p-channel device designs.     

Analytical model for p-channel MOSFETs

An analytical model for p-channel MOSFETs is described. The model is based on the unified charge control model (UCCM), which describes both the subthreshold and the above-threshold regimes using one continuous equation. Also derived and incorporated into the model is an equation for the dependence of the hole mobility on gate-to-source voltage and threshold voltage. The model makes it possible to propose a simple and unambiguous characterization procedure for extracting device parameters. Detailed measurements of capacitance-voltage and current-voltage characteristics of p-channel MOSFETs with different gate lengths are reported. Results are in excellent agreement with experimental results. The model is ideally suited for applications in computer-aided design software for simulation of both digital and analog circuits, and for automated parameter extraction     

InP MISFET及有关的高速低功耗逻辑集成电路

InP MISFET及有关的高速低功耗逻辑集成电路已受到越来越大的注意.本文介绍了这方面的发展现状、工艺制造及目前达到的性能等.对工艺制造中的核心部分——绝缘层生长作了重点介绍.最后提出了作者的几点看法.     

Anisotype-gate self-aligned p-channel heterostructure field-effecttransistors

A new self-aligned p-channel HFET structure was evaluated for application to complementary HFET circuits. The AlGaAs/InGaAs HFET structure uses an anisotype graded n⁺ InGaAs/GaAs semiconductor gate to enhance the barrier height of the FET, resulting in a significant reduction in gate leakage current at low voltages. With AlGaAs composition of x=0.3, and a thin AlAs spacer of 60 Å, leakage current was reduced by a factor of about 1000 at gate voltage of 1 V, when compared to AlGaAs/InGaAs HIGFET of aluminum content x=0.75. The anisotype PFET maintains high device transconductance, typically 50 mS/mm for 1.3×10 μm PFETs, high reverse breakdown voltages 9-10 V, and low capacitance. Microwave S -parameter characterization resulted in F_t of 5 GHz for a 1×50 μm PFET     

Over 20-GHz cutoff frequency submicrometer-gate diamond MISFETs

Submicrometer-gate (0.2-0.5-/spl mu/m) diamond metal-insulator-semiconductor field-effect transistors (MISFETs) were fabricated on an H-terminated diamond surface. The maximum transconductance in dc mode reaches 165 mS/mm, while the average transconductance is 70 mS/mm in submicrometer-gate diamond MISFETs. The highest cutoff frequency of 23 GHz and the maximum frequency of oscillation of 25 GHz are realized in the 0.2-/spl mu/m-gate diamond MISFET. From the intrinsic transconductances or the cutoff frequencies, the saturation velocities are estimated to be 4/spl times/10/sup 6/ cm/s in the submicrometer-gate FETs. They are reduced by gate-drain capacitance and source resistance.     

Submicrometer n+-Ge gate AlGaAs/GaAs MISFETs

Submicrometer n⁺-Ge gate AlGaAs/GaAs MISFETs have been developed by designing a fabrication process for the n⁺-implanted region. The short-channel effect was sufficiently suppressed by lowering the ion-implantation energy down to 50 keV to achieve a standard deviation of threshold voltage as small as 13 mV for 0.5-μm-gate FETs in a 2-in-diameter wafer. The source resistance was reduced by increasing the annealing temperature to 850°C to obtain a transconductance of 500 mS/mm for a 0.5-μm-gate FET. Even after annealing at such a high temperature, the quality of the channel layer was maintained at a sufficient level to realize a large cutoff frequency of 70 GHz for a 0.4-μm-gate FET. A divide-by-four static frequency divider was also fabricated using the above-mentioned fabrication technology. Successful operation at 16 GHz at 300 K was obtained with a divider using 0.9-μm-gate FETs at a low power dissipation of 36 mW per T-flip-flop     

Hot-carrier-induced degradation in p-channel LDD MOSFET's

When the p-channel MOSFET is stressed near the maximum substrate current Isub, the lifetime t (5-percent increase in the transconductance) followstI_{sub} = A(I_{sub}/I_{d})^{-n}, with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratioI_{sub}/I_{d}and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.     

Pulse-doped diamond p-channel metal semiconductor field-effecttransistor

A p-type diamond metal semiconductor field-effect transistor (MESFET) structure, utilizing a boron pulse-doped layer as the conducting channel, has been successfully fabricated. The pulse-doped structure consists of an undoped diamond buffer layer, a highly doped thin diamond active layer, and an undoped diamond cap layer grown by the microwave plasma assisted chemical vapor deposition method. It is shown that this field-effect transistor with a gate length of 4 μm and the gate width of 39 μm exhibits an extrinsic transconductance of 116 μS/mm with both pinch-off characteristics and current saturation     

Experimental results on submicron-size p-channel MOSFET's

We report results on p-channel MOSFET's with channel lengths as small as 0.5 µm. Using design criteria obtained from numerical simulation, the devices have been fabricated by a low temperature process with very short annealing times. Fabricated devices with submicron channel lengths are dominated by velocity saturation of holes. Comparing the drive capability of n- and p-channel devices, we find the intrinsic device currents to be within a factor of 1.4 for a channel length of 0.5 µm.     

Characteristics of p-channel Si nano-crystal memory

In this work, the feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. By comparing the programming characteristics of devices with nano-crystals and devices without nano-crystals, the role of dots as storage node is presented. The programming and erasing mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. In case of erasing, the electron tunneling occurs from either the conduction band or the valence band. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time     

Optimum p-channel isolation structure for CMOS

A two-dimensional numerical model of the width direction of a MOSFET is used to simulate the surface potential and the subthreshold current of p-channel devices. Fully-recessed, semi-recessed, and nonrecessed oxide isolation structures with various transition angles as well as interface charge are modeled. The nonrecessed oxide structure is superior for reducing subthreshold current, in some cases more than 20 percent. The fully-recessed oxide with a 90° transition angle provides maximum device density, a planar surface, and ease of fabrication. Experimental results indicate that for the fully-recessed oxide structure the p-channel device with interface charge will show a threshold-voltage variation of only 12 percent with widths varying from 10 to 1.5 µm, and an increase in subthreshold current of an order of magnitude compared to a wide device.     

Modeling of noise for p-channel DG-FinFETs

The noise performance of p-channel Double Gate FinFETs has been studied with varying structural parameters. The effects of mobility degradation due to velocity saturation, carrier heating and channel length modulation have been taken into consideration for an accurate modeling of noise. The dependence of mobility fluctuations on the inversion carrier density has been incorporated. This has been validated by the experimental results. The noise behavior of p-channel device has been compared to that of a corresponding n-channel device. It has been observed that noise in p-channel device is comparatively higher due to higher number of oxide-trap density in it. Further, it has been noted that with the same trap density in both p-channel and n-channel device, the flicker noise in the p-channel device is lower than that of the corresponding n-channel device.