Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET

In this paper, for the first time, we have analyzed DC characteristics and analog/RF performances for nanowire quadruple-gate (QuaG) gate-all-around (GAA) metal oxide semiconductor field effect transistor (MOSFET), using isomorphic polynomial function for potential distribution. The QuaG GAA MOSFET not only suppresses the short channel effects (SCEs) and offer ideal subthreshold slope (SS), but also is a good candidate for analog/RF device due to its high transconductance (g_m) and high cutoff frequency (f_T). Therefore, this work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. For this, the developed model is based on the solution of 3D Laplace and Poisson׳s equations for subthreshold and strong inversion regions respectively. The developed potential model has been used to formulate a new model for total gate, drain and source charge. Further, the expression for different capacitance for investigating RF performance is obtained from the developed model. Finally, the developed device electrostatics for QuaG GAA MOSFET have been used for the analysis of analog/RF performance. Different capacitances and analog/RF figures of merit are extracted from small signal frequency (1 MHz) ac device simulation. Whereas technology computer-aided design (TCAD) simulations have been performed by 3D ATLAS, Silvaco International.     

Effect of Si capping layer on the interface quality and NBTI of high mobility channel Ge-on-Si pMOSFETs

The effects of a Si capping layer on the device characteristics and negative bias temperature instability (NBTI) reliability were investigated for Ge-on-Si pMOSFETs. A Ge pMOSFET with a Si cap shows a lower subthreshold slope (SS), higher transconductance (G_m) and enhanced drive current. In addition, lower threshold voltage shift and G_m,max degradation are observed during NBTI stress. The primary reason for these characteristics is attributed to the improved interface quality at the high-k dielectric/substrate interface. Charge pumping was used to verify the presence of lower density of states in Ge pMOSFETs with a Si cap.     

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I_D=5 μA/μm and V_DS=0.5 V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V_DD=0.5 V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ～20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V_DD=0.5 V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ～10%, ～35% and ～25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric

In this paper, the length scaling of the silicon Double Gate Tunnel Field Effect Transistor (DG Tunnel FET) is studied. It is found that scaling limits are reached sooner by Tunnel FETs with an SiO₂ gate dielectric, while those with a high-K dielectric can be scaled further before threshold voltage, and average and point subthreshold swing are affected. It is demonstrated that the scaling of the high-K Tunnel FET is completely different than that of conventional MOS transistors. An outstanding feature of the Tunnel FET switch is that length scaling has a much weaker impact on device characteristics than does gate control (e.g. the use of a high-K dielectric), which primarily dictates the tunneling barrier width and consequently, device conduction. This paper demonstrates that while some improvements are observed, the length scaling does not dramatically affect switch figures of merit such as subthreshold slope, I_on and I_off down to about 20 nm, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET. A discussion of the length dependence of the transconductance, g_m, and output conductance, g_ds of the Tunnel FET is presented for the first time.     

A new analytical subthreshold model of SRG MOSFET with analogue performance investigation

For the first time, a pseudo-two-dimensional (2D) approach is extended from a rectangular device structure to a cylindrical one. A pseudo-2D model applying Gauss's law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in subthreshold regime is presented. From this pseudo-2D analysis, electrostatic potentials, current characteristics, the threshold voltage roll-off, the drain-induced barrier lowering and the subthreshold swing are explicitly modelled. The obtained analytical model has been extended to develop a model for transconductance-to-drain current ratio (g _m/I _d) in weak inversion regime. Analogue figures of merit of SRG MOSFETs are studied, including transconductance efficiency g _m/I _d, intrinsic gain and output resistance. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modelled expressions are compared with the simulated characteristics obtained from ATLAS device simulator.     

Improved performance of nanoscale junctionless transistor based on gate engineering approach

In this paper, we propose an effective method to improve the electrical characteristics of dual-material-gate (DMG) junctionless transistor (JLT) based on gate engineering approach, with the example of n-type double gate (DG) JLT with total channel length down to 30 nm. The characteristics are demonstrated and compared with conventional DMG DGJLT and single-material gate (SMG) DGJLT. The results show that the novel DMG DGJLT presents superior subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (G_m), ON/OFF current ratio, and intrinsic delay (τ). Moreover, these unique features can be controlled by engineering the length and workfunction of the gate material. In addition, the sensitivities of the novel DMG device with respect to structural parameters are investigated.     

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A_VO) and cut-off frequency (f_T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g_m), transconductance-to-current ratio (g_m/I_ds), Early voltage (V_EA), output conductance (g_ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs.     

GaAs-based metal-oxide semiconductor field-effect transistors with Al2O3 gate dielectrics grown by atomic layer deposition

We demonstrate GaAs-based, metal-oxide-semiconductor field-effect transistors (MOSFETs) with excellent performance using an Al₂O₃ gate dielectric, deposited by atomic layer deposition (ALD). This achievement is very significant because Al₂O₃ possesses highly desirable physical and electrical properties as a gate dielectric. These MOSFET devices exhibit extremely low gate-leakage current, high transconductance, and high dielectric breakdown strength. A short-circuit, current-gain, cutoff frequency (f_T) of 14 GHz and a maximum oscillation frequency (f_max) of 25.2 GHz have been achieved from a 0.65-μm gate-length device. The interface trap density (D_it) of Al₂O₃/GaAs is evaluated by the hysteresis of drain-source current, I_ds, versus gate-source bias, V_gs, and the frequency dispersion of transconductance, g_m.     

On the importance of the Vg,max-Vth parameter on LTPS TFT stressing behavior

In this work we point out the importance of the device parameter V_g,max-V_th (the difference between the gate voltage at maximum transconductance and the threshold voltage obtained from linear extrapolation method) for LTPS TFTs under dc stress. The evolution of this parameter with stress time is monitored for the first time, along with the other typical device parameters (V_th, G_m,max, S) in order to further clarify the nature of the traps generated. In the first dc stress case considered, we observed very different S degradation of the two samples, but very similar G_m,max degradation, as well as similar V_g,max-V_th evolution. Therefore, G_m,max evolution with stress time was found to be related more strongly to tail state generation, probed through V_g,max-V_th, and not to midgap trap generation, probed through S. In the second case, no midgap state generation is observed, but only severe tail state generation. Hence, the nature of the created defects and the reason for the significant G_m,max reduction could only be probed through the observation of V_g,max-V_th, a parameter not utilized until now. Finally, stressing both n- and p-channel devices, we are able to explain the much more intense G_m,max degradation observed for n-channel devices, associating it to the larger tail state generation in n-channel TFTs, also pointed by V_g,max-V_th evolution with stress.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

Novel attributes in scaling issues of carbon nanotube field-effect transistors

For the first time, we present a scaling study of carbon nanotube field-effect transistors (CNTFETs) using a two-dimensional model. We investigate the scaling issues in device performance focusing on transconductance characteristics, output characteristics, average velocity, I_on/I_off ratio, subthreshold swing and drain-induced barrier lowering (DIBL) with different gate oxide thicknesses and carbon nanotube (CNT) diameters. We concluded that the I_on/I_off ratio increases with the gate oxide thickness reduction and increase in the CNT diameter and lead to a high on-state current. Furthermore, leakage current reduces with decrease in the gate oxide thickness, but it becomes higher in CNTFETs with larger CNT diameter. Also, our results show the output conductance, transconductance, voltage gain and average electron velocity at the top of the barrier improve in CNTFETs with thinner gate oxide and larger CNT diameter. In addition, the investigation of short channel effects shows that CNTFETs with thinner gate oxide offer lower DIBL and subthreshold swing, but in the CNTFETs with larger CNT diameter DIBL and subthreshold swing become worse.     

Analog/RF Study of Self-aligned In<Subscript>0.53</Subscript>Ga<Subscript>0.47</Subscript>As MOSFET with Scaled Gate Length

This study presents the impact of gate length scaling on analog and radio frequency (RF) performance of a self- aligned multi-gate n-type In_0.53Ga_0.47As metal oxide semiconductor field effect transistor. The device is fabricated using a self-aligned method, air-bridge technology, and 8 nm thickness of the Al₂O₃ oxide layer with different gate lengths. The transconductance-to-normalized drain current ratio (g _m/I _D) method is implemented to investigate analog parameters. Moreover, g _m and drain conductance (g _D) as key parameters in analog performance of the device are evaluated with g _m/I _D and gate length variation, where g _m and g _D are both showing enhancement due to scaling of the gate length. Early voltage (V _EA) and intrinsic voltage gain (A _V) value presents a decreasing trend by shrinking the gate length. In addition, the results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.     

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

In this paper, electrical behavior of symmetric double gate Ge channel MOSFETs with high-k dielectrics is reported on the basis of carrier concentration formalism. The model relies on the solution of Poisson-Boltzmann equations subject to suitable boundary conditions taking into account the effect of interface trap charge density (D_it) and the Pao-Sah’s current formulation considering field dependent hole mobility. It is continuous as it holds good for sub-threshold, weak and strong inversion regions of device operation. The proposed model has been employed to calculate the drain current of DG MOSFETs for different values of gate voltage and drain voltage along with various important device parameters such as transconductance, output conductance, and transconductance per unit drain current for a wide range of interface trap charge density, equivalent oxide thickness (EOT) and bias conditions. Moreover, most of the important device parameters are compared with their corresponding Si counter parts. Accuracy of the model has been verified by comparing analytical results with the numerical simulation data. A notable improvement of the drive current and transconductance for Ge devices is observed with reference to Si devices, particularly when D_it is small.     

Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (V_gs) and the transconductance generation factor (g_m/I_d) considering the influence of drain current (I_d) and the transconductance (g_m). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.     

Simulation of InGaAs subchannel DG-HEMTs for analogue/RF applications

The paper reports on the influence of a barrier thickness and gate length on the various device parameters of double gate high electron mobility transistors (DG-HEMTs). The DC and RF performance of the device have been studied by varying the barrier thickness from 1 to 5 nm and gate length from 10 to 150 nm, respectively. As the gate length is reduced below 50 nm regime, the barrier thickness plays an important role in device performance. Scaling the gate length leads to higher transconductance and high frequency operations with the expense of poor short channel effects. The authors claim that the 30-nm gate length, mole fractions tuned In_0.53Ga_0.47As/In_0.7Ga_0.3As/In_0.53Ga_0.47As subchannel DG-HEMT with optimised device structure of 2 nm In_0.48Al_0.52As barrier layer show a peak g_m of 3.09 mS/µm, V_T of 0.29 V, I_ON/I_OFF ratio of 2.24 × 10⁵, subthreshold slope ~73 mV/decade and drain induced barrier lowering ~68 mV/V with f_T and f_max of 776 and 905 GHz at V_ds = 0.5 V is achieved. These superior performances are achieved by using double-gate architecture with reduced gate to channel distance.     

Effect of interface state trap density on the characteristics of n-type,enhancement-mode,implant-free In0.3Ga0.7As MOSFETs

The effect of interface state trap density, D_it, on the device characteristics of n-type, enhancement-mode, implant-free (IF) In_0.3Ga_0.7As MOSFETs [1], [2] has been investigated using a commercial drift-diffusion (DD) device simulation tool. Methodology has been developed to include arbitrary D_it distributions in the input simulation decks to more accurately fit the measured subthreshold characteristics of recently reported 1.0 μm gate length IF In_0.3Ga_0.7As MOSFETs [3]. The impact of interface states on a scaled 30 nm gate length IF MOSFET is also reported.     

Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs

Symmetric Dual-k Spacer (SDS) Hybrid FinFETs is a novel device, which combines three significant technologies i.e., 2-D ultra-thin-body (UTB), 3-D FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. For the first time, this article systematically analyzes the impacts of non-rectangular fin shape on various performance metrics of SDS Hybrid FinFETs. Under distinctive inclination fin angles as prescribed by the process technology, the performances of the device at different fin heights are examined. This work evaluates the response of fin tapering as well as fin height on parameters like threshold voltage (V_th), subthreshold slope (SS), on current (I_on), transconductance (g_m), transconductance generation factor (TGF), and total gate capacitance (C_gg) in SDS Hybrid FinFETs. Optimum structural configuration is thus proposed to fabricate the hybrid device in sub-20 nm FinFET architecture.     

Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs

The underlap double gate MOSFET (UDG-MOSFET) has been well established as a potential candidate for the RF applications. However, before implementation the various process related variations are required to be addressed for the better dependability. In this paper, the effect of process dependent parameter variations on the RF performance of the UDG-MOSFET is analyzed. The process dependent parameters considered are the oxide and the body thicknesses. The RF performance of UDG-MOSFET is analyzed as a function of RF figure of merits (FOMs), intrinsic capacitance (C_gs, C_gd), intrinsic resistance (R_gs, R_gd), transport delay (τ_m), inductance (L_sd) and analog FOMs transconductance (g_m), transconductance generation factor (g_m/I_d), output resistance (R_o) and intrinsic gain (g_mR_o). The analysis is performed using the non-quasi static (NQS) small signal model of the UDG-MOSFET.     

Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications

The impact of high permittivity gate dielectrics with different equivalent oxide thickness (EOT) for conventional, low and high tilt angle halo implants on the performance of 100 nm n-MOSFETs device is studied using device simulator Synopsys ISE-TCAD. In this paper, we systematically increase the value of gate dielectric (3.9-50) and investigate its effects on conventional, low angle of tilt (10^o) and high angle of tilt (50^o) halo implants for different device parameters of 100 nm n-MOSFETs using two different EOT viz. 1.5 nm and 2.0 nm. The impact of gate dielectric permittivity along with the different angles of halo implants on short channel performance contributing to the DIBL, the subthreshold swing, I_ON/I_OFF ratio, and the threshold voltage V_T are studied for two different EOT thicknesses. The device has been investigated for digital performance parameters like the variation of substrate-body voltage on DIBL, I_OFF, I_ON and the threshold voltage V_T for sub 100 nm technology generation. It has also been investigated for analog performance like trans-conductance generation factor (gm/I_D) and overall gain (gmR₀).