伯克利短沟道绝缘栅场效应晶体管模型的研究进展

随着金属氧化物半导体(MOS)集成电路工艺的飞速发展,体硅金属氧化物半导体场效应晶体管(MOSFET)模型经历了从物理到经验,最后到半经验物理的转变.介绍了以阈值电压和反转电荷为建模基础的伯克利短沟道绝缘栅场效应晶体管模型(BSIM),以及该模型中阈值电压、饱和电流和电容的基本建模理论.回顾了近年来体硅MOSFET BSIM的研究进展,着重从各种模型的优缺点、建模机理和适用范围方面分析了4种最有代表性的BSIM,即BSIM3v3,BSIM4,BSIM5和BSIM6.从模型的发展历史可以看出模型是随着MOSFET尺寸的缩小而不断完善和发展的.最后,对体硅MOSFET的模型发展趋势进行了展望.     

考虑量子效应的MOS器件表面势模型

介绍了目前基于表面势的MOSFET集约模型研究的最新进展,及考虑量子效应时对表面势进行修正的一般方法。并从三角势阱近似出发考虑量子效应,得到了一个新的表面势解析模型,并与经典理论和数值模拟结果进行了比较。模型简单、准确,且物理意义清晰,适合于植入到基于表面势的集约模型中。     

短沟道MOSFET源漏寄生电阻的二维半解析模型北大核心CSCD

根据金属氧化物半导体场效应晶体管(MOSFET)的工作原理,在MOSFET的源/漏区域引入了矩形等效源,提出了源/漏电阻的二维定解问题。通过用分离变量法、傅里叶展开和积分方程相结合建立MOSFET源/漏电阻的二维半解析模型,得到了源/漏电阻与几何尺寸之间的关系。该模型避免了数值分析时的方程的离散化,且具有较高的精度。计算和仿真结果表明,模型计算出的源/漏电阻阻值接近于Silvaco的仿真值。     

基于MESFET非线性模型的MOSFET DC建模技术

常用的MOSFET模型模型参数多且复杂,在保证精确度的基础上应尽量简化模型。尝试采用目前比较成熟通用的MESFET非线性等效电路经验模型表征射频MOSFET的直流特性。进行模型参数提取,从模型对MOSFET的DC仿真与测量曲线数据的对比结果,以及采用这6个模型仿真MOSFET直流特性时的RMS误差结果来看,这6个常用的MESFET非线性模型可以表征MOSFET的直流特性,参数越多模型精度越高。     

DSOI总剂量效应模型及背偏调控模型

总剂量辐射效应会导致绝缘体上硅金属氧化物半导体场效应晶体管(DSOI MOSFET)器件的阈值电压漂移、泄漏电流增大等退化特性。由于背栅端口的存在,SOI器件存在新的总剂量效应加固途径,对于全耗尽SOI器件,利用正背栅耦合效应,可通过施加背栅偏置电压补偿辐照导致的器件参数退化。本文研究了总剂量辐照对双埋氧层绝缘体上硅金属氧化物半导体场效应晶体管(DSOI MOSFET)总剂量损伤规律及背栅偏置调控规律,分析了辐射导致晶体管电参数退化机理,建立了DSOI晶体管总剂量效应模拟电路仿真器(SPICE)模型。模型仿真晶体管阈值电压与实测结果≤6 mV,同时根据总剂量效应模型给出了相应的背栅偏置补偿模型,通过晶体管背偏调控总剂量效应SPICE模型仿真输出的补偿电压与试验测试结果对比,N型金属氧化物半导体场效应晶体管(NMOSFET)的背偏调控模型误差为9.65%,P型金属氧化物半导体场效应晶体管(PMOSFET)为5.24%,该模型可以准确反映DSOI器件辐照前后阈值特性变化,为器件的背栅加固提供参考依据。     

亚100nm体硅MOSFET集约I-V模型

利用"局域化"的概念和二维泊松方程的解析解,建立了沟道方向上二维量子效应对阈电压的修正模型.基于密度梯度理论,建立了多晶硅栅内量子效应对阈电压的修正模型.在此基础上,结合弹道理论,开发了一个适用于亚100nm MOSFET的集约I-V模型.通过与TSMC提供的沟长为45nm实际器件测试结果[1],以及与三组亚100nm MOSFET的数值模拟结果的比较,证明了该模型具有良好的精度(平均误差小于8%)和可延伸性.     

超深亚微米SOI总剂量效应泄漏电流模型

总剂量辐射效应会导致绝缘体上硅金属氧化物半导体场效应晶体管(SOI MOSFET)器件的阈值电压漂移、泄漏电流增大等退化特性。浅沟槽隔离(STI)漏电是器件退化的主要因素,会形成漏极到源极的寄生晶体管。针对130 nm部分耗尽(PD) SOI NMOSFET器件的总剂量辐射退化特性,建立了一个包含总剂量辐射效应的通用模拟电路仿真器(SPICE)模型。在BSIM SOI标准工艺集约模型的基础上,增加了STI寄生晶体管泄漏电流模型,并考虑了辐射陷阱电荷引起寄生晶体管的等效栅宽和栅氧厚度的变化。通过与不同漏压下、不同宽长比的器件退化特性的实验结果对比,该模型能够准确反映器件辐射前后的漏电流特性变化,为器件的抗辐射设计提供参考依据。     

基于GaAs STATZ模型的RF MOSFET DC建模技术

STATZ模型是表征GaAsMESFET特性的常用模型,具有表达式简洁、参数少的优点。通过尝试将STATZ模型用于表征射频MOSFET的直流特性,提取并在ADS软件中优化了STATZ直流模型的参数。为了提高仿真精度,模型必须考虑晶体管漏极与源极的寄生电阻,根据MOSFET处于强反型区且漏-源电压为零时的等效电路模型提取了晶体管的漏极和源极的寄生电阻。在ADS软件中利用STATZ模型对MOSFET的直流特性进行了仿真,测量的MOSFET直流曲线与仿真曲线一致性很好,验证了模型的良好的精确度,证明了GaAs STATZ模型可以用于表征射频MOSFET的直流特性。晶体管采用中芯国际的0.13μm RF CMOS工艺制作。     

功率MOSFET的研究与进展

器件设计工艺、封装、宽禁带半导体材料和计算机辅助设计4大技术的发展进步使得功率MOSFET的性能指标不断达到新的高度。超级结技术使得高压功率MOSFET的导通电阻大大降低,降低栅极电荷和极间电容的改进沟槽工艺和横向扩散工艺技术进一步提高了低压功率MOSFET的优值因子,中小功率MOSFET继续朝着单片集成智能功率电子发展。功率MOSFET封装呈现出集成模块化、增强散热性和高可靠性的特点。基于宽禁带半导体材料SiC和GaN的功率MOSFET具有高温、高频和低功耗等优异性能,计算机辅助设计工具引领功率MOSFET在工艺设计、制造和电路系统应用方面快速发展。     

模拟集成电路仿真中的UDSM MOSFET建模

对MOSFET器件特性、MOSFET建模方法和建模发展历程进行了回顾,重点分析了在模拟集成电路设计中较为流行的几种模型:BSIM3、EKV和SP2001模型,对其各自的优缺点进行了比较。结果表明,获得能够精确地预测高性能模拟系统的模型是很困难的;几种模型中,EKV模型在模拟集成电路的低功耗设计中具有一定的优势。     

A review of compact modeling for phase change memory

Phase change memory(PCM)attracts wide attention for the memory-centric computing and neuromorphic comput-ing.For circuit and system designs,PCM compact models are mandatory and their status are reviewed in this work.Macro mod-els and physics-based models have been proposed in different stages of the PCM technology developments.Compact model-ing of PCM is indeed more complex than the transistor modeling due to their multi-physics nature including electrical,thermal and phase transition dynamics as well as their interactions.Realizations of the PCM operations including threshold switching,set and reset programming in these models are diverse,which also differs from the perspective of circuit simulations.For the purpose of efficient and reliable designs of the PCM technology,open issues and challenges of the compact modeling are also discussed.     

Black box modelling of the Op-Amp including switching power supply on effect

In general, models at the device and circuit levels are very important in system design. Building compact models at the circuit level is complicated, needs a lot of physical information about the circuit and moreover it has a long simulation time. We present in this paper an alternative modeling methodology, black box modeling. In this technique, we need only the output behavior of the circuit. We get this behavior either from measurements or simulations from previously built compact models. We apply this technique to the operational amplifier as a case study. We use the Op-Amp, BSIM3v3-based compact transistor model, to obtain the performance of the circuit. An excellent agreement is obtained between the output voltage from the black box model of the Op-Amp (for both of the effect of the switching power supply on and the steady state behavior) and the corresponding output from the model used to build it.     

Multiple block structure-preserving reduced order modeling of interconnect circuits

In this paper, we propose a generalized multiple-block structure-preserving reduced order interconnect macromodeling method (BSPRIM). Our approach extends the structure-preserving model order reduction (MOR) method SPRIM [R.W. Freund, SPRIM: structure-preserving reduced-order interconnect macromodeling, in: Proceedings of International Conference on Computer Aided Design (ICCAD), 2004, pp. 80-87] into more general block forms. We first show how an SPRIM-like structure-preserving MOR method can be extended to deal with admittance RLC circuit matrices and show that the 2q moments are still matched and symmetry is preserved. Then we present the new BSPRIM method to deal with more circuit partitions for linear dynamic circuits formulated in impedance and admittance forms. The reduced models by BSPRIM will still match the 2q moments and preserve the circuit structure properties like symmetry as SPRIM does. We also show that BSPRIM can build the compact models with similar size and accuracy of that produced by traditional projection based methods but using less computation costs. Experimental results show that BSPRIM outperforms SPRIM in terms of accuracy with more partitions and outperforms PRIMA with less CPU times for generating the same accurate models.     

Compact model generation for on-chip transmission lines

An approach for the fast and accurate generation of compact distributed circuit models for on-chip transmission lines on lossy silicon substrates is presented. Using a novel ABCD matrix partitioning procedure, accurate distributed circuit models are extracted from scattering parameters obtained from measurements and calibrated full-wave electromagnetic simulations for a small set of transmission-line geometries spanning ranges of design parameter values. A feedforward artificial neural network is trained using the extracted results, and applied to generate accurate compact models for arbitrary values within the bounds of the training ranges. Consequently, the model generation time is greatly reduced compared to conventional approaches by exploiting the interpolation capabilities of the neural network. The compact model generator is fully compatible with HSPICE and SPECTRE-RF and is easily incorporated into parasitic-aware RF circuit design and optimization tools.     

Generating compact, guaranteed passive reduced-order models of 3-D RLC interconnects

As very large scale integration (VLSI) circuit speeds and density continue to increase, the need to accurately model the effects of three-dimensional (3-D) interconnects has become essential for reliable chip and system design and verification. Since such models are commonly used inside standard circuit simulators for time or frequency domain computations, it is imperative that they be kept compact without compromising accuracy, and also retain relevant physical properties of the original system, such as passivity. In this paper, we describe an approach to generate accurate, compact, and guaranteed passive models of RLC interconnects and packaging structures. The procedure is based on a partial element equivalent circuit (PEEC)-like approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior. The resulting formulation, based on nodal or mixed nodal and mesh analysis, enables the application of existing model order reduction techniques. Compactness and passivity of the model are then ensured with a two-step reduction procedure where Krylov-subspace moment-matching methods are followed by a recently proposed, nearly optimal, passive truncated balanced realization-like algorithm. The proposed approach was used for extracting passive models for several industrial examples, whose accuracy was validated both in the frequency domain as well as against measured time-domain data.     

一个改进的量子隐形传态回路

量子隐形传态是一种典型的量子通信方式,它用经典辅助的方法来传送量子态,并引入了量子纠缠的特性.实现隐形传态的量子回路形式有很多,为了更有效地传递量子态,本文在Brassard回路的基础上提出一个改进的量子回路,它具有更简洁的结构,并能实现量子隐形传态.     

Circuit level prediction of device performance degradation due to negative bias temperature stress

A circuit level methodology for predicting performance degradations due to negative bias temperature stress is developed in this paper. Degradation mechanism is discussed based on experimental observations. Then, models that consist of a threshold voltage shift and a drain current reduction are developed based on the degradation mechanism. The developed models are implemented into a compact MOSFET model so that we can directly link the local degradation of pMOSFETs’ electrical characteristics to the total circuit performances. The validity of the developed models is confirmed by the good agreement in simulated and measured results of I–V characteristics of pMOSFET in all the transistor working region before and after negative bias temperature stress. Then, circuit performance prediction is carried out for the stressed 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between the experimental results and predicted results are obtained.     

Practical modeling for circuit simulation

There is much more to modeling for circuit simulation than deriving a set of I(V), and perhaps Q(V), equations and extracting a SPICE MODEL card. Unfortunately, some practical aspects of modeling are often overlooked. This paper details common-sense guidelines for modeling and highlights common modeling problems. Particular emphasis is given on understanding accuracy requirements and numerical requirements, on ensuring that compact models are asymptotically correct, and on highlighting the real goal of modeling for circuit simulation: getting complete models for allowable device layouts working in the CAD system on a designer's desk     

Equivalent circuit approach for single electron transistor modelfor efficient circuit simulation by SPICE

A new compact DC/transient single electron transistor model for circuit simulation by SPICE is introduced. This model includes newly developed equivalent circuit approach based on the time-dependent master equation and an exact conductance or transient conductance model. The simulation speed of this model is improved compared with that of the previous models