Thermally stimulated current in SiO2

Thermally stimulated current (TSC) techniques provide information about oxide-trap charge densities and energy distributions in MOS (metal-oxide-semiconductor) capacitors exposed to ionizing radiation or high-field stress that is difficult or impossible to obtain via standard capacitance–voltage or current–voltage techniques. The precision and reproducibility of measurements through repeated irradiation/TSC cycles on a single capacitor is demonstrated with a radiation-hardened oxide, and small sample-to-sample variations are observed. A small increase in E′_δ center density may occur in some non-radiation-hardened oxides during repeated irradiation/TSC measurement cycles. The importance of choosing an appropriate bias to obtain accurate measurements of trapped charge densities and energy distributions is emphasized. A 10 nm deposited oxide with no subsequent annealing above 400°C shows a different trapped-hole energy distribution than thermally grown oxides, but a similar distribution to thermal oxides is found for deposited oxides annealed at higher temperatures. Charge neutralization during switched-bias irradiation is found to occur both because of hole-electron annihilation and increased electron trapping in the near-interfacial SiO₂. Limitations in applying TSC to oxides thinner than 5 nm are discussed.     

Effect of SiO2/Si interface roughness on gate current

In many theoretical investigations of the electric-tunnel effect through an ultrathin oxide in metal-oxide-semiconductor (MOS) structure, it is commonly assumed that the oxide is of uniform thickness. One example of nonuniformity in oxides is interface roughness. Interface roughness effects on direct tunneling current in ultrathin MOS structures are investigated theoretically in this article. The roughness at SiO₂/Si interface is described in terms of Gauss distribution. It is shown that the transmission coefficient increases with root-mean-square (rms) roughness increasing, and the effect of rms roughness on the direct tunneling current decreases with the applied voltage increasing and increases with rms roughness increasing.     

Electroluminescence from Au/Si/SiO2/p-Si structure

Si/SiO₂ films have been grown using the two-target alternation magnetron sputtering technique. The thickness of the SiO₂ layer in all the films was 8 nm and that of the Si layer in five types of the films ranged from 4 to 20 nm in steps of 4 nm. Visible electroluminescence (EL) has been observed from the Au/Si/SiO₂/p-Si structures at a forward bias of 5 V or larger. A broad band with one peak 650–660 nm appears in all the EL spectra of the structures. The effects of the thickness of the Si layer in the Si/SiO₂ films and of input electrical power on the EL spectra are studied systematically.     

Flat-field spectrograph in SiO2/Si

The operation of a flat-field spectrograph in silica glass on silicon (SiO₂/Si) as a demultiplexer with 4-nm channel spacing in the 1.5-μm waveguide length region is demonstrated. The concept allows fabrication tolerances to be compensated simultaneously with the adjustment of fan-out. Fiber-to-fiber insertion loss of 10.1 dB and crosstalk attenuation >15 dB have been achieved     

Improving low-temperature APCVD SiO2 passivation byrapid thermal annealing for Si devices

The quality of low-temperature (≈400°C) atmospheric pressure chemical vapor deposited (APCVD) silicon dioxide (SiO₂ ) films has been improved by a short time rapid thermal annealing (RTA) step. The RTA step followed by a low temperature (400°C) forming gas anneal (FGA) results in a well-passivated Si-SiO₂ interface, comparable to thermally grown conventional oxides. Efficient and stable surface passivation is obtained by this technique on virgin silicon as well as on photovoltaic devices with diffused (n⁺p) emitter surface while maintaining a very low thermal budget. Device parameters are improved by this APCVD/RTA/FGA passivation process     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

Atomic-layer-deposited Al2O3 and HfO2 on GaN: A comparative study on interfaces and electrical characteristics

Al₂O₃, HfO₂, and composite HfO₂/Al₂O₃ films were deposited on n-type GaN using atomic layer deposition (ALD). The interfacial layer of GaON and HfON was observed between HfO₂ and GaN, whereas the absence of an interfacial layer at Al₂O₃/GaN was confirmed using X-ray photoelectron spectroscopy and transmission electron microscopy. The dielectric constants of Al₂O₃, HfO₂, and composite HfO₂/Al₂O₃ calculated from the C-V measurement are 9, 16.5, and 13.8, respectively. The Al₂O₃ employed as a template in the composite structure has suppressed the interfacial layer formation during the subsequent ALD-HfO₂ and effectively reduced the gate leakage current. While the dielectric constant of the composite HfO₂/Al₂O₃ film is lower than that of HfO₂, the composite structure provides sharp oxide/GaN interface without interfacial layer, leading to better electrical properties.     

Interface states in SiSiO2 interfaces

Interface state parameters were studied in MOS capacitors over a wide range of energy by conductance and capacitance measurements at various temperatures from room temperature to liquid nitrogen temperature. A new technique was developed for analysis of the data which allows to obtain the density of states, the capture cross section, the surface potential and the dispersion parameter from the conductance and capacitance vs. frequency curves. The density of interface states as well as the electron capture cross section were found to be a function of energy only and to be independent of temperature. Maxima in the density of states have not been found.     

Temperature and frequency dependent electrical and dielectric properties of Al/SiO2/p-Si (MOS) structure

The electrical and dielectric properties of Al/SiO₂/p-Si (MOS) structures were studied in the frequency range 10 kHz-10 MHz and in the temperature range 295-400 K. The interfacial oxide layer thickness of 320 Å between metal and semiconductor was calculated from the measurement of the oxide capacitance in the strong accumulation region. The frequency and temperature dependence of dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tan δ) and the ac electrical conductivity (σ_ac) are studied for Al/SiO₂/p-Si (MOS) structure. The electrical and dielectric properties of MOS structure were calculated from C-V and G-V measurements. Experimental results show that the ε′ and ε″ are found to decrease with increasing frequency while σ_ac is increased, and ε′, ε″, tan δ and σ_ac increase with increasing temperature. The values of ε′, ε″ and tan δ at 100 kHz were found to be 2.76, 0.17 and 0.06, respectively. The interfacial polarization can be more easily occurred at low frequencies, and the number of interface state density between Si/SiO₂ interface, consequently, contributes to the improvement of dielectric properties of Al/SiO₂/p-Si (MOS) structure. Also, the effects of interface state density (N_ss) and series resistance (R_s) of the sample on C-V characteristics are investigated. It was found that both capacitance C and conductance G were quite sensitive to temperature and frequency at relatively high temperatures and low frequencies, and the N_ss and R_s decreased with increasing temperature. This is behavior attributed to the thermal restructuring and reordering of the interface. The C-V and G/ω-V characteristics confirmed that the N_ss, R_s and thickness of insulator layer (δ) are important parameters that strongly influence both the electrical and dielectric parameters and conductivity in MOS structures.     

Incomplete charge transfer in CMOS image sensor caused by Si/SiO2 interface states in the TG channel

CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO₂ interface state traps in the charge transfer path, which reduces the charge transfer efficiency and image quality. Until now, scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition. However, the existing models have thus far ignored the charge transfer limitation due to Si/SiO₂ interface state traps in the transfer gate channel, particularly under low illumination. Therefore, this paper proposes, for the first time, an analytical model for quantifying the incomplete charge transfer caused by Si/SiO₂ interface state traps in the transfer gate channel under low illumination. This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution, exponential distribution and measured distribution. The model was verified with technology computer-aided design simulations, and the results showed that the simulation results exhibit the consistency with the proposed model.     

Evolution of surface-states density of Si/wet thermal SiO2 interface during bias-temperature treatment

Evolution of Si/SiO₂ surface state density during a negative bias temperature treatment is reported. Two kinds of surface state are observed and their evolution is studied with the oxidation conditions, the type of the substrate and a preliminary electronic irradiation as parameters. A qualitative model is proposed to explain the observed results.     

Evaluation of trap creation and charging in thin SiO2 using both SCM and C-AFM

Conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) are used in this work to characterize trap creation and charge trapping in ultra-thin SiO₂. It is found that C-AFM working at normal operational voltages causes severe damage and subsequent negative charge trapping in the oxide. Permanent hillocks are seen in the topography of stressed regions. The height of these features is determined rather by the applied voltage than the electric field. Electrostatic repulsion between tip and sample and Si epitaxy underneath the oxide are the two most probable causes of this feature. The immediate physical damage caused in the oxide during high field C-AFM measurements is a possible showstopper for use of the C-AFM to investigate differences in pristine interface states. SCM operates at lower voltages, yielding less oxide damage and is able to indicate the interface state density variations through hysteresis in the dC/dV vs. V curves.     

Surface charge and stress in the Si/SiO2 system

A model for the stress distribution in thermally oxidised silicon slices has been developed using beam theory and bimetallic strip theory. The stresses have been confirmed by making lattice parameter measurements on oxidised silicon using the APEX X-ray diffraction technique. The often suggested relationship between the surface charge density at the Si/SiO₂ interface and the stress in the silicon surface has been investigated and shown to be inconsistent. Finally, analysis of the variation of surface charge density with oxide thickness has caused us to postulate the presence of both positively and negatively charged centres at the interface.     

Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO2 as a gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO₂ gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO₂ thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states (D_it) at the HfO₂/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D_it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.     

Laser-induced self-organization of nano-wires on SiO2/Si interface

Original observation of new graded band gap structures formed on the surface of elementary Si semiconductor at studying the optical properties of Si nano-hills formed at the SiO₂/Si interface by pulsed Nd:YAG laser irradiation is reported. The self-organized nano-hills on Si surface are characterized by a strong photoluminescence in the visible range of spectrum with a shoulder extended to the long-wave part of the spectrum. The feature is explained by the quantum confinement effect in nano-hills-nano-wires of gradually changing diameter.     

Determination of Si/SiO2 interface roughness using weaklocalization

The interface roughness of intentionally textured Si/SiO₂ interfaces was measured using the quantum weak localization (WL) correction to the electrical conductivity at low temperatures. The deduced roughness was confirmed by observation of the Si surface replicas by atomic force microscopy (AFM). Quantitative agreement between the two methods was found (Δ=1.2 to 1.4 Å from WL and 1.35 Å from AFM). For a surface with artificially induced texture, it is found that WL can easily distinguish a significant increase in roughness relative to the smooth surfaces. AFM confirms this qualitative conclusion     

Analysis of electrical characteristics of Au/SiO2/n-Si (MOS) capacitors using the high-low frequency capacitance and conductance methods

The purpose of this paper is to analyze electrical characteristics in Au/SiO₂/n-Si (MOS) capacitors by using the high-low frequency (C_HF-C_LF) capacitance and conductance methods. The capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements have been carried out in the frequency range of 1 kHz-10 MHz and bias voltage range of (−12 V) to (12 V) at room temperature. It was found that both C and G/ω of the MOS capacitor were quite sensitive to frequency at relatively low frequencies, and decrease with increasing frequency. The increase in capacitance especially at low frequencies is resulting from the presence of interface states at Si/SiO₂ interface. Therefore, the interfacial states can more easily follow an ac signal at low frequencies, consequently, which contributes to the improvement of electrical properties of MOS capacitor. The interface states density (N_ss) have been determined by taking into account the surface potential as a function of applied bias. The energy density distribution profile of N_ss was obtained from C_HF-C_LF capacitance method and gives a peak at about the mid-gap of Si. In addition, the high frequency (1 MHz) capacitance and conductance values measured under both reverse and forward bias have been corrected for the effect of series resistance (R_s) to obtain the real capacitance of MOS capacitors. The frequency dependent C-V and G/ω-V characteristics confirm that the N_ss and R_s of the MOS capacitors are important parameters that strongly influence the electrical properties of MOS capacitors.     

SOI planar photonic crystal fabrication: Etching through SiO2/Si/SiO2 layer systems using fluorocarbon plasmas

Dry plasma etching of sub-micron structures in a SiO₂/Si/SiO₂ layer system using Cr as a mask was performed in a fluorocarbon plasma. It was determined that the best anisotropy could be achieved in the most electropositive plasma. A gas composition yielding the desired SOI planar photonic crystal structures was optimized from the available process gases, Ar, He, O₂, SF₆, CF₄, c-C₄F₈, CHF₃, using DC bias data sets. Application of the c-C₄F₈/(noble gas) chemistry allowed fabrication of the desired SOI planar photonic crystal. The average etching rates for the pores and ridge waveguide regions were about 71 and 97 nm/min, respectively, while the average SiO₂/Si/SiO₂ to Cr etching selectivity for the ridge waveguide region was about 33:1 in case of the c-C₄F₈/90%Ar plasma with optimized parameters.     

MOS characteristics of ultrathin SiO2 prepared byoxidizing Si in N2O

MOS characteristics of ultrathin gate oxides prepared by furnace oxidizing Si in N₂O have been studied. Compared to control oxides grown in O₂, N₂O oxides exhibit significantly improved resistance to charge trapping and interface state generation under hot-carrier stressing. In addition, both charge to breakdown and time to breakdown are improved considerably. MOSFETs with N₂O gate dielectrics exhibit enhanced current drivability and improved resistance to g_m degradation during channel hot-electron stressing     

Charge storage peculiarities in poly-Si–SiO2–Si memory devices with Si nanocrystals rich SiO2

The paper focuses on the study of charge trapping processes in non-volatile memory metal-oxide-silicon (MOS) structures with Si nanocrystal floating gate formed by Si ion implantation. Careful electrical studies of the MOS structures based on the analysis of the capacitance–voltage (C–V) characteristics during pulse charge injection in the oxide enabled the distinguishing of the electron emission from the nanoclusters and the charge trapping in structural defects of the dioxide matrix. The trapping model is discussed.