Characterization of transient currents in HfO2 capacitors in the short timescale

We present a detailed experimental investigation of transient currents in HfO₂ capacitors in the short timescale. We show that the transient currents flowing through the capacitor plates when the gate voltage is reset to zero after a low voltage stress period follow a power-law time dependence t^−α (with α ? 1) over more than eight decades of time and down to the μs timescale. As transient currents in HfO₂ are largely increased with respect to the SiO₂ case, these results confirm that transient effects can be a severe issue for the successful integration of high-k dielectrics.     

X-ray metrology for high-k atomic layer deposited HfxZr1−xO2 films

Hafnium-based dielectrics are the most promising material for SiO₂ replacement in future nodes of CMOS technology. While devices that utilize HfO₂ gate dielectrics suffer from lower carrier mobility and degraded reliability, our group has recently reported improved device characteristics with a modified Hf_xZr_1−xO₂ [R.I. Hegde, D.H. Triyoso, P.J. Tobin, S. Kalpat, M.E. Ramon, H.-H. Tseng, J.K. Schaeffer, E. Luckowski, W.J. Taylor, C.C. Capasso, D.C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L.B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R.S. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y.H. Chiu, B.E. White, Jr., in: Technical Digest - International Electron Devices Meet, vol. 39, 2005, D.H. Triyoso, R.I. Hegde, J.K. Schaeffer, D. Roan, P.J. Tobin, S.B. Samavedam, B.E. White, Jr., R. Gregory, X.-D. Wang, Appl. Phys. Lett. 88 (2006) 222901]. These results have lead to evaluation of X-ray reflectivity (XRR) for monitoring high-k film thickness and control of Zr addition to HfO₂ using measured film density. In addition, a combination of XRR and spectroscopic ellipsometry (SE) is shown to be a fast and non-intrusive method to monitor thickness of interfacial layer between high-k and the Si substrate.     

Influence of the oxidation temperature on the non-trigonal Ge dangling bonds at the (1 0 0)Ge/GeO2 interface

GeO₂ was proposed as valuable passivation layer at the surface with Ge to integrate oxide with high dielectric constant in Ge-based logic devices. Hence, the identification of the defects present at different Ge/GeO₂ interfaces becomes a mandatory issue to predict the electrical features of devices based on such materials. High sensitive electrically detected magnetic resonance measurements were performed to study the microstructure of defects occurring at such an interface. The influence of the oxidation temperature on the electrically active paramagnetic traps was investigated.     

Epitaxial growth of Dy2O3 thin films on epitaxial Dy-germanide films on Ge(0 0 1) substrates

Ultra-thin films of Dy are grown on Ge(0 0 1) substrates by molecular beam deposition near room temperature and immediately annealed for solid phase epitaxy at higher temperatures, leading to the formation of DyGe_x films. Thin films of Dy₂O₃ are grown on the DyGe_x film on Ge(0 0 1) substrates by molecular beam epitaxy. Streaky reflection high energy electron diffraction (RHEED) patterns reveal that epitaxial DyGe_x films grow on Ge(0 0 1) substrates with flat surfaces. X-ray diffraction (XRD) spectrum suggests the growth of an orthorhombic phase of DyGe_x films with (0 0 1) orientations. After the growth of Dy₂O₃ films, there is a change in RHEED patterns to spotty features, revealing the growth of 3D crystalline islands. XRD spectrum shows the presence of a cubic phase with (1 0 0) and (1 1 1) orientations. Atomic force microscopy image shows that the surface morphology of Dy₂O₃ films is smooth with a root mean square roughness of 10 Å.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

Resistive switching effects of HfO2 high-k dielectric

Resistive switching behavior of HfO₂ high-k dielectric has been studied as a promising candidate for emerging non-volatile memory technology. The low resistance ON state and high resistance OFF state can be reversibly altered under a low SET/RESET voltage of ±3 V. The memory device shows stable retention behavior with the resistance ratio between both states maintained greater than 103. The bipolar nature of the voltage-induced hysteretic switching properties suggests changes in film conductivity related to the formation and removal of electronically conducting paths due to the presence of oxygen vacancies induced by the applied electric field. The effect of annealing on the switching behavior was related to changes in compositional and structural properties of the film. A transition from bipolar to unipolar switching behavior was observed upon O₂ annealing which could be related to different natures of defect introduced in the film which changes the film switching parameters. The HfO₂ resistive switching device offers a promising potential for high density and low power memory application with the ease of processing integration.     

Towards metal electrode interface scavenging of rare-earth scandates: A Sc2O3 and Gd2O3 study

Amorphous Gd₂O₃ and Sc₂O₃ thin films were deposited on Si by high-pressure sputtering (HPS). In order to reduce the uncontrolled interfacial SiO_x growth, firstly a metallic film of Gd or Sc was sputtered in pure Ar plasma. Subsequently, they were in situ plasma oxidized in an Ar/O₂ atmosphere. For post-processing interfacial SiO_x thickness reduction, three different top metal electrodes were studied: platinum, aluminum and titanium. For both dielectrics, it was found that Pt did not react with the films, while Al reacted with them forming an aluminate-like interface and, finally, Ti was effective in scavenging the SiO₂ interface thickness without severely compromising gate dielectric leakage.     

Electron states at the (1 0 0)Ge/HfO2 Interface

The energy distribution of extended and localized electron states at the Ge/HfO₂ interface is determined by combining the internal photoemission of electrons and holes from Ge into the Hf oxide and AC capacitance/conductance measurements. The inferred offsets of the conduction and valence band at the interface, i.e., 2.0 ± 0.1 and 3.0 ± 0.1 eV, respectively, suggest the possibility to apply the deposited HfO₂ layer as a suitable insulator on Ge. The post-deposition annealing of the Ge/HfO₂ structures in oxygen results in 1 eV reduction of the valence band offset, which is attributed to the growth of a GeO₂ interlayer. However, this treatment enables one to substantially reduce the density of Ge/HfO₂ interface traps, approaching ≈1×10¹² cm⁻² eV⁻¹ near the Ge midgap.     

Characterization of the annealing impact on La2O3/HfO2 and HfO2/La2O3 stacks for MOS applications

The impact of various rapid thermal annealing used during the integration on the La₂O₃/HfO₂ and HfO₂/La₂O₃ stacks deposited by Atomic Layer deposition was analyzed. The consequences of lanthanum localization in such stacks on the evolution of the films during the rapid thermal annealing are investigated in term of morphology, crystalline structure, silicate formation and film homogeneity as a function of the depth. It appeared that the La₂O₃ location has an impact on the temperature of the quadratic phase formation which could be linked to the formation of SiOHfLa silicate and the resistance of the films to dissolution in HF 0.05 wt%.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

Effect of biasing at elevated temperature on the electronic structure of Pt/HfO2/Si stacks

The spatial distribution of charges in a Pt/HfO₂/Si stack has been manipulated by applying a cyclic bias voltage ±2.5 V in combination with moderate (T ∼ 630 K) heating. The modifications were monitored in situ by room temperature capacitance-voltage (C-V) and current-voltage (I-V) measurements and analyzed ex situ by hard X-ray photoelectron spectroscopy which additionally provides information on possible chemical changes at the interfaces. The experimental data on the charge/potential distributions resulting from the different steps of bias-temperature stress (BTS) are consistent with the model that additional oxygen vacancies, which are generated in HfO₂ and positively charged by charge transfer across the interface with a high work function metal (Pt), are driven across the HfO₂ layer. These vacancies ultimately control the observed growth/dissolution of SiO_x at the bottom interface upon negative/positive BTS, respectively.     

Reliability and gate conduction variability of HfO2-based MOS devices: A combined nanoscale and device level study

The electrical properties and reliability of MOS devices based on high-k dielectrics can be affected when the gate stack is subjected to an annealing process, which can lead to the polycrystallization of the high-k layer. In this work, a Conductive Atomic Force Microscope (C-AFM) has been used to study the nanoscale electrical conduction and reliability of amorphous and polycrystalline HfO₂ based gate stacks. The link between the nanoscale properties and the reliability and gate conduction variability of fully processed MOS devices has also been investigated.     

Epitaxial growth of Fe/MgO/Ge(0 0 1) heterostructures

We report on the growth of epitaxial Fe/MgO heterostructures on Ge(0 0 1) by Molecular Beam Epitaxy. The better crystal quality and interfacial chemical sharpness at the oxide-semiconductor interface have been obtained by growing MgO at room temperature, followed by a post-annealing at 773 K, on top of a p(2 × 1)-Ge(0 0 1) clean surface. The growth of Fe at room temperature followed by annealing at 473 K gives the best epitaxial structure with optimized crystallinity of each layer compatible with limited chemical interdiffusion. Tunneling devices based on the epitaxial Fe/MgO/Ge heterostructure have been micro-fabricated and tested in order to probe the electrical properties of the MgO barrier. The current-voltage characteristics clearly show that tunneling is the dominant phenomenon, thus indicating that this system is very promising for practical applications in electronics and spintronics.     

Atomic oxygen-assisted molecular beam deposition of Gd2O3 films for ultra-scaled Ge-based electronic devices

The atomic oxygen-assisted molecular beam deposition of Gd₂O₃ films on Ge(0 0 1) substrates has been performed at various growth temperatures. The compositional aspects, the interface details and the surface structure have been investigated by in situ X-ray photoelectron spectroscopy, time-of-flight secondary ion mass spectroscopy and in situ atomic force microscopy, and ex situ. The interface layer of GeO₂ has been subsequently fabricated by means of atomic oxygen exposure in order to passivate the high-k/Ge interface. The electrical characterization on the final Gd₂O₃/GeO₂/Ge structure has been reported. The electrical characterization on the Al gate/Gd₂O₃/GeO₂/Ge structure exhibits a MOS behavior, indicating the beneficial effect of GeO₂ passivation.     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

Structural and electrical properties of Er-doped HfO2 and of its interface with Ge (0 0 1)

Er-doped HfO₂ thin films with Er content ranging from 0% to 15% are deposited by atomic layer deposition on native oxide free Ge(001). The crystallographic phase is investigated by X-ray diffraction and is found to depend on the Er%. The cubic fluorite structure develops on Ge for Er% as low as 4% and is stable after annealing at 400 °C in N₂. Microstrain increases with increasing the Er content within the fluorite structure. Time of flight secondary ion mass and electron energy loss spectroscopy evidence a Ge diffusion from the substrate that results in the formation of a Ge-rich interfacial region which does not present a structural discontinuity with the oxide. The diffusion of Ge is enhanced by the annealing and causes a reordering of the crystal lattice. In annealed films the interface defect density measured by low temperature conductance measurements is found to decrease with decreasing the Er content.     

XPS and IPE analysis of HfO2 band alignment with high-mobility semiconductors

A detailed analysis of the band alignment between atomic-layer deposition (ALD)-grown HfO₂ thin films and n-type Ge(1 0 0) substrate is presented. The valence band offset (VBO) is determined by X-ray photoelectron spectroscopy (XPS) after careful evaluation of the experimental data and accurate removal of the artefacts induced by differential charging phenomena occurring during XPS measurement. VBO values are 2.7±0.1 eV for all samples independent of the different growth conditions. A conduction band offset (CBO) of 2.0±0.1 eV and a band gap of 5.6±0.1 eV have been obtained by internal photoemission (IPE) and photoconductivity measurements, respectively. VBO and CBO values obtained by the different techniques are in excellent agreement within the experimental error.     

Al-oxynitrides as a buffer layer for Pr2O3/SiC interfaces

We elaborate the possibility of combining high-k dielectrics with wide band gap semiconductors, i.e. Pr₂O₃ on SiC. The thermal stability of interfacial aluminum oxynitride (AlON) layers between Pr-oxide and SiC has been investigated by synchrotron radiation photoemission spectroscopy (SRPES). The interface of Pr₂O₃ with SiC is reactive. Such reaction is successfully prevented by utilizing a stable interlayer derived from AlON. No elemental carbon is observed in detectable amount after Pr-Oxide deposition on AlON covered 3C-SiC and subsequent vacuum annealing. After vacuum annealing at 500 °C AlON transformed to AlN and Pr-aluminate with a small amount of CN close to the SiC surface which were thermally stable even at 900 °C. AlON hence provides a good diffusion barrier between Pr-oxide dielectric and 3C-SiC.