A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

A CMOS linear-in-dB VGA and AGC loop for telecommunication applications

In this paper, an Automatic Gain Control (AGC) loop which is based on a linear-in-dB Variable Gain Amplifier (VGA) is proposed. The VGA structure is based on simple nMOS differential pairs with variable tail currents. The linear-in-dB gain tuning schema is designed using a novel exponential current generator which also offers temperature compensation of the VGA's gain. The gain of the VGA is tuned by a control voltage with gain range about 28 dB with ±1 dB linearity error. The worst cases of the VGA gain, over process and temperature corners, are ±1.54 dB and ±2.45 dB for maximum and minimum gain setting, respectively. The proposed implementation is designed in a CMOS 90 nm triple-well process with 1.2 V supply voltage.     

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.     

A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium

In this paper a novel device named as SDOV MOSFET is proposed for the first time. This structure features localized void layers under the source and drain regions. The short channel effects of this device can be improved due to the SOI-like source/drain structure. In addition, without the dielectric layer under the channel region, this device can avoid some weaknesses of UTB SOI devices caused by the thin silicon film and the underlying buried oxide, such as mobility degradation, film thickness fluctuation and self-heating effect. Based on self-aligned hydrogen and helium co-implantation technology, the new device can be fabricated by a process compatible with the standard CMOS process. The SDOV MOSFETs with 50 nm gate length are experimentally demonstrated for verification.     

High mobility compressive strained Si0.5Ge0.5 quantum well p-MOSFETs with higher-k/metal-gate

Strained SiGe quantum well p-MOSFETs with LaLuO₃ higher-k dielectric were fabricated and characterized. The strained Si/strained Si_0.5Ge_0.5/strained SOI heterostructure transistors showed good output and transfer characteristics with an I_on/I_off ratio of 10⁵. The extracted hole mobility shows an enhancement of about 2.5 times over Si universal hole mobility and no degradation compared to HfO₂ or even SiO₂ gate dielectric devices.     

Annealing effect on physical and electrical characteristics of thin HfO2, HfSixOy and HfOyNz films on Si

We report the effect of annealing on electrical and physical characteristics of HfO₂, HfSi_xO_y and HfO_yN_z gate oxide films on Si. Having the largest thickness change of 0.3 nm after post deposition annealing (PDA), HfO_yN_z shows the lowest leakage current. It was found for both as-grown and annealed structures that Poole-Frenkel conduction is dominant at low field while Fowler-Nordheim tunneling in high field. Spectroscopic ellipsometry measurement revealed that the PDA process decreases the bandgap of the dielectric layers. We found that a decreasing of peak intensity in the middle HfO_yN_z layer as measured by Tof-SIMS may suggest the movement of N toward the interface region between the HfO_yN_z layer and the Si substrate during the annealing process.     

Resistive switching characteristics of ultra-thin TiOx

We investigated the resistive switching characteristics of Ir/TiO_x/TiN structure with 50 nm active area. We successfully formed ultra-thin (4 nm) TiO_x active layer using oxidation process of TiN BE, which was confirmed by X-ray Photoelectron Spectroscopy (XPS) depth profiling. Compared to large area device (50 μm), which shows only ohmic behavior, 250 and 50 nm devices show very stable resistive switching characteristics. Due to the formation and rupture of oxygen vacancies induced conductive filament at Ir and TiO_x interface, bipolar resistive switching was occurred. We obtained excellent switching endurance up to 10⁶ times with 100 ns pulse and negligible degradation of each resistance state at 85 °C up to 10⁴ s.     

Microstructure and stress in high-k Hf-Y-O thin films

We investigated the microstructure and the stress of high-k Hf-Y-O thin films deposited by atomic layer deposition (ALD). These hafnium oxide based films with a thickness of 5-60 nm stabilized in crystal structure with yttrium oxide by alternating the Hf- or Y-containing metal precursor during deposition. The microstructure was investigated by XRD and TEM in dependence of substrate and deposition temperature. The film stress was monitored during thermal cycles up to 500 °C using the substrate curvature method on (1 0 0)-Si wafer material with or without 10 nm TiN bottom electrode as well as on fused silica. It was observed that crystallinity and phases are depending on deposition temperature and film thickness. During thermal treatment the films crystallize depending on deposition temperature, yttrium content and substrate material at different temperatures. Crystallization of the films depends strongly on yttrium content. The highest reduction of 720 MPa was observed for films deposited with a Hf:Y cycle ratio of 10:1 where 6.2% of all metal atoms are replaced by yttrium. These Hf-Y-O films also show the highest k-value of 29 and have the smallest thermal expansion coefficient mismatch to TiN electrodes. Therefore we conclude that Hf-Y-O films are candidates for application in next generations of microelectronic MIM-capacitor devices or metal gate transistor technology.     

Performance of current mirror with high-k gate dielectrics

This work compares the performance of the basic current mirror topology by using two different materials for gate dielectrics, the conventional SiON and an Hf-based high-k dielectrics. The impact of gate leakage and of channel length modulation on the basic current mirror operation is described. It is shown that in the case of SiON gate dielectrics with an equivalent oxide thickness (EOT) of 1.4 nm, it is not possible to find a value for the channel length which allows a good trade-off to be obtained while minimizing the gate leakage and reducing the channel length modulation. On the other hand, the study demonstrates that in the case of HfSiON gate dielectrics with similar EOT, appropriate L values can be found obtaining very high output impedance current sources with reduced power consumption owing to low leakage and most of all with better parameter predictability.     

Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1−x films by surface sol-gel method and reaction-anneal treatment

Hafnium oxide (HfO₂) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl₄) source by surface sol-gel process, then ultrathin (HfO₂)_x(SiO₂)_1−x films were fabricated due to the reaction of SiO₂ layer with HfO₂ under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO₂ and pre-grown SiO₂ layer, and the composition was Hf_0.52Si_0.48O₂ under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO₂)_x(SiO₂)_1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment.     

Influence of temperature and drain current on source and drain resistances in AlGaN/GaN HEMTs

The behavior of source and drain resistances (R_S and R_D) has been studied for a wide range of drain currents at ambient temperatures from 150 to 500 K. Both parasitic resistances show an important increase as temperature rises, directly related to the reduction in the electron mobility. High drain currents also produce a non-linear increment of R_S and R_D, once the space-charge limited current is exceeded. Both temperature and drain current mechanisms have been modeled together by means of a simple equation, and a good agreement between simulations and measurements is found. Non-linear R_S and R_D allow a more accurate extraction of the intrinsic parameters, especially in the high drain current range. The use of variable parasitic resistances instead of their usually assumed constant values reveals higher intrinsic transconductance (g_m,int) and C_gs.     

Porosity generation using hydrogen plasma assisted thermal curing for ultra low k material

In this work H₂ plasma curing is studied to appreciate hydrogen species impact on porogen removal efficiency and transformation occurring within the porous SiOCH structure. The investigation is done by comparing H₂ plasma with other curing treatment (UV curing). H₂ plasma curing shows a benefit in term of porogen removal and can be considered as a fast process as only few minutes are required to decompose the C-H bonds and create the porosity. However, longer treatment reveals carbon depletion by Si-CH₃ decrease and porosity collapse through the shrinkage enhancement. Plasma treatments lead also to the creation of SiH bonds which could serve as a hydrogen radical generator when the film is electrically stressed. The leakage current and breakdown voltage values are then affected by these hydrogen radicals, which can contribute in the electrical conduction. The H₂ process allows obtaining films with a dielectric constant below 2.4. This process shows encouraging results comparing with the k = 2.35 obtained with UV curing technology.     

An investigation of ultra low-k dielectrics with high thermal stability for integration in memory devices

For the PMD in a next generation memory device, two kinds of newly developed ultra low-k MSQ materials (k < 2.0) are shown to have good thermal stability, up to 600 °C, while the investigated HSQ (k = 2.9) material degraded at temperatures >500 °C. The thermal stability of the low-k MSQ is correlated with the amount of Si-X (X = H or CH₃), the ratio of Si-X to Si-O, and the structure of the Si-O bonds. With PE-SiO₂ and PE-SiN capping on HSQ, the k-value of  < 3.0 can be maintained up to 800 °C due to Si-H remaining in the film. Similarly, PE-SiC and PE-SiO₂ capping increases the k-value degradation onset temperature of the MSQ materials by 50 °C.     

Ge volatilization products in high-k gate dielectrics

GeO molecules are often emitted by Ge substrates under high-temperature annealing and, in the case of gate stacks, they diffuse through high-k oxides. Here we use first-principles quantum-mechanical calculations to probe the stability of these impurities in La₂O₃ and HfO₂ and their effect on the electronic properties of the host systems. We find that the GeO species introduce several different levels inside the energy band gaps of La₂O₃ and HfO₂. As a result, the impurities may act as charge carrier traps. Hydrogenation of the GeO defects modifies the position and numbers of gap states, but does not eliminate the carrier trap levels completely. The results suggest a possible role of Ge volatilization in enhancing leakage currents and degradation in high-k gate stacks of Ge-based devices.     

Materials characterization of WNxCy, WNx and WCx films for advanced barriers

A ternary WN_xC_y system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 °C in a process sequence using tungsten hexafluoride (WF₆), triethyl borane (TEB) and ammonia (NH₃) as precursors. The WC_x layers were deposited by a novel ALD process at a process temperature of 250 °C. The WN_x layers were deposited at 375 °C using bis(tert-butylimido)-bis-(dimethylamido)tungsten (^tBuN)₂(Me₂N)₂W (imido-amido) and NH₃ as precursors. WN_x grows faster on plasma enhanced chemical vapor deposition (PECVD) oxide than WC_x does on chemical oxide. WN_xC_y grows better on PECVD oxide than on thermal oxide, which is opposite of what is seen for WN_x. In the case of the ternary WN_xC_y system, the scalability towards thinner layers and galvanic corrosion behavior are disadvantages for the incorporation of the layer into Cu interconnects. ALD WC_x based barriers have a low resistivity, but galvanic corrosion in a model slurry solution of 15% peroxide (H₂O₂) is a potential problem. Higher resistivity values are determined for the binary WN_x layers. WN_x shows a constant composition and density throughout the layer.     

Evaluating k-values for low-k materials after damascene integration: Method and results

This work discusses a method for measuring k-values of low-k films after integration in damascene structures. The experimental results are obtained from 90 nm ½ pitch single damascene structures on low-k materials with intrinsic k-values ranging between 2.2 and 3. The measurement technique is discussed in detail with a focus on the accuracy, limitation of the method, impact of low-k damage and applicability for smaller dimensions.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

近红外SPAD标定的偏压偏流控制系统研究

针对近红外1550 nm单光子雪崩光电二极管(single photon avalanche photodiode,SPAD)的特性,为精确测量其参数性能,设计了高精度偏压控制电路及偏流检测电路系统。该系统以FPGA为控制核心,通过上位机软件下发偏压控制参数,采用高精度器件并经过电压放大滤波等操作实现对SPAD偏压的精准控制。采用电流检测器件,通过恒流源补偿的方案将偏流值检测转换成电压值的检测,利用模数转换器件进行电压采集上传给FPGA,上位机软件通过数据拟合推导得到最终的偏流值。通过实验测试验证了电路的可行性,偏压控制精度小于30 mV,输出电压纹波小于100 mV,偏流检测上传稳定。该偏压控制及偏流检测系统设计具有结构简单、偏压设置精度高、超低纹波、控制灵活的优点,已经应用于近红外1550 nm SPAD标定系统中,工作稳定可靠。     

A new cell structure with a spread source/drain (SSD) MOSFET and acylindrical capacitor for 64-Mb DRAM's

A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs