Gentle FUSI NiSi metal gate process for high-k dielectric screening

In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).     

Characteristics of metal-oxide-semiconductor (MOS) device with Er metal gate on SiO2 film

We have investigated the structural and electrical properties of metal-oxide-semiconductor (MOS) devices with Er metal gate on SiO₂ film. Rapid thermal annealing (RTA) process leads to the formation of a high-k Er-silicate gate dielectric. The in situ high-voltage electron microscopy (HVEM) results show that thermally driven Er diffusion is responsible for the decrease in equivalent oxide thickness (EOT) with an increase in annealing temperature. The effective work function (Φ_m,eff) of Er metal gate, extracted from the relations of EOT versus flat-band voltage (V_FB), is calculated to be ∼2.86 eV.     

Fully strained Si0.75Ge0.25 epitaxial films with HfSiO gate dielectrics for high mobility channel metal-oxide semiconductor devices

The authors report on fully strained Si_0.75Ge_0.25 metal-oxide-semiconductor capacitors with HfSiO₂ high-k gate dielectric and TaN metal gate fabricated on Si substrates. Fully strained Si_0.75Ge_0.25 films are directly grown on Si substrates below the critical thickness. HfSiO₂ high-k gate dielectrics exhibit an equivalent oxide thickness of 13-18 Å with a permittivity of 17.7 and gate leakage current density lower than SiO₂ gate oxides by >100×. Interfacial oxide of the HfSiO₂/Si_0.75Ge_0.25 stack consists primarily of SiO₂ with a small amount of Ge and Hf. High performance SiGe field effect transistors are highly manufacturable with excellent electrical characteristics afforded by the fully strained HfSiO₂/SiGe gate stack.     

Process damage-free damascene metal gate technology for gentle integration of epitaxially grown high-k

This paper presents the first successful attempt to integrate crystalline high-k gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1.9 nm are discussed and compared with devices with rare-earth gate dielectrics fabricated previously in a conventional CMOS process.     

HfAlOx high-k gate dielectric on SiGe: Interfacial reaction, energy-band alignment, and charge trapping properties

Ultra thin HfAlO_x high-k gate dielectric has been deposited directly on Si_1−xGe_x by RF sputter deposition. The interfacial chemical structure and energy-band discontinuities were studied by using X-ray photoelectron spectroscopy (XPS), time of flight secondary ion mass spectroscopy (TOF-SIMS) and electrical measurements. It is found that the sputtered deposited HfAlO_x gate dielectric on SiGe exhibits excellent electrical properties with low interface state density, hysteresis voltage, and frequency dispersion. The effective valence and conduction band offsets between HfAlO_x (E_g = 6.2 eV) and Si_1−xGe_x (E_g = 1.04 eV) were found to be 3.11 eV and 2.05 eV, respectively. In addition, the charge trapping properties of HfAlO_x/SiGe gate stacks were characterized by constant voltage stressing (CVS).     

Studies on dielectric relaxation and defect generation for reliability assessments in ultrathin high-k gate dielectrics on Ge

In this work, we present the results of dielectric relaxation and defect generation kinetics towards reliability assessments for Zr-based high-k gate dielectrics on p-Ge (1 0 0). Zirconium tetratert butoxide (ZTB) was used as an organometallic source for the deposition of ultra thin (∼14 nm) ZrO₂ films on p-Ge (1 0 0) substrates. It is observed that the presence of an ultra thin lossy GeO_x interfacial layer between the deposited high-k film and the substrate, results in frequency dependent capacitance-voltage (C-V) characteristics and a high interface state density (∼10¹² cm⁻² eV⁻¹). Use of nitrogen engineering to convert the lossy GeO_x interfacial layer to its oxynitride is found to improve the electrical properties. Magnetic resonance studies have been performed to study the chemical nature of electrically active defects responsible for trapping and reliability concerns in high-k/Ge systems. The effect of transient response and dielectric relaxation in nitridation processes has been investigated under high voltage pulse stressing. The stress-induced trap charge density and its spatial distribution are reported. Charge trapping/detrapping of stacked layers under dynamic current stresses was studied under different fluences (−10 mA cm⁻² to −50 mA cm⁻²). Charge trapping characteristics of MIS structures (Al/ZrO₂/GeO_x/Ge and Al/ZrO₂/GeO_xN_y/Ge) have been investigated by applying pulsed unipolar (peak value - 10 V) stress having 50% duty-cycle square voltage wave (1 Hz-10 kHz) to the gate electrode.     

Comparison of radio frequency physical vapor deposition target material used for LaOx cap layer deposition in 32 nm NMOSFETs

The MOSFET gate length reduction down to 32 nm requires the introduction of a metal gate and a high-K dielectric as gate stack, both stable at high temperature. Here we use a nanometric layer of Lanthanum to shift the device threshold voltage from 500 mV. Because this layer plays a key role in the device performance and strongly depends on its deposition process, we have compared two LaO_x deposition methods in terms of physical properties and influence on electrical NMOS device parameters. Chemical characterizations have shown a different oxidization state according to Lanthanum thickness deposited. It has been related to threshold voltage shift and gate leakage current variations on NMOS transistors. Furthermore mobility extractions have shown that Lanthanum is a cause of mobility degradation.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

Role of lanthanum in the gate stack: Co-sputtered TaLaN metal gates on Hf-based dielectrics

We examine the characteristics of TaLaN metal gates in direct contact with HfO₂ dielectric, in particular focusing on the effect of La in the gate stack for NMOS applications. Effective work functions (EWF) and vacuum work functions (WF) are measured as a function of lanthanum content in TaLaN without any intentional heating using X-ray photoelectron spectroscopy, U-V photoelectron spectroscopy, and electrical C-V measurements. We find that the addition of lanthanum to tantalum nitride lowered both the EWF and the WF of the metal gate by ∼0.2 eV and ∼0.9 eV, respectively. Furthermore, XPS indicates that lanthanum in TaLaN at the interface with HfO₂ is primarily bonded to nitrogen rather than oxygen and not reacting with the dielectric.     

The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

Ruthenium oxide metal nanocrystal capacitors with high-κ dielectric tunneling barriers for nanoscale nonvolatile memory device applications

The ruthenium oxide metal nanocrystals embedded in high-κ HfO₂/Al₂O₃ dielectric tunneling barriers prepared by atomic layer deposition in the n-Si/SiO₂/HfO₂/ruthenium oxide (RuO_x)/Al₂O₃/Pt memory capacitors with a small equivalent oxide thickness of 8.6 ± 0.5 nm have been investigated. The RuO_x metal nanocrystals in a memory capacitor structure observed by high-resolution transmission electron microscopy show a small average diameter of ∼7 nm with high-density of >1.0 × 10¹²/cm² and thickness of ∼3 nm. The ruthenium oxide nanocrystals composed with RuO₂ and RuO₃ elements are confirmed by X-ray photoelectron spectroscopy. The enhanced memory characteristics such as a large memory window of ΔV ≈ 12.2 V at a sweeping gate voltage of ±10 V and ΔV ≈ 5.2 V at a small sweeping gate voltage of ±5 V, highly uniform and reproducible, a large electron (or hole) storage density of ∼1 × 10¹³/cm², low charge loss of <7% (ΔV ≈ 4.2 V) after 1 × 10⁴ s of retention time are observed due to the formation of RuO_x nanocrystals after the annealing treatment and design of the memory structure. The charge storage in the RuO_x nanocrystals under a small voltage operation (∼5 V) is due to the modified Fowler-Nordheim tunneling mechanism. This memory structure can be useful for future nanoscale nonvolatile memory device applications.     

High-k TixSi1−xO2 thin films prepared by co-sputtering method

We report on high-k Ti_xSi_1−xO₂ thin films prepared by RF magnetron co-sputtering using TiO₂ and SiO₂ targets at room temperature. The Ti_xSi_1−xO₂ thin films exhibited an amorphous structure with nanocrystalline grains of 3-30 nm having no interfacial layers. The XPS analyses indicate that stoichiometric TiO₂ phases in the Ti_xSi_1−xO₂ films increased due to stronger Ti-O bond with increasing TiO₂ RF powers. In addition, the electrical properties of the Ti_xSi_1−xO₂ films became better with increasing TiO₂ RF powers, from which the maximum value of the dielectric constant was estimated to be ∼30 for the samples with TiO₂ RF powers of 200 and 250 W. The transmittance of the Ti_xSi_1−xO₂ films was above 95% with optical bandgap energies of 4.1-4.2 eV. These results demonstrate a potential that the Ti_xSi_1−xO₂ thin films were applied to a high-k gate dielectric in transparent thin film transistors as well as metal-oxide-semiconductor field-effect transistors.     

Lanthanum diffusion in the TiN/LaOx/HfSiO/SiO2/Si stack

Band edge Complementary Metal Oxide Semiconductor (CMOS) devices are obtained by insertion of a thin LaO_x layer between the high-k (HfSiO) and metal gate (TiN). High temperature post deposition anneal induces Lanthanum diffusion across the HfSiO towards the SiO₂ interfacial layer, as shown by Time of Flight Secondary Ions Mass Spectroscopy (ToF-SIMS) and Atom Probe Tomography (APT). Fourier Transform Infrared Spectroscopy in Attenuated Total Reflexion mode (ATR-FTIR) shows the formation of La-O-Si bonds at the high-k/SiO₂ interface. Soft X-ray Photoelectron Spectroscopy (S-XPS) is performed after partial removal of the TiN gate. Results confirm La diffusion and changes in the La chemical environment.     

Microstructure and stress in high-k Hf-Y-O thin films

We investigated the microstructure and the stress of high-k Hf-Y-O thin films deposited by atomic layer deposition (ALD). These hafnium oxide based films with a thickness of 5-60 nm stabilized in crystal structure with yttrium oxide by alternating the Hf- or Y-containing metal precursor during deposition. The microstructure was investigated by XRD and TEM in dependence of substrate and deposition temperature. The film stress was monitored during thermal cycles up to 500 °C using the substrate curvature method on (1 0 0)-Si wafer material with or without 10 nm TiN bottom electrode as well as on fused silica. It was observed that crystallinity and phases are depending on deposition temperature and film thickness. During thermal treatment the films crystallize depending on deposition temperature, yttrium content and substrate material at different temperatures. Crystallization of the films depends strongly on yttrium content. The highest reduction of 720 MPa was observed for films deposited with a Hf:Y cycle ratio of 10:1 where 6.2% of all metal atoms are replaced by yttrium. These Hf-Y-O films also show the highest k-value of 29 and have the smallest thermal expansion coefficient mismatch to TiN electrodes. Therefore we conclude that Hf-Y-O films are candidates for application in next generations of microelectronic MIM-capacitor devices or metal gate transistor technology.     

Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes

We present a novel metal gate/high-k complementary metal–oxide–semiconductor (CMOS) integration scheme with symmetric and low threshold voltage (V_th) for both n-channel (nMOSFET) and p-channel (pMOSFET) metal–oxide–semiconductor field-effect transistors. The workfunction of pMOSFET is modulated by oxygen in-diffusion (‘oxygenation’) through the titanium nitride metal gate without equivalent oxide thickness (EOT) degradation. A significant V_th improvement by 420 mV and an aggressively scaled capacitance equivalent thickness under channel inversion (T_inv) of 1.3 nm is achieved for the pFET by using a replacement process in conjunction with optimized oxygenation process. Immunity of nMOSFET against oxygenation process is demonstrated.     

Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics

Schottky barrier SOI-MOSFETs incorporating a La₂O₃/ZrO₂ high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10¹¹ eV⁻¹ cm⁻², a low subthreshold slope of 70-80 mV/decade, and an I_ON/I_OFF current ratio greater than 2 × 10⁶ are obtained.     

Rare earth-based high-k materials for non-volatile memory applications

A study of a La-based high-k oxide to be employed as active dielectric in future scaled memory devices is presented. The focus will be held on La_xZr_1−xO_2−δ (x = 0.25) compound. In order to allow the integration of this material, its chemical interaction with an Al₂O₃ cap layer has been studied. Moreover, the electrical characteristics of these materials have been evaluated integrating them in capacitor structures. The rare earth-based ternary oxide is demonstrated to be a promising candidate for future non-volatile memory devices based on charge trapping structure.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

ALD of LaHfOx nano-laminates for high-κ gate dielectric applications

Electrical properties and thermal stability of LaHfO_x nano-laminate films deposited on Si substrates by atomic layer deposition (ALD) have been investigated for future high-κ gate dielectric applications. A novel La precursor, tris(N,N′-diisopropylformamidinato) lanthanum [La(ⁱPrfAMD)₃], was employed in conjunction with conventional tetrakis-(ethylmethyl)amido Hf (TEMA Hf) and water (H₂O). The capacitance-voltage curves of the metal oxide semiconductor capacitors (MOSCAPs) showed negligible hysteresis and frequency dispersion, indicating minimal deterioration of the interface and bulk properties. A systematic shift in the flat-band voltage (V_fb) was observed with respect to the change in structure of nano-laminate stacks as well as La₂O₃ to HfO₂ content in the films. The EOTs obtained were in the range of ∼1.23-1.5 nm with leakage current densities of ∼1.3 × 10⁻⁸ A/cm² to 1.3 × 10⁻⁵ A/cm² at V_fb − 1 V. In addition, the films with a higher content of La₂O₃ remained amorphous up to 950 °C indicating very good thermal stability, whereas the HfO₂ rich films crystallized at lower temperatures.