Improvement in threshold voltage control by minimizing boronpenetration in a LV-GCMOS technology

Maintaining tight threshold voltage (V_T) control for a low-voltage CMOS process is critical due to the large impact of V_T on circuit performance at low power supply voltages. In this paper, PMOS V_T was shown to be sensitive to poly gate thickness and BF₂⁺ source/drain implant energy. This data helped identify boron penetration as a prime contributor to PMOS threshold voltage variation. SIMS measurements were used to investigate boron diffusion through the poly gate at various stages in the process flow. These SIMS profiles pointed to the low-temperature thermal cycle of the nitride spacer deposition as a key step which influenced the amount of boron penetration and thus the final device threshold voltage. Experimental evidence shows that the temperature gradient across the nitride spacer deposition furnace causes a variable amount of boron penetration resulting in a large variation in PMOS V_T. We adopted a process flow change which virtually eliminated boron penetration and significantly reduced the sensitivity of the devices to manufacturing variations. Threshold voltage variation was reduced by a factor of two     

Thickness dependence of boron penetration through O2 and N2O-grown gate oxides and its impact on threshold voltagevariation

We report on a quantitative study of boron penetration from p⁺ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O₂ or N₂O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, N_B, for thicknesses other than those measured. We find that the minimum t_ox required to inhibit boron penetration is always 2-4 nm less when N₂O-grown gate oxides are used in place of O₂- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on t_ox, incremental variations in oxide thickness result in a large variation in N_B , leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10¹¹ cm^-2     

High-performance embedded SOI DRAM architecture for the low-powersupply

This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can he relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage, Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM     

A statistical methodology as applied to a 256 Mbit DRAM passtransistor design

We present a novel design for manufacturing (DFM) methodology that has been applied to the design of a pass transistor for 256 Mbit DRAM. The design inputs that include gate oxide thickness, which limits the booted wordline voltage, the threshold voltage adjust implant, and the substrate bias voltage, for different channel lengths, are optimized to meet the constraints on performance, reliability, and robustness against manufacturing variations. The problems associated with applying conventional DFM techniques are discussed and a new methodology based on “margins” is presented. The results pertaining to the optimized DRAM pass transistor design for a power supply voltage V_cc=2.5 V are presented,     

Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

A novel CMOS fabrication process with a dual gate oxide (NDGO, thin oxide 5.0 nm, thick oxide 7.8 nm) and a shallow trench isolation (STI) top-edge rounded by a pad oxide undercut was developed for a 256M-bit mobile dynamic random access memory (DRAM) with V_D=1.8 V. We present a comprehensive study on the I–V characteristics and the long-term reliability of CMOSFET fabricated by NDGO process, and compared these characteristics with those of conventional single gate oxide transistors with a gate oxide thickness 5.0–7.5 nm. While thin oxide nMOSFET have a threshold voltage of nMOSFET (V_thn) of between 0.70 and 0.72 V and a saturation current (I_DSAT) of between 280 and 300 μA/μm, thick oxide nMOSFET have a V_thn of between 0.85 and 0.90 V and an I_DSAT of between 160 and 200 μA/μm in NDGO process due to a difference in the gate oxide thickness at similar boron doses. A 10 year lifetime of thick oxide cell transistors is projected for a V_g=8.9 V due to an electrical stress release at the STI top-edge round improved by the pad oxide undercut. The hot carrier lifetime and hot electron induced punchthrough also showed good characteristics. Consequently, this NDGO process is able to provide a reliable transistor performance for a 256M-bit mobile DRAM operating at low power.     

Growth Behavior of Cubic Boron Nitride Films in a Two‐Step Process: Changing Bias Voltage,Gas Composition,and Substrate Temperature

In the deposition of cubic boron nitride (cBN) films by DC‐bias‐assisted DC jet chemical vapor deposition in an Ar–N₂–BF₃–H₂ gas system, the balance between growth and etching and its relation to the deposition conditions were investigated. A two‐step process was designed to optimize the nucleation and growth separately, and a critical bias voltage for the growth of cBN after nucleation was observed. It was found that etching occurred when the bias voltage was below this critical value. Under optimized conditions, the crystallinity and crystal size of the cBN films were improved during the second step. Furthermore, cBN films showing clear crystal facets were obtained.     

Anomalous narrow channel effect in trench-isolated buried-channelp-MOSFET's

An anomalous threshold voltage dependence on channel width measured on 0.25 μm groundrule trench-isolated buried-channel p-MOSFET's is reported here. As the channel width is reduced, the magnitude of the threshold voltage first decreases before the onset of the expected sharp rise in Vt for widths narrower than 0.4 μm. Modeling shows that a “boron puddle” is created near the trench bounded edge as a result of transient enhanced diffusion (TED) during the gate oxidation step. TED is governed by interstitials produced by a deep phosphorus implant, used for latchup suppression, diffusing towards the trench sidewall and top surface of the device. The presence of the “boron puddle” imposes a penalty on the off-current of narrow devices. A solution for minimizing the “boron puddle” is demonstrated with simulations, confirmed by measurements     

Threshold voltage dependence of LOCOS-isolated thin-film SOINMOSFET on buried oxide thickness

Effects of buried oxide thickness on short-channel effect of LOCOS-isolated thin-film SOI n-MOSFETs have been investigated. Devices fabricated on SOI substrate with thin (100 nm) buried oxide have smaller roll-off of threshold voltage than those fabricated on SOI substrate with thick (400 nm) buried oxide. This is caused by a different boron concentration at the silicon film that results from the difference of stress with the buried oxide thickness. In the case of thin buried oxide, higher volumetric expansion of the field oxide causes higher stress at the interface between the silicon film and the surrounding oxide, including field and buried oxide, which prevents boron atoms from diffusing beyond the interface     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

SiGe HBT基区结构的优化对欧拉电压的影响

欧拉电压是SiGe HBT一项重要的直流参数,受到基区结构(如Ge组分)的影响。研究发现,高温过程会导致硼的外扩散,从而影响异质结的位置,使欧拉电压受到影响。实验发现,通过优化基区结构,加厚CB结处i-SiGe厚度,可获得VA=520 V,βVA=164,320 V的SiGe HBT。     

Reduction of the parasitic charge generation during silicon nitride deposition in a LOCOS isolation without field implant

MOS integrated circuits use the Local oxidation of silicon to isolate laterally adjacent devices (LOCOS isolation). The insulation structure is typically formed by a semiconductor region doped by ion implantation (field implant) and covered by a thick thermal oxide (field oxide). Other insulators (plasma enhanced chemical vapor deposited (PECVD) silicon oxides and LPCVD silicon nitride) and metal interconnection are subsequently deposited on the field oxide. The ion implant together with the thick insulator ensure a high threshold voltage value of the parasitic MOS transistor formed by source and drain of the adjacent active devices and by the insulator/interconnection gate.However, economical purpose leads to the extension of the application field of lower cost technology, addressing the problem of LOCOS isolation without any field implant. As already shown in a previous work [Fay JL, Beluch J, Allirand L, Brosset D, Despax B, Bafleur M, Sarrabayrose G. Jpn J Appl Phys 38(9A):5012–7] for inter-layer dielectric applications, our PECVD oxides suffer from excessive concentration of fixed positive charges brought about by the silicon nitride deposition, and causing the N-channel field threshold voltage to decrease.Characterization reveals that these charges are generated by diffusion of species coming from the gas phase during the silicon nitride process. These generated charges can be reduced either by increasing the O₂/tetra-ethyl orthosilicate ratio or by doping the oxide with boron and phosphorus. To avoid diffusion and generation of charges, we minimized the thermal budget using a PECVD silicon nitride. With this process, we have achieved a high threshold voltage and an acceptably low leakage current of the NMOS parasitic transistor.     

Anomalous reverse short-channel effect in p+ polysilicongated P-channel MOSFET

The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p⁺ poly-gate PMOSFET's. The RSCE is found to be more significant as the boron penetration becomes more severe. The RSCE is significant in BF ₂ doped poly-gated MOS devices and is alleviated in buffered poly-gated MOS devices. Fluorine enhanced boron diffusion in the gate oxide during high temperature process is believed to account for the RSCE, which is also confirmed by using a two-dimensional process simulator     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature     

Temperature-compensation circuit techniques for high-density CMOSDRAMs

Temperature-compensation circuit techniques are presented for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The above-mentioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM process. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/°C, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/°C. As a result, a 6.5-ns faster RAS access time and improved latchup immunity have been achieved, compared with conventional circuit techniques     

Novel Method for Nondestructive Body Effect Measurement in Dynamic Random Access Memory

Body effect is a key characteristic of a dynamic random access memory (DRAM) cell transistor. The conventional method uses a test element structure or nano-probe equipment for body effect measurements. However, the test element structure measurement is inaccurate because the structure is located outside the DRAM chip. Additionally, the nano-probe destroys the chip while measuring the body effect in the chip. Therefore, we developed a novel nondestructive method to measure the body effect in the DRAM. This method uses a memory bitmap test system. The test system was originally a device that determines pass or fail of the cells. However, it was modified to extract the gate voltage that causes the failure due to a cell transistor leakage current. Because the leakage current is correlated to the threshold voltage, this gate voltage is a relative threshold voltage. The body effect was obtained by measuring the relative threshold voltage under different body biases. After confirming the method in a single cell, we simplified the method for a mass cell measurement. Two relative threshold voltages for each body bias were used for a fast and simple test. The mass measurement method could obtain 8196 body cell effects within 2 min. The results of the newly developed method were the same as that of the conventional test element structure measurement.     

A methodology for the implementation of MOSFETs with a high-k dielectric gate material on the design of 90 nm technology circuits

Up to date, MOSFETs have been made through well established techniques that use SiO₂ as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO₂ as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO₂ is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO₂ devices. A cell layout is provided and the DRAM circuit characteristics are also presented.     

Control of boron diffusion in polysilicon for constructing overlapping polysilicon gate charge-coupled devices

The diffusion coefficient of boron having values significantly different in silicon and silicon dioxide has been used to control the doping of boron impurity in intrinsic polysilicon deposited over the gate oxide. The method reduces the possibility of doping gate oxide while diffusing boron in polysilicon. Using the method, silicon gate p-MOSFETS and twenty bit photo-sensor, four phase, double overlapping polysilicon gate surface channel charge-coupled devices have been constructed with a transfer efficiency of 0.9990. The measured values of the threshold voltage of MOSFETS are in close agreement with their corresponding calculated values.     

Threshold shift of p-channel transistors by boron implantation and the C-V characteristics of the corresponding mos structures

Short p-channel transistors for scaled CMOS circuits are fabricated using double implantations with phosphorus and boron ions. Deep phosphorus channel implantation is required for increasing the channel punch-through voltage, while shallow boron implantation is used to adjust the device threshold voltage for p-channel transistors with n + poly as the gate electrode. The effect of the boron dose and the sub-surface junction depth on the device characteristics, especiallly the C?V characteristics, is investigated.The capacitance dispersion with respect to frequency, which is observed for MOS diodes with large boron dose or deep boron depth, will be discussed in detail. This phenomenon is explained by the majority carrier modulation at the sub-surface junction associated with the boron implanted channel. The effect of the non-uniform phosphorus channel doping on the measured C?V characteristics will also be examined. The technique of the one-dimensional calculation of the channel potential distribution is presented to show the correlation of the implanted boron dose and the observed abnormal C?V characteristics.     

Suppression of boron penetration in p-channel MOSFETs usingpolycrystalline Si1-x-yGexCy gatelayers

Boron penetration through thin gate oxides in p-channel MOSFETs with heavily boron-doped gates causes undesirable positive threshold voltage shifts. P-channel MOSFETs with polycrystalline Si_1-x-yGe_xC_y gate layers at the gate-oxide interface show substantially reduced boron penetration and increased threshold voltage stability compared to devices with all poly Si gates or with poly Si_1-xGe gate layers. Boron accumulates in the poly Si_1-x-yGe_xC_y layers in the gate, with less boron entering the gate oxide and substrate. The boron in the poly Si_1-x-yGe_xC_y appears to be electrically active, providing similar device performance compared to the poly Si or poly Si_1-xGe_x gated devices     

Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface

The impact of halo implantation angle on the low-frequency noise of short channel n-MOSFET is reported. The low-frequency noise is degraded with larger tilt angle for the same implant dose and energy. The higher dose/energy of the halo implant with larger tilt angle further enhances the degradation of low-frequency noise. The larger halo angle introduces non-uniform doping distribution and creates the non-uniform threshold voltage along the channel. Additional traps can be created near the oxide/semiconductor interface due to boron pileup due to larger tilt angle. A quantitative analysis supported by experimental results confirm that the degradation of 1/f noise is due to the combined effect of non-uniformity in threshold voltage along the channel and the creation of extra trap charges near the oxide-semiconductor interface (near-interfacial charges).