New technique for measuring the threshold voltage in MOS devices

The present paper describes an experimental method that can be used to measure the threshold voltage in MOS devices in the form of transistors or capacitors. The proposed method is based on the detection of the non-steady-state/steady-state transition of the surface potential at the oxide–semiconductor interface of a MOS device, when it is swept from depletion to inversion regions. This detection is carried out as follows: a set of current versus gate signal frequency measurements, for different voltage amplitudes, is performed. The frequency values corresponding to the maximum measured current (optimum frequency) f_m, are read. Several gate voltage versus optimum frequencies (f_m–V_G) curves are plotted for gate voltage values ranging from 0.2 to 3 V with a 0.1 V step increment. The (f_m–V_G) curves are found to undergo an abrupt change of slope at a specific gate voltage value. The value of threshold voltage is extracted from the critical points of the former curves. Experiments have been carried out on different devices. The measured values of threshold voltage are found to be in good agreement to those obtained by the conventional I_D–V_GS and simulation methods as well as that supplied by the device manufacturer.     

Thorough analysis of quantum mechanical effects on MOS structure characteristics in threshold region

Threshold voltage shift due to quantum mechanical effects (QMEs) are studied for both n- and p-MOS structure in the paper. Subband structure and carrier distribution are formulated for both type of MOS structure in effective mass approximation. QMEs on threshold voltage shift are thoroughly analyzed based on the model. Carrier distribution in subbands for both n-MOS and p-MOS are calculated and analyzed from density-of-states point of view. Model results for n- and p-MOS structure are compared with experimental and full-band self-consistent calculation results and show good coincidence. It is proved that at least in threshold region, effective mass approximation has similar accuracy as the full-band self-consistent method to predict the influence of QMEs MOS structure characteristics.     

An accurate, analytical, and technology-mapped definition of the surface potential at threshold and a new postulate for the threshold voltage of MOSFETs

A novel approach of defining the threshold voltage for long channel MOSFETs has been presented in this paper, where it has been proposed that it corresponds to the gate-to-source voltage for which the drift and diffusion components of the total drain current become equal to each other. In order to avoid the greater computation time associated with the numerical solution of these two components, an analytical expression of the surface potential, corresponding to the threshold condition, is given here, which has the same functional form as the one proposed by Tsividis. The fuzzy parameter n, appearing in this expression of the surface potential, is expressed as a function of the substrate doping density (N_A) and the oxide thickness (t_ox). The threshold voltage values, obtained analytically from the relation between the surface potential at the threshold condition and the closed-form technology-mapped expression of the fuzzy parameter n, show an excellent match with those obtained from SILVACO simulations for a wide range of N_A and t_ox, with the maximum error being only about 4%. The comparison of the percent error values of the threshold voltage obtained from this proposed model with those obtained from the other two recently proposed methods, all with respect to SILVACO simulation results, further verifies the validity of our completely analytical, mathematically simple, and straight-forward approach, proposed in this work here.     

Mechanisms of temperature dependence of threshold voltage in high-k/metal gate transistors with different TiN thicknesses

The change in temperature coefficient of the threshold voltage (=dV_th/dT) for poly-Si/TiN/high-k gate insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) was systematically investigated with respect to various TiN thicknesses for both n- and p-channel MOSFETs. With increasing TiN thickness, dV_th/dT shifts towards negative values for both n- and p-MOSFETs. A mechanism that changes dV_th/dT, depending on TiN thickness is proposed. The main origins are the work function of TiN (Φ_TiN) and its temperature coefficient (dΦ_TiN/dT). These are revealed to change when decreasing the thickness of the TiN layer, because the crystallinity of the TiN layer is degraded for thinner films, which was confirmed by ultraviolet photoelectron spectroscopy (UPS), transmission electron microscopy (TEM) and X-ray diffraction (XRD).     

Analysis of different parameters of channel material and temperature on threshold voltage of CNTFET

Carbon nanotubes have some unique features and special properties that offer a great potential for nano-electronic devices. In this paper, we have analyzed the effect of chiral vector, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage of CNTFET over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as of MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime especially when the gate length is around 10 nm; which is quite contrary to the well known short channel effects in MOSFET. It is observed that at or below 10 nm channel length the threshold voltage increases rapidly in case of CNTFET device whereas in case of MOSFET device the threshold voltage decreases drastically.     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

不同工艺制备的GaAs MESFET阈值电压均匀性研究

分别采用离子注入隔离凹栅工艺、自隔离平面工艺、离子注入隔离平面工艺在非掺杂半绝缘 Ga As衬底上制备 MESFET,对三种工艺制备的 MESFET的阈值电压均匀性进行了研究。结果表明 ,器件工艺对 MESFET阈值电压有一定的影响 ,开展 Ga As MESFET阈值电压均匀性研究应采用适宜的工艺 ,以尽可能减少工艺引起的偏差。     

A new method for measurement of threshold voltage non-uniformity in CCD multiplexers for hybrid focal plane arrays

A new, simple and rapid method for determining threshold voltage (V_T) non-uniformity in two-dimensional CCD multiplexers (MUXs) for hybrid focal plane arrays is presented. The method is based on simple oscilloscopic measurement of non-uniformity in the output signal of CCD MUX. The non-uniformity in V_T, measured by this method, is compared with conventional current forcing method. The results of the proposed new method agree within 7.8% with the conventional method. Additionally, intrinsic non-uniformity due to processing and material variations is also measured by this method.     

特高压电容器用电极箔腐蚀工艺的研究

通过对特高压(Vfe=950V)电容器用电极箔微观形貌的理论计算,采用一次腐蚀控制孔密度和孔长度参数,二次腐蚀控制相应的孔径。研究了700～1100V特高压电极箔的两次电化学腐蚀工艺。使Vfe为950V的特高压电容器用电极箔的参数指标得到了优化:孔密度为0.116个/μm2,孔径为2.02μm,比容达到0.210×10–6F/cm2。     

Analytical 2D modeling for potential distribution and threshold voltage of the short channel fully depleted cylindrical/surrounding gate MOSFET

A two-dimensional analytical model for fully depleted cylindrical/surrounding gate MOSFET is presented. We used the evanescent mode analysis to solve the 2D Poisson's equation and to deduce analytically the surface potential and threshold voltage expressions of this device. Comparison with the other models reveals a good agreement.     

低压铝箔交流腐蚀工艺研究

考察了电解电容器用高纯铝箔在HCl-H2SO4-H3PO4混合酸体系中的交流腐蚀过程,综合配方和工艺两方面主要因素研究铝箔的交流扩面行为。结合SEM形貌分析,重点考察了前级电流密度、后级电流密度及腐蚀电量等对铝箔比容的影响,确定了最佳的低压铝箔交流腐蚀工艺,在2V化成,Cs达76×10–6F/cm2。     

N管开启电压调整注入对P－N结击穿电压的影响

为了讨论问题方便，定义了两种Ｐ－Ｎ结：“漏Ｐ－Ｎ结”和“单纯Ｐ－Ｎ结”。分析了二者击穿电压相关因素的差别，认为“漏Ｐ－Ｎ结”的击穿电压与沟道区杂质浓度密切相关。ＥＥＰＲＯＭ的研制中，要求“漏Ｐ－Ｎ结”击穿电压≥２０Ｖ，即沟道区杂质浓度要低到一定的程度，而同时又必须保证一定的开启电压，即沟道区杂质浓度要高到一定的程度。通过分析与实验，提出了解决这一矛盾的通用原则。     

低压电子铝箔耐蚀性的研究与应用

采用对比实验,研究了腐蚀工艺对低压电子铝箔耐蚀性的影响。当腐蚀溶液中w(HCl)为15%～25%、w(H2SO4)为10%～20%,温度为85℃,电流密度为0.40A/cm2,腐蚀时间为3min时,铝箔腐蚀效果最佳,其耐蚀性数值(腐蚀前后质量差值与原光箔质量之比)为0.70%～0.83%。该工艺可迅速准确地判断低压电子铝箔的耐蚀性,平均每个样品所花时间仅为26min。