Investigating Concurrent-Mode Operation of Dual-Band Class-J/J Power Amplifiers: Analysis and Design Technique

In this paper, concurrent-mode operation of dual-band PAs under simultaneous drive of two stimuli is investigated. It is shown that Class-J operation is well suited for this mode of operation as its concurrent-mode efficiency is less affected by the load reactance tuning accuracy at inter-modulation frequencies. This characteristic results in preserved efficiencies over wider bandwidths, and simplicity of intermodulation tuning network (IMTN) realization. It has been also shown that dual-band Class-J/J PA fully takes advantage of the transistor’s nonlinear output capacitance in case of simultaneously driven input by boosting the efficiency. A Class-J/J concurrent dual-band PA with IMTN is designed and implemented which operates over 1.842/2.655 GHz bands. About 40 dBm output power and efficiencies more than 70% at lower band and upper band are obtained according to the experimental results while the concurrent-mode efficiency is about 61.2%.

     

A broadband,high isolation millimeter-wave CMOS power amplifier using a transformer and transmission line matching topology

This paper presents the design and characterization of a broadband millimeter-wave PA realized in a 130 nm standard RF-CMOS process with 8-metal-layer and transistor f _T /f _MAX of 117/161 GHz. The power amplifier adopts transformer and transmission line matching topology which achieves small area of die and wide bandwidth. A new lumped transformer model is proposed to facilitate the optimization. The measured 3 dB bandwidth is 20 GHz (from 47 to 67 GHz), the measured maximum gain is about 8.6 dB, output 1 dB compression power is 9.36 dBm and consumes 90 mA current from DC supply 1.2 V. Including GSG and DC pads, the PA occupies a compact chip area of 0.318 mm², and without pads, the PA occupies 0.141 mm².     

PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit

A personal communications service/wide-band code division multiple access (PCS/W-CDMA) dual-band monolithic microwave integrated circuit (MMIC) power amplifier with a single-chip MMIC and a single-path output matching network is demonstrated by adopting a newly proposed on-chip linearizer. The linearizer is composed of the base-emitter diode of an active bias transistor and a capacitor to provide an RF short at the base node of the active bias transistor. The linearizer enhances the linearity of the power amplifier effectively for both PCS and W-CDMA bands with no additional DC power consumption, and has negligible insertion power loss with almost no increase in die area. It improves the input 1-dB gain compression point by 18.5 (20) dB and phase distortion by 6.1/spl deg/ (12.42/spl deg/) at an output power of 28 (28) dBm for the PCS (W-CDMA) band while keeping the base bias voltage of the power amplifier as designed. A PCS and W-CDMA dual-band InGaP heterojunction bipolar transistor MMIC power amplifier with single input and output and no switch for band selection is embodied by implementing the linearizer and by designing the amplifier to have broad-band characteristics. The dual-band power amplifier exhibits an output power of 30 (28.5) dBm, power-added efficiency of 39.5 % (36 %), and adjacent channel power ratio of -46 (-50) dBc at the output power of 28 (28) dBm under 3.4-V operation voltage for PCS (W-CDMA) applications.     

Switched inductor dual-band CMOS cross-coupled VCO

This letter proposes a high-performance CMOS dual-band voltage-controlled oscillator (VCO). The VCO consists of two cross-coupled VCOs coupled by a pair of switched inductors or LC resonators to vary the resonator’s inductance. A pair of nMOSFET is used to switch high- and low-frequency bands. The VCO operates at the high-band using low resonator’s inductance and the VCO operates at the low-band using large inductance. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and it can generate differential signals in the frequency range of 5.6–6.66 GHz and 4.13–4.75 and it also has comparable high output voltage swings at both low and high-frequency bands. The die area of the dual-band VCO is 0.84 × 1.1 mm². At the supply voltage of 0.75 V, the high (low)-band figure of merit is ?193.6 (?192.3) dBc/Hz.     

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values'' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices.     

1–8 GHz high efficiency single-stage travelling wave power amplifier

This paper describes a Class-A/AB wideband power amplifier that comprises of a single-stage transistor travelling wave structure in which capacitive coupling and frequency dependent lossy artificial-line are employed at the input of the active device. The proposed technique significantly enhances the amplifier’s gain-bandwidth product, input match and gain flatness performance. To ensure the amplifier delivers a predefined power to the load over its entire operating band 2-to-8 GHz a broadband load-pull technique was applied at the output of the amplifier. To avoid reduction in the amplifier’s bandwidth resulting from parasitic capacitive effects associated with the off-chip choke inductor a wideband RF choke was designed. The 1.31 × 2.93 mm² power amplifier was fabricated using 0.25 μm GaAs pHEMT MMIC process. The measurement results show that the proposed amplifier delivers an average P _sat of 29.5 dBm and P _out,1 dB of 26 dBm, and the corresponding PAE levels are 55 and 35 % for the P _sat and P _out,1 dB, respectively.     

225–255-GHz InP DHBT Frequency Tripler MMIC Using Complementary Split-Ring Resonator

In this paper, a novel design of frequency tripler monolithic microwave integrated circuit (MMIC) using complementary split-ring resonator (CSRR) is proposed based on 0.5-μm InP DHBT process. The CSRR-loaded microstrip structure is integrated in the tripler as a part of impedance matching network to suppress the fundamental harmonic, and another frequency tripler based on conventional band-pass filter is presented for comparison. The frequency tripler based on CSRR-loaded microstrip generates an output power between ?8 and ?4 dBm from 228 to 255 GHz when the input power is 6 dBm. The suppression of fundamental harmonic is better than 20 dBc at 77–82 GHz input frequency within only 0.15?×?0.15 mm² chip area of the CSRR structure on the ground layer. Compared with the frequency tripler based on band-pass filter, the tripler using CSRR-loaded microstrip obtains a similar suppression level of unwanted harmonics and higher conversion gain within a much smaller chip area. To our best knowledge, it is the first time that CSRR is used for harmonic suppression of frequency multiplier at such high frequency band.     

Design of a full-band CMOS UWB receiver and fast-hopping carrier generator for 3.1–10.6 GHz

This paper presents an interference rejection full-band UWB receiver and fast hopping carrier generator for 3.1–10.6 GHz. This receiver enables 11 bands of operation by embedding a tunable notch filter to eliminate interferers in a 5 GHz wireless local area network. The carrier generator can cover 3.1–10.6 GHz within less than 9.5 ns. The receiver, based on the proposed multi-band OFDM standard, consists of a zero-IF receive chain and required system noise figure, the receiver linearity specifications of which are discussed in this paper. It consists of a single-ended low-noise amplifier (LNA), a down-conversion mixer, a low-pass filter (LPF), and a programmable gain amplifier with an IO buffer. The LNA employs a common-gate topology of the 1st stage with dual-resonant loads, a cascade amplifier of the 2nd stage for mid-band resonance, and a tunable notch filter. The down-conversion mixer adopts a single-balanced architecture with LO cancellation. The LPF is implemented based on an active RC topology, and implements a four-stage programmable gain amplifier. The receiver dissipates 49.3 mA from a 1.8 V power supply. The average voltage conversion gain of the receiver IC is 73.5 dB, and the system noise figure is 8.4 dB. Input P1dB increases from ?36.8 dBm at 4 GHz to ?30.5 dBm at 10.3 GHz. The attenuation is 8.5 dB, which is achieved in the interference rejection band at 5.2 GHz. It occupies an area of 0.98 × 3.3 mm² including the bond pads.     

A novel full-wave rectifier/sinusoidal frequency doubler topology based on CFOAs

In this paper, a high-efficiency class-F power amplifier (PA) is designed using integration between a low voltage p-HEMT transistor and a miniaturized microstrip suppressing cell. It results in nth harmonic suppression and high power added efficiency (PAE) under low radio frequency (RF) input powers. The simulation is performed based on harmonic balance analysis. The proposed power amplifier is fabricated, and measurements results validated the simulations. The proposed power amplifier operates at 1.8 GHz with 100 MHz bandwidth and an average PAE of 71.1%, with very low drain voltage of 2 V. At fundamental frequency of 1.8 GHz, the maximum measured PAE is 73.5% at about 12 dBm RF input power. The maximum output power and gain are 23.4 and 17.5 dBm in RF input power ranges of 0–12 dBm, respectively. The fabricated class-F PA with such characteristics can be used for power amplifications in wireless transmitters such as 4G (4th generation)-LTE (long term evolution) communication systems.     

基于PIN开关的可重构双波段功率放大器设计

为满足5G通信中多标准、多模式系统对功率放大器的需求,提出了一种新型的可重构双波段匹配电路结构.首先,在输出匹配网络中加入分布式PIN开关,通过开关的闭合与断开实现两个双波段输出匹配电路的良好匹配;然后,基于带通滤波器理论设计的宽带输入匹配网络,能够实现1.5～2.5 GHz频段内的良好匹配.为验证方法的有效性,采用C...     

Design of a capacitor cross-coupled dual-band LNA with switched current-reuse technique

This paper presents the design of a 2.5/3.5-GHz dual-band low-power and low-noise CMOS amplifier (LNA), which uses the capacitor cross-coupling technique and current-reuse method with four switches. The proposed LNA uses a single RF block and a broadband input stage, which is a key aspect for the easy reconfiguration of a dual-band LNA. Switching at the inter-stage and output allows for the selection of a different standard. The dual-band LNA attenuates the undesired interference of a broadband gain response circuit, which allows the linearity of the amplifier to be improved. The capacitor cross-coupled gm-boosting method improves the NF and reduces the current consumption. The proposed LNA employs a current-reused structure to decrease the total power consumption. The inter-stage and output switched resonators switch the LNA between the 2.5-GHz and 3.5-GHz bands. The proposed dual-band LNA optimises power consumption by the securing gain, noise figure and linearity. The simulated performance reveals gains of 16.7 dB and 19.6 dB, and noise figures of 3.04 dB and 2.63 dB at the two frequency bands, respectively. The linearity parameters of IIP3 are ?5.7 dBm at 2.5 GHz and ?9.7 dBm at 3.5 GHz. The proposed dual-band LNA consumes 5.6 mW from a 1.8 V power supply.     

A high efficiency transmitter and receiver for magnetic resonant wireless battery charging system in 0.35 μm BCD

This paper presents a transmitter and receiver for magnetic resonant wireless battery charging system. In the receiver, a wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, 1-stage voltage multiplier or 2-stage voltage multiplier mode. As a result, a rectified DC voltage is output from 7.5 to 19 V for an input AC voltage of 5–20 V. In the transmitter, a class-E power amplifier (PA) with an automatic power control loop and load compensation circuit is proposed to improve the power efficiency. The transmitted power is controlled by adjusting the signal applied to the gate of the power control transistor. In addition, a parallel capacitor is also controlled to enhance the efficiency and compensate for the load variation. This chip is implemented using 0.35 μm BCD technology with an active area of around 5,000 × 2,500 μm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94 %.The maximum power efficiency of the receiver is about 70 %. The transmitter provides an output power control range of 10–30.2 dBm. The maximum power efficiency of the PA is 71.5 %.     

S波段高效F类/逆F类GaN HEMT功率放大器设计

为了解决F类和逆F类（F-1类）功率放大器设计过程中受晶体管寄生参数影响,导致功放效率低以及输出匹配电路结构复杂的问题,提出了一种新型的输出匹配电路结构.首先,在直流偏置线中加入谐波调谐功能,避免单独设计谐波控制电路;其次,为满足F类和F-1类功放在器件本征漏极端所需的阻抗状态,匹配寄生参数呈现的封装端谐波阻抗,采用一段L型传输线结构代替传统的L-C集总元件寄生补偿方法;最后,由两段串联的传输线实现最优基波阻抗与50 Ω负载间的匹配.为验证方法的有效性,采用CGH40010氮化镓高电子迁移率晶体管（Gallium nitride high electron mobility transistor,GaN HEMT）器件,设计并加工了两款工作在2.4 GHz的F类和F-1类功放.测试结果显示:F类功放的峰值功率附加效率（power added efficiency,PAE）为75.5%,饱和输出功率为40.8 dBm;F-1类功放的峰值PAE为77.6%,饱和输出功率为40.3 dBm.该方法降低了电路复杂度和设计难度,可以较容易地补偿晶体管寄生参数,功放在高频工作时的效率得到提升,为利用GaN HEMT器件设计高效功放提供了一种可行的方案.     

A 65 nm CMOS fully-integrated dynamic reconfigurable differential power amplifier with high gain in both bands

A fully-integrated dual-band dynamic reconfigurable differential power amplifier with high gain in 65 nm CMOS is presented. A switchable shunt LC network is proposed to implement the dual-band reconfigurable operation and achieve high gain at both low and high frequency bands, and the high quality on-chip transformers are utilized to implement input/output impedance matching and single-ended to differential conversion. Measured results show that the dual-band dynamic reconfigurable power amplifier can provide 23 dB gain at 2.15 GHz and 21 dB gain at 4.70 GHz, and achieve more than 19 dBm saturated output power at 2.15 GHz and 13 dBm saturated output power at 4.70 GHz, respectively. The die area is about 1.7 mm×2.0 mm.     

A 0.4–2.3 GHz broadband power amplifier extended continuous class-F design technology

A 0.4–2.3 GHz broadband power amplifier (PA) extended continuous class-F design technology is proposed in this paper. Traditional continuous class-F PA performs in high-efficiency only in one octave bandwidth. With the increasing development of wireless communication, the PA is in demand to cover the mainstream communication standards’ working frequencies from 0.4 GHz to 2.2 GHz. In order to achieve this objective, the bandwidths of class-F and continuous class-F PA are analysed and discussed by Fourier series. Also, two criteria, which could reduce the continuous class-F PA’s implementation complexity, are presented and explained to investigate the overlapping area of the transistor’s current and voltage waveforms. The proposed PA design technology is based on the continuous class-F design method and divides the bandwidth into two parts: the first part covers the bandwidth from 1.3 GHz to 2.3 GHz, where the impedances are designed by the continuous class-F method; the other part covers the bandwidth from 0.4 GHz to 1.3 GHz, where the impedance to guarantee PA to be in high-efficiency over this bandwidth is selected and controlled. The improved particle swarm optimisation is employed for realising the multi-impedances of output and input network. A PA based on a commercial 10 W GaN high electron mobility transistor is designed and fabricated to verify the proposed design method. The simulation and measurement results show that the proposed PA could deliver 40–76% power added efficiency and more than 11 dB power gain with more than 40 dBm output power over the bandwidth from 0.4–2.3 GHz.     

基于40 nm CMOS工艺的毫米波注入锁定分频器

设计了一款应用于60 GHz频率综合器的二分频注入锁定分频器。通过优化射频注入和直流偏置网络,降低了注入信号损耗,提高了注入效率;通过优化注入管和交叉管尺寸、减小寄生电容、降低振荡摆幅,提高了注入效率,降低了功耗;电磁仿真毫米波段电感,建立集总等效电路模型,实现了高感值、低串联电阻的差分电感的设计,提高了锁定范围。电路设计采用SMIC 40 nm 1P6M RF CMOS工艺,芯片核心面积为0.016 mm²。仿真结果表明,在0.8 V电源电压下,电路功耗为5.5 mW,工作频率范围为55.2~61.2 GHz,注入锁定范围为6.0 GHz,满足低功耗和宽锁定范围的要求,适用于毫米波段锁相环频率综合器。     

A multi-band low noise amplifier with strong immunity to interferers

A multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (with center frequencies at 1.2, 1.7 and 2.2 GHz respectively) using an area efficient switchable \(\pi\) network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip built-in-self-test circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point (\(IIP_3\)) ranges from ?15 to 0 dBm. Implemented in a 0.13 \(\upmu\)m CMOS technology, the LNA occupies an active area of about 0.29 mm\(^2\). This design can be used for cognitive radio and other wideband applications, which require a dynamic configuration of the signal-to-intermodulation ratio, when sufficient information about the power and the location of the interferers is not available.     

Prediction of matching condition for a microstrip subsystem using artificial neural network and adaptive neuro-fuzzy inference system

In this paper, a subsystem consisting of a microstrip bandpass filter and a microstrip low noise amplifier (LNA) is designed for WLAN applications. The proposed filter has a small implementation area (49 mm²), small insertion loss (0.08 dB) and wide fractional bandwidth (FBW) (61%). To design the proposed LNA, the compact microstrip cells, an field effect transistor, and only a lumped capacitor are used. It has a low supply voltage and a low return loss (–40 dB) at the operation frequency. The matching condition of the proposed subsystem is predicted using subsystem analysis, artificial neural network (ANN) and adaptive neuro-fuzzy inference system (ANFIS). To design the proposed filter, the transmission matrix of the proposed resonator is obtained and analysed. The performance of the proposed ANN and ANFIS models is tested using the numerical data by four performance measures, namely the correlation coefficient (CC), the mean absolute error (MAE), the average percentage error (APE) and the root mean square error (RMSE). The obtained results show that these models are in good agreement with the numerical data, and a small error between the predicted values and numerical solution is obtained.     

一个8~18GHz的宽带高功率放大器

设计研制了一个8~18GHz的混合集成电路宽带高功率放大器。高功率放大器由基于GaAs MMIC工艺的4指微带兰格耦合器实现。为了减小电磁干扰,采用散热效果好的多层AlN材料作为功率放大器的载体。当输入功率为25dBm时,功率放大器输出连续波饱和功率在8–13 GHz 频率范围内大于39dBm,在其他频率范围内大于38.6dBm,在11.9GHz我们得到最大输出功率39.4dBm。在整个频带内,功率附加效率大于18%,当输入功率为18dBm时小信号增益为15.70.7 dB。高功率功率放大器尺寸为25mm*15mm*1.5mm.     

A 1 V power amplifier for 81–86 GHz E-band

The design and layout of a two stage SiGe E-band power amplifier using a stacked transformer for output power combination is presented. In EM-simulations with ADS Momentum, at E-band frequencies, the power combiner consisting of two individual single turn transformers performs significantly better than a single 2:1 transformer with two turns on the secondary side. Imbalances in the stacked transformer structure are reduced with tuning capacitors for maximum gain and output power. At 84 GHz the simulated loss of the stacked transformer is as low as 1.35 dB, superseding the performance of an also presented alternative power combiner. The power combination allows for a low supply voltage of 1 V, which is beneficial since the supply can then be shared between the power amplifier and the transceiver, thereby eliminating the need of a separate voltage regulator. To improve the gain of the two-stage amplifier it employs a capacitive cross-coupling technique not yet seen in mm-wave SiGe PAs. Capacitive cross-coupling is an effective technique for gain enhancement but is also sensitive to process variations as shown by Monte Carlo simulations. To mitigate this two alternative designs are presented with the cross coupling capacitors implemented either with diode coupled transistors or with varactors. The PA is designed in a SiGe process with f _T  = 200 GHz and achieves a power gain of 12 dB, a saturated output power of 16 dBm and a 14 % peak PAE. Excluding decoupling capacitors it occupies a die area of 0.034 mm².