Optical notch filter design based on digital signal processing

Based on digital signal processing theory,a novel method of designing optical notch filter is proposed for Mach-Zehnder interferometer with cascaded optical fiber rings coupled structure.The method is simple and effective,and it can be used to implement the designing of the optical notch filter which has arbitrary number of notch points in one free spectrum range(FSR).A design example of notch filter based on cascaded single-fiber-rings is given.On this basis,an improved cascaded double-fiber-ri...     

Low-voltage low-power FGMOS based VDIBA and its application as universal filter

This paper presents Floating gate MOS (FGMOS) based low-voltage low-power variant of recently proposed active element namely Voltage Differencing Inverting Buffered Amplifier (VDIBA). The proposed configuration operates at lower supply voltage ±0.75 V with the total quiescent power consumption of 1.5 mW at the biasing current of 100 µA. Further the operating frequency of the proposed VDIBA is improved by using the resistive compensation method of bandwidth extension in Operational Transconductance Amplifier (OTA) stage of the block. By using resistive compensation method of bandwidth extension, the bandwidth of OTA stage increases from 92.47 MHz to 220.67 MHz. As an application, proposed FGMOS based VDIBA has been used to realize a novel resistorless voltage mode (VM) universal filter. The proposed universal filter configuration is capable of realizing all the standard filter functions in both inverting and non-inverting forms simultaneously without any matching constraint. Other important features include independently tunable filter parameters, cascadibility and low sensitivity figure. The proposed filter is tunable over the frequency range of 4.1 MHz to 12.9 MHz and is capable of compensating for process, voltage and temperature (PVT) variation. The simulations are performed using SPICE and TSMC 0.18 µm CMOS technology parameters with±0.75 V supply voltage to validate the effectiveness of the proposed circuit.     

基于二阶滤波器的高阶带通滤波器设计和仿真

根据n阶带通滤波器传递函数的特点和低通与高通级联的思想,给出了高阶RC有源带宽可调的带通滤波器的一般设计方法和VCVS结构电路的设计步骤,并成功设计出一款高性能的四阶有源带通滤波器,其电路简单,通频带宽,精度高,成本低廉.经Multisim10仿真测试,其性能完全达到了预期效果和设计要求.     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

低压低功耗运算放大器结构设计技术

低电压、低功耗、动态摆幅达到轨到轨（Rail—to—Rail）的运放是实现SOC设计的核心，而相关的输入输出模块是其中的关键技术。本文分析了两种分别工作于弱反型区和强反型区的恒跨导Rail—to—Rail输入级，同时给出了低压和极低压下两种AB类控制输出级的实现方案，并对各方案进行了比较和总结。     

级联臂长差啁啾MZI型带通滤波器的分析设计

为了设计出自由频谱区(FSR)较大和3dB带宽较小的带通滤波器,拟合级联马赫-曾德尔干涉仪(MZI)与阶梯形滤波器原理的相似性,在MZI中引入啁啾臂长差以有效扩展FSR.采用传输矩阵法建立带通滤波器的理论模型,进而分析其滤波性能(3dB带宽、FSR)与结构参数(级联级数、衍射阶数)的对应关系.结果表明,当合理选取啁啾系数,该滤波器在保持3dB带宽不变的前提下有效扩展了FSR,并且在整个FSR内具有高边模抑制比.在设计实例中,对应低于.5nm的3dB带宽和高于100nm的FSR(要求边模抑制比高于35dB)的滤波性能,器件的级联级数、衍射阶数、最佳啁啾系数分别对应16,5和5.     

Very low-voltage analog signal processing based on quasi-floating gate transistors

A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very low-voltage applications.     

The design of wideband and low-power CMOS active polyphase filter and its application in RF double-quadrature receivers

In this work, a new technique to implement the transfer function of polyphase filter with CMOS active components is proposed and analyzed. In the proposed polyphase filter structure, the currents mirrored from capacitors and the transistors in a single-stage are used to realize high-pass and low-pass functions, respectively. The multistage structure expands the frequency bandwidth to more than 20 MHz. Furthermore, a constant-gm bias circuit is employed to decrease the sensitivity of image rejection to temperature and process variations. HSPICE simulations are performed to confirm the performance. With the current-mode operation, the low-voltage version of proposed active polyphase filters was designed. It can be operated at 1-V power supply with similar performance but with only 50% of the power dissipation of the normal-voltage version. The proposed four-stage polyphase filter is fabricated in 0.25-/spl mu/m CMOS 1P5M technology. The measured image rejection ratio is higher than -48 dB at frequencies of 6.1 MHz/spl sim/30 MHz. The measured voltage gain is 6.6 dB at 20 MHz and IIP3 is 8 dBm. The power dissipation is 11 mW at a supplied voltage of 2.5 V and the active chip area is 1162/spl times/813 /spl mu/m/sup 2/.     

Fuzzy rule-based signal processing and its application to imagerestoration

A novel signal processing technique based on fuzzy rules is proposed for estimating nonstationary signals, such as image signals, contaminated with additive random noises. In this filter, fuzzy rules concerning the relationship between signal characteristics and filter design are utilized to set the filter parameters, taking the local characteristics of the signal into consideration. The fuzzy rules are found to be quite effective, since the rules to set the filter parameters are usually expressed in an ambiguous style. The high performance of this filter is demonstrated in noise reduction of a 1-D test signal and a natural image with various training signals     

数字滤波器在数字信号处理中的应用设计

在信号处理中,滤波占有十分重要的地位.数字滤波是数字信号处理的基本方法,以FIR滤波器为基础,利用MATLB程序设计语言对低通FIR数字滤波器进行了有效的设计,应用DSP 汇编语言编程实现了该滤波器.     

Lossless grounded inductance simulator employing single VDBA and its experimental band-pass filter application

Actively simulated grounded inductors have been used in several applications ranging from filter to oscillator design as well as cancelation of parasitic inductances. In this paper, new lossless grounded inductance simulator employing only one voltage differencing buffer amplifier (VDBA) and two passive components is proposed. The aim of this paper is to present new inductance simulator using the minimum number of active and passive components. The proposed inductance simulator can be tuned electronically by changing the transconductance of the VDBA. Finally, using the proposed inductance simulator a band-pass filter is constructed. The performance of the filter is simulated by using PSPICE and simulation results are verified experimentally.     

基于LabVIEW的医学信号处理程序设计

近年来,随着计算机技术的不断完善和进步,医学信号数字化的需求越来越突出。而虚拟仪器技术的应用提高了医疗信号处理仪器的数字化进程,同时由于虚拟仪器技术将硬件软件化和软件模块化的特点,使得仪器具有开发周期短、通用性强和便于维修升级等特点,为研究人员节省了大量的时间和精力。本文主要讨论了采用虚拟仪器和LabVIEW分析、处理生物医学信号（心电信号、脑电信号）的方法和技术,满足了医院内部乃至在整个网络上实现辅助诊断的需求,并能分析病人病变过程。     

有源磁控忆阻器的等效电路及滤波频率特性研究

基于三次非线性数学模型,采用通用有源电路元器件完成了一种磁控忆阻器的"浮地"二端口等效电路实现,基于Multisim电路仿真软件并搭建实际硬件电路研究了其伏安特性,进而研究了基于该有源磁控忆阻器的WC高通和低通滤波电路的频率特性,并与无源RC高通和低通滤波电路的频率特性进行了比较。软件仿真和硬件实验结果表明:有源WC高通滤波电路与无源RC高通滤波电路呈现相似的幅频和相频特性,而有源WC低通滤波电路的频率特性不同于单极点的无源RC低通滤波电路,其幅频和相频特性均呈现出多极点的特性。     

基于DSP Builder的脑电信号小波处理

针对脑电信号非平稳性特点,利用小波变换对采集到的脑电信号进行滤波处理.然而小波变换巨大的计算量限制其在高速实时信号处理领域的应用,FPGA器件兼具并/串行工作方式,具有较高的并行计算能力,在现场数字信号处理领域具有较强的实时性.提出基于FPGA的小波变换系统设计方法,首先利用DB2小波对脑电信号按Mallat算法进行分解,然后采用小波重构算法去噪.试验结果表明,运用小波分解重构算法,可以对脑电信号进行实时滤波.     

基于DSP Builder的脑电信号小波处理

针对脑电信号非平稳性特点,利用小波变换对采集到的脑电信号进行滤波处理。然而小波变换巨大的计算量限制其在高速实时信号处理领域的应用,FPGA器件兼具并／串行工作方式,具有较高的并行计算能力,在现场数字信号处理领域具有较强的实时性。提出基于FPGA的小波变换系统设计方法,首先利用DB2小波对脑电信号按Mallat算法进行分解,然后采用小波重构算法去噪。试验结果表明,运用小波分解重构算法,可以对脑电信号进行实时滤波。     

基于Matlab的FIR带通滤波器设计及DSP实现

借助Matlab的FDATOOL滤波器设计分析软件,设计了一种FIR数字带通滤波器,并对一段含噪语音信号进行滤波。利用汇编语言编程,在DSP上实现了该滤波器。实验结果表明,该数字带通滤波器精确,稳定性好,易于移植,具有很强的实用性与灵活性。     

单调谐滤波器参数设计及其应用

针对电力谐波给企业带来的安全生产隐患及对公用电网造成的严重污染和不利影响,本文简述了滤波器的工作原理,并结合工程实际为例,详细阐述了单调谐滤波器的特性及其设计过程,这种设计方法根据现有的设计经验,全面考虑设计的要求和条件,通过无功需求量确定出滤波器的基本参数,给出了结构简单、经济可靠的抑制谐波危害的办法。实践证明该设计方案谐波抑制效果良好,节能效果显著,在工程实践中可行。最后,实例分析的结果也证明了设计过程的合理性。     

考虑器件标称化的带通滤波器仿真优化设计

滤波器的传统设计方法计算出的电感、电容值并不能与市场上购置的电感、电容值完全对应,导致制作的滤波器技术指标降低。为此提出一种改进的LC带通滤波器优化设计方法,借助ADS对电路进行仿真优化,使仿真结果更接近于实际测试值。与传统方法相比,文中设计的滤波器提高了实际滤波器的性能;并且通过优化,使所有元件值均为市场所售器件的标称值,从而解决了因购置器件值与计算值不完全一致而导致的滤波器性能恶化。     

Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design

In this paper, novel non-conventional techniques,¹ named by the author of this paper “bulk-driven floating-gate (BD-FG)” MOS transistor (MOST) and “bulk-driven quasi-floating-gate (BD-QFG) MOST” for low-voltage (LV) low-power (LP) analog circuit design are presented. These novel techniques appear as a good solution to merge the advantages of floating-gate (FG) and quasi-floating-gate (QFG) with the advantages of bulk-driven (BD) technique and suppress their disadvantages. Consequently, the transconductance and transient frequency of BD-FG and BD-QFG MOSTs approach the conventional gate driven (GD) MOST values. Furthermore, a novel LV LP class AB second generation current conveyor based on BD-FG MOST is presented in this paper as an example. The supply voltage is only ±0.4 V with a rail-to-rail voltage swing capability and total power consumption of mere 10 μW. PSpice simulation results using the 0.18 μm P-well CMOS technology are included to confirm the attractive properties of these new techniques.     

High-speed, low-power, bipolar standard cell design methodology forGbit/s signal processing

A low-power Si bipolar standard cell LSI design methodology for gigabit/second signal processing is described. To obtain high-speed operation, it features a pair of differential clock channels inside cells, differential clock distribution with the placement of differential wires of equal length and load, a performance-driven layout, and a highly accurate static timing analysis. A computer-aided-design-based optimization technology for power dissipation makes cell currents minimum while maintaining the circuit speed. A 5.6-K gate synchronous digital hierarchy signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design method