HIBI Communication Network for System-on-Chip

This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates.HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μ m technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals.Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration. Erno Salminen Tampere University of Technology (TUT), Finland.Currently he is working towards his PhD degree in the Institute of Digital and Computer Systems (DCS) at TUT. His main research interests are digital systems design and communication issues in SoCs. Tero KangasTampere University of Technology (TUT), Finland.Since 1999 he has been working as a research scientist in the Institute of Digital and Computer Systems (DCS) at TUT. Currently he is working towards his PhD degree and his main research topics are system architectures and SoC design methodologies in multimedia applications. Timo D. H?m?al?ainen Tampere University of Technology (TUT), Finland. He was nominated to full professor at TUT/Institute of Digital and Computer Systems in 2001. He heads the DACI research group that focuses on three main research areas: wireless sensor networks, high-performance multi-DSP and hardware based video encoding, and design flow tools for heterogeneous MP-SoC platforms. Jouni Riihi?mki Tampere University of Technology (TUT), Finland. Currently he is working as a senior design engineer at Nokia Technlogy Platforms. He is also working towards his PhD degree. His research interests include SoC design and verification methodologies. Vesa Lahtinen received his M.Sc. and Ph.D. from TUT in 1998 and 2004, respectively. In TUT, his main research areas were system-on-chips and their interconnects. Currently, Dr. Lahtinen is a Senior Research Engineer in the Computing Architectures Laboratory of Nokia Research Center (NRC) concentrating on architecture modeling and, specifically, memory architectures. Kimmo Kuusilinna Tampere University of Technology (TUT), Finland. His main research interests include system-level design and verification, on-chip interconnections, and parallel memories. Currently he is working as a senior research engineer at the Nokia Research Center.     

高士其的科普创作思想

高士其是20世纪30年代成长起来的中国著名的科普作家。他是科学小品文这一重要科普创作体裁的集大成者,并且开创了现代科学诗这一新的体裁。作为科学文艺作家,他的作品不仅具有科学性、艺术性、思想性三个特点,而且将科学知识成功地本土化。他早期作品的思想性主要体现在具有很强的战斗性,与当时的时代背景紧密相关。     

A 1 V switchable CMOS LNA for 802.11A/B WLAN applications

A new dual-band, 2.4 and 5.2 GHz, combined LNA, which can operate at 1 V supply only, for WLAN application is presented. The switched transistor technique is used in the LNA. It could match the input port in two frequency bands and reduce one on-chip spiral inductor usage compared with [1, 2]. Theoretical analysis and transistor level simulation results using 0.18 μm CMOS process from Chartered Semiconductor are presented to demonstrate this idea. Wang-Chi Cheng received his B.Eng., M.Phil., and Ph.D. degrees in Electronic Engineering of the Chinese University of Hong Kong (CUHK) in 1999, 2001 and 2004. His research achievements during M.Phil. and Ph.D. studies were in the field of low voltage receiver front-end circuits design with CMOS technology. He joined the Electrical and Electronic Engineering department of Nanyang Technological University (NTU), Singapore, in May 2005 as a Research Fellow. Now, he is a Senior Engineer in charge of the UWB transceiver IC design in Hong Kong Applied Science and Technology Research Institute (ASTRI). His current research interests include 802.11 A/B WLAN and UWB transceiver design. He is also a paper reviewer of the IEEE Microwave and Wireless Components Letters. Jian-Guo Ma received his B.Sc. and M.Sc. in 1982 and 1988 respectively with honors from Lanzhou university of Chain, and Doctoral Degree in Engineering from Gerhard-Mercator University of Germany in 1996. From Jan. 1982 to March 1991, he has worked with Lanzhou university of China on RF & Microwave Engineering. Before he joined Nanyang Technological University in 1997, he was with Technical University of Nova Scotia, Canada. Now, he is a Professor of the University of Electronic Science and Technology of China. His research interests are: RFIC designs for wireless applications; RF characterization and modeling of semiconductor devices; RF interconnects and packaging; SoC and Applications; EMC/EMI in RFICs. He has published more than 150 technical papers and two books in above mentioned areas. He holds 6 patents in CMOS RFICs. He is now Associate Editor for IEEE Microwave and Wireless Components Letters. Kiat-Seng Yeo received his B.E. (Hons.) (Elect) in 1993, and Ph.D. (Elect. Eng.) in 1996 both from Nanyang Technological University, Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore as a Lecturer in 1996, and became an Assistant Professor and an Associate Professor in 1999 and 2002, respectively. Professor Yeo provides consulting to statutory boards and multinational corporations in the areas of semiconductor devices and electronic circuit design. He has been extensively involved in the modeling and fabrication of small MOS/Bipolar integrated technologies for the last ten years. His research interests also include the design of new circuits and systems (based on scaled technologies) for low-voltage low-power applications; radio frequency integrated circuit (RF IC) design; integrated circuit design of BiCMOS/CMOS multiple-valued logic circuits, domino logic, and memories; and device characterization of deep submicrometer MOSFETs. Manh-Anh Do obtained his B.E. (Hons) (Elect.) in 1973, and Ph.D. (Elect. Eng.) in 1977 both from University of Canterbury, New Zealand. Between 1977 and 1989, he held various positions including: R & D engineer and production manager at Radio Engineering Ltd., research scientist at Fisheries Research Centre, New Zealand, and senior lecturer at National University of Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore as a senior lecturer in 1989, and obtained the Associate Professorship in 1996 and the Professorship in 2001. He has been a consultant for many projects in the Singapore electronic industry, and was the principal consultant for the design, testing and implementation of the $200 million Electronic Road Pricing (ERP) island-wide project in Singapore, from 1990 to 2001. His current research is on digital and mobile communications, RF IC design, mixed-signal circuits and intelligent transport systems. Before that, he specialsed in sonar designing, biomedical engineering and signal processing. Since 1995, he has been Head of Division of Circuits and Systems, School of EEE, NTU. He is a Fellow of IEE, UK, a Chartered Engineer (UK) and a Professional Engineer (Singapore).     

Sub-mA single ended CMOS low noise amplifier with 2.41 dB noise figure

This paper presents a single ended low noise amplifier (LNA) using 0.18 μm CMOS process packed and tested on a printed circuit board. The LNA is powered at 1.0 V supply and drains 0.95 mA only. The LNA provides a forward gain of 11.91 dB with a noise figure of only 2.41 dB operating in the 0.9 GHz band. The measured value of IIP3 is 0.7 dBm and of P1dB is −12 dBm. Zhang Liang is currently with Cyrips, Singapore. Ram Singh Rana was born in Delhi (India). Having primary education in Bijepur, Dwarahat(India), he received the B.Tech. (hons.) degree in Computer Engineering from G.B. Pant University, Pantnagar, India in 1988 and the Ph.D degree from the Indian Institute of Techonology (IIT), Delhi, India in 1996. He worked for his Ph.D in the Centre for Applied Research in Electronics, IIT Delhi in close interaction with the Semiconductor Complex Limited, Mohali, India. He was with ESPL, Mohali(India) in 1988 for a very short period and then served IIT Delhi as Senior Research Associate (88-90) and Senior Scientific Officer (90-95) where his main contributions were on CMOS analog IC design in subthreshold operation. He was a Lecturer in the Kumaon Engg. College, Dwarahat (India) before serving the IIT Roorkee (Formerly Univ. of Roorkee) in 1998 as assistant Professor. In 1999, he was a Manager (Engineering), Semiconductor Product Sector of the Motorola, Noida, India. Since joining the Institute of Microelectronics, Singapore in 2000, he worked mostly on RFICs, Fractional-N PLLs, ADCs. During 2001-2004, he worked there as IC Design Research and Training Program Manager. Currently, he is serving the institute as Senior Research Engineer in CMOS IC design (below 1V) for biomedical and bio-sensors. His current interests include design and consultancy for CMOS ICs/systems for the biomedical and high speed communication applications. Dr. Rana received Young Teacher Career Award from the All India Council for Technical Education in 1997. He was an Adjunct Asstt. Professor with the National University of Singapore (NUS), Singapore in 2004. He is sole inventor of two US granted patents and has filed several other patents. He has authored/co-authored about 40 publications. He has been reviewer for several IEEE journals and conference papers. Dr Rana is a senior member of IEEE and a member of Graduate Program in BioEngineering, NUS Singapore. He has chaired /co-chaired sessions in many international conferences. Zhang Liang was born in China in June 1978. He received the Bachelor degree and the Master degree in Electrical Engineering from the Xi’an JiaoTong University, Xi’an, China, in 2000 and 2003 respectively. Since 2003, he has been a postgraduate student in the Electrical and Computer Engineering department, National University of Singapore(NUS), Singapore and has successfully completed M.Engg degree program of the NUS. He is currently working on RFICs as a design engineer in Cyrips, Singapore. His design and research interests include integrated circuit design for communications. He has authored/co-authored several publications of international standard. Hari K Garg obtained his BTech degree in EE from IITDelhi in 1981. Subsequently, he obtained his MEng & PhD degrees from Concordia University in 1983 & 1985, and MBA from Syracuse University in 1985. He was a faculty member at Syracuse University from 1985 till 1995. He has been with the National University of Singapore since 1995 till present with the exception of 1998-1999 when he was with Philips. Hari’s research interests are in the area of digital signal/image processing, wireless communications, coding theory and digital watermarking. He has published extensively on these and related topics. He is also founder of several companies in the space of mobile telephony. In his spare time, Hari enjoys singing and a good game of Squash.     

Looking back: how practical experience in the classroom taught me aprofessional approach on the job

The author discusses his experience as a graduate student in the Technical Communication Program at Oklahoma State University (OSU). He discusses activities that he found particularly valuable being an intern, namely, participating in the Society for Technical Communication (STC), writing for publication, and giving oral presentations     

Simplified Modeling of a Multipole Amplifier Using All-Pass Network Functions

This paper presents a system model for the representation of amplifiers that cannot be accurately characterized by a classical two pole transfer function. The effects of higher order poles are modeled by an all-pass function added to the conventional two pole model. The accuracy of the model is demonstrated by comparing the results for a typical CMOS amplifier to those obtained from device level simulations using SPICE. This model can be easily implemented in a standard simulator and is shown to achieve fast simulation time. This model is expected to have application in system level modelling of mixed-signal circuits using conventional SPICE simulators.Yihong Dai received his B.S. and M.Eng. degrees in Electrical Engineering from Shanghai JiaoTong University, Shanghai, China in 1993 and 1996, respectively. From 1996 to 1998, he enjoyed his industrial experiences in Shanghai with semiconductor companies like Shanghai Nortel Semiconductor and Motorola Electronics (China) Shanghai Branch. Since 1998, he has been a research assistant at the Analog and Mixed-signal Laboratory of the Electrical Engineering Department of Brigham Young University working toward his Ph.D. During the summer of 1999, he was with AMI semiconductor Utah Research and Design Center where he developed a threshold voltage based CMOS voltage reference architecture. In the summer of 2001, he was with Ultra Design where he designed a reference amplifier for high speed digital-to-analog converters. His research interest includes voltage reference, reference amplifier and high speed data converters in both CMOS and GaAs processes.Donald T. Comer received the B.S, M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and the University of Santa Clara, respectively, all in electrical engineering. He began teaching at San Jose State University in 1961 and mixed his teaching and industrial work until he left San Jose State University in 1979. He has worked for California Technical Industries, IBM Corp., Mobility Systems, Precision Monolithics, Storage Technology Corp., and Analog Devices during his career. He founded the AMI Utah Research and Design Center in 1998 that specializes in MOS design. In 2002, Dr. Comer founded Ultra Design, a design center that specializes in high-frequency heterojunction circuit designs. He holds fifteen patents and has published over 50 articles dealing with solid-state and integrated circuits. He has published five textbooks in the field of large-signal and integrated circuits. He formerly held the Quentin Berg Chair at Penn State Harrisburg from 1990 to 1995. He is now a professor of electrical and computer engineering at Brigham Young University where he held the Endowed Chair of Engineering from 1995 to 1998.David J. Comer received the B.S., M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and Washington State University, respectively, all in electrical engineering. He has worked for IBM Corp., Pacific Electromagnetics, Lawrence Livermore Laboratories, and Intel Corporation. He began his teaching career at the University of Idaho and has taught at the University of Calgary and California State University, Chico. He is presently a professor of electrical and computer engineering at Brigham Young University. He served as Chairman of the Division (Dean) of Engineering at CSU, Chico and as Department Chair at BYU.While at CSU, Chico, Dr. Comer served on the statewide Engineering Liaison Committee and served as Chair of the Council of California State University Deans of Engineering.Dr. Comer has published twelve textbooks and over 60 articles in the field of circuit design. He has contributed sections to the Encyclopedia of Physical Science and Technology and holds seven patents. He was given the Professional Achievement Award at CSU, Chico and was named the Outstanding Teacher of Engineering at BYU. He has also held the College of Engineering Research Chair at Brigham Young University.Darren Korth received the B.S. and M.S. degrees in electrical engineering at Brigham Young University, Provo, Utah in 1999. He is currently pursuing a Ph.D. in electrical engineering. He served as an instructor for the Department of Electrical and Computer Engineering at Brigham Young University from 2000 to 2002. From 2001 to 2003, he also worked as a senior design engineer at UltraDesign, LLC, Provo, Utah where he researched high-speed data converter circuits. He is currently with AMI Semiconductor in their RF CMOS group.     

Scalable Architecture for SoC Video Encoders

Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers. Tero Kangas, MSc ’01, Tampere University of Technology (TUT). Since 1999 he has been working as a research scientist in the Institute of Digital and Computer Systems (DCS) at TUT. Currently he is working towards his PhD degree and his main research topics are system architectures and SoC design methodologies in multimedia applications. Kimmo Kuusilinna, PhD ’01, TUT. His main research interests include system-level design and verification, interconnection networks, and parallel memories. Currently he is working as a senior research engineer at the Nokia Research Center. Timo D. H?m?l?inen, MSc ’93, PhD ’97, TUT. He acted as a senior research scientist and project manager at TUT in 1997-2001. He was nominated to full professor at TUT/Institute of Digital and Computer Systems in 2001. He heads the DACI research group that focuses on three main lines: wireless local area networking and wireless sensor networks, high-performance DSP/HW based video encoding, and interconnection networks with design flow tools for heterogeneous SoC platforms.     

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

A Body biasing technique has recently been proposed for microprocessors in sub-100 nm technology generations [11, 12]. It is shown that forward body bias (FBB) reduces the leakage power and suppresses the effect of process variation while reducing the complexity of dualV_th technology. In this paper, we study the effect of body bias on the delay fault testing of CMOS circuits. We analyze the impact of both fixed and adaptive body biasing techniques on test cost and the quality of test. Statistical analysis on several benchmark circuits shows that the adaptive body biasing design will have the most effective impact on delay fault by maintaining the test cost at its minimum under process variation while ensuring the test quality at its highest level. Bipul C. Paul received B.Tech. and M.Tech. degrees in radiophysics and electronics, from the University of Calcutta and the Ph.D. degree from Indian Institute of Science (IISc), Bangalore, India. After his graduation, he joined Alliance Semiconductor (India), where he worked on synchronous DRAM design. In 2000, he joined Purdue University, West Lafayette, USA, as a Post Doctoral Fellow, where he worked on low-power electronic design of nanoscale circuits (both bulk and SOI technologies), statistical design under process variation, VLSI testing, verification and noise analysis. He has also developed device and circuit optimization techniques for ultra-low power digital sub-threshold operation. Dr. Paul is presently with Toshiba Research, where he is working on post-silicon devices and technology and nano-architecture. He is also a Visiting Scientist at Stanford University, USA. Dr. Paul received National scholarship (India) in 1984, the senior research fellowship award from CSIR, India in 1995 and the Best Thesis of the Year award in 1999. He is a senior member of IEEE. Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. Dr. Roy has published more than 200 papers in refereed journals and conferences, holds 5 patents, and is a co-author of a book on Low Power CMOS VLSI Design (John Wiley). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, best paper awards at 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, and is currently a Purdue University faculty scholar professor. He is in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, and IEEE Transactions on VLSI Systems. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000). Dr. Roy is fellow of IEEE.     

Audio Fingerprinting: Nearest Neighbor Search in High Dimensional Binary Spaces

Audio fingerprinting is an emerging research field in which a song must be recognized by matching an extracted “fingerprint” to a database of known fingerprints. Audio fingerprinting must solve the two key problems of representation and search. In this paper, we are given an 8192-bit binary representation of each five second interval of a song and therefore focus our attention on the problem of high-dimensional nearest neighbor search. High dimensional nearest neighbor search is known to suffer from the curse of dimensionality, i.e. as the dimension increases, the computational or memory costs increase exponentially. However, recently, there has been significant work on efficient, approximate, search algorithms. We build on this work and describe preliminary results of a probabilistic search algorithm. We describe the data structures and search algorithm used and then present experimental results for a database of 1,000 songs containing 12,217,111 fingerprints. Ingemar J. Cox is currently Professor and Chair of Telecommunications in the Departments of Electronic Engineering and Computer Science at University College London and Director of UCL's Adastral Park Postgraduate Campus. He is currently a holder of a Royal Society Wolfson Fellowship. He received his B.Sc. from University College London and Ph.D. from Oxford University. He was a member of the Technical Staff at AT&T Bell Labs at Murray Hill from 1984 until 1989 where his research interests were focused on mobile robots. In 1989 he joined NEC Research Institute in Princeton, NJ as a senior research scientist in the computer science division. At NEC, his research shifted to problems in computer vision and he was responsible for creating the computer vision group at NECI. He has worked on problems to do with stereo and motion correspondence and multimedia issues of image database retrieval and watermarking. In 1999, he was awarded the IEEE Signal Processing Society Best Paper Award (Image and Multidimensional Signal Processing Area) for a paper he co-authored on watermarking. From 1997–1999, he served as Chief Technical Officer of Signafy, Inc, a subsiduary of NEC responsible for the commercialization of watermarking. Between 1996 and 1999, he led the design of NEC's watermarking proposal for DVD video disks and later colloborated with IBM in developing the technology behind the joint “Galaxy” proposal supported by Hitachi, IBM, NEC, Pioneer and Sony. In 1999, he returned to NEC Research Institute as a Research Fellow. He is a senior member of the IEEE, a Fellow of the IEE and a Fellow of the Royal Society for Arts and Manufactures. He is co-editor in chief of the IEE Proc. on Information Security and an associate editor of the IEEE Trans. on Information Forensics and Security. He is co-author of a book entitled “Digital Watermarking” and the co-editor of two books, ‘Autonomous Robots Vehicles’ and ‘Partitioning Data Sets: With Applications to Psychology, Computer Vision and Target Tracking’. This work was performed while the author was at NEC Research Institute, Princeton. ? [2002] IEEE, Reprinted, with permission, from Miller, M.L.; Rodriguez, M.A.; Cox, I.J.; Multimedia Signal Processing, 2002 IEEE Workshop on, 2002 Page(s): 182–185.     

Connectivity of Wireless Multihop Networks in a Shadow Fading Environment

This article analyzes the connectivity of multihop radio networks in a log-normal shadow fading environment. Assuming the nodes have equal transmission capabilities and are randomly distributed according to a homogeneous Poisson process, we give a tight lower bound for the minimum node density that is necessary to obtain an almost surely connected subnetwork on a bounded area of given size. We derive an explicit expression for this bound, compute it in a variety of scenarios, and verify its tightness by simulation. The numerical results can be used for the practical design and simulation of wireless sensor and ad hoc networks. In addition, they give insight into how fading affects the topology of multihop networks. It is explained why a high fading variance helps the network to become connected.Christian Bettstetter is a senior researcher in the Future Networking Lab at DoCoMo Euro-Labs. His current research interests are in the area of self-organized networking, especially, in wireless ad hoc and sensor networks. He published several technical articles in this area and co-authored the Wiley book ‘GSM: Switching, services and protocols.’ From 1998 to 2003, he was with the Institute of Communication Networks at the Technische Universität München (TUM), where he did research and teaching on mobile communication networks, and managed a new international graduate program. Christian received the Dr.-Ing. degree (summa cum laude) and the Dipl.-Ing. degree in electrical engineering and information technology from TUM in 2004 and 1998, respectively. During his graduate studies, he worked for Wacker Siltronic, Portland, OR, USA, and wrote his master thesis on turbo decoding at the University of Notre Dame, IN, USA. He is a member of the IEEE and ACM SIGMOBILE.Christian Hartmann studied electrical engineering at the University of Karlsruhe (TH), where he received the Dipl.-Ing. degree in 1996. In 1997 he joined the Institute of Communication Networks at the Technische Universität München (TUM), where he earned the Dr.-Ing. degree (summa cum laude) in 2003. He is currently a senior researcher and member of the teaching staff at the same institution. During a research leave in the winter of 2000/2001 Christian was with the Wireless Research Lab of Lucent Bell Labs, Crawford Hill, NJ. His main research interests are in the area of mobile and wireless networks, including capacity and performance evaluation, radio resource management, modeling and simulation. He is a member of the IEEE.     

Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages

A CMOS OTA-C low-pass notch filter for EEG application is described. The pass-band covers four bands of brain wave and provides more than 65 dB attenuation for the 50 Hz power line interference. The OTA works in the weak inversion region and a low transconductance of 3 nA/V is achieved. The low transconductance enables using small capacitors in the OTA-C filter so that the filter is suitable for the multi-channel EEG integrated circuits. The measured results show the good performance of the filter for filtering the noise in acquired EEG signals. Xinbo Qian received the B.Sc. degree from Beijing Institute of Technology, P.R. China, in 1991 and M.Sc. degree from Institute of Physics, Chinese Academy of Sciences, in 1996. From 1996 to 1999, she was a research engineer in the Institute of Acoustics, Chinese Academy of Sciences, worked on the sonar signal receiving and processing systems. Since 1999, she has been pursuing the Ph.D. degree in Electrical and Computer Engineering department, National University of Singapore, with research direction on on-chip readout circuits for microbolometer focal plane arrays. Now she is employed by Department of Mechanical Engineering and Division of Bioengineering, National University of Singapore as a research fellow. Her research interest is low-noise integrated circuits design and bio-medical sensor electronics, including electroencephalography IC, magnetocardiography IC, low-noise amplifier, filter and data converters etc. Yong Ping Xu graduated from Nanjing University, P.R. China in 1977. He received his Ph.D. from University of New South Wales (UNSW) Australia, in 1994. From 1978 to 1987, he was with Qingdao Semiconductor Research Institute, P.R. China, initially as an IC design engineer, and later the deputy R&D manager and the Director. From 1989 to 1992, he was working on silicon diode based infrared detectors towards his Ph.D. at School of Electrical Engineering, UNSW Australia. From 1993 to 1995, he worked on an industry collaboration project with GEC Marconi, Sydney, Australia, at the same university, involved in design of sigma-delta ADCs. He was a lecturer at University of South Australia, Adelaide, Australia from 1996 to 1998. He has been with the Department of Electrical and Computer Engineering, National University of Singapore since June 1998 and is now an Associate Professor. His general research interests are in the areas of mixed-signal and RF integrated circuits, and integrated MEMS and sensing systems. His current focuses are high-speed wideband ADC, UWB front-end circuits and low-power low-voltage integrated circuits for biomedical applications. He is a Senior Member of IEEE. Xiaoping Li received his Ph.D. degree from Department of Mechanical and Manufacturing Engineering, University of New South Wales, Australia in 1991, and joined the National University of Singapore in 1992, where he is currently an Associate Professor with the Department of Mechanical Engineering and Division of Bioengineering. He was a visiting professor of Tokyo Institute of Technology, Japan in 2000, and visiting professor of Georgia Institute of Technology, USA in 2001. He is a member of American Society of Mechanical Engineers (ASME), a senior member of Society of Manufacturing Engineering (SME) and a senior member of North American Manufacturing Research Institute/SME, and is currently the Chairman of SME Singapore Chapter. His current research interests include neurosensors and nanomachining. He is a guest editor of International Journal of Computer Applications in Technology, USA. He is a regular reviewer of the ASME Journal of Manufacturing Engineering, USA, Transactions of NAMRI/SME, USA, Journal of materials processing technology, UK, International Journal of Machine Tools and Manufacture, UK, and IMechE Journal of Engineering Manufacture, UK.     

FGMOS Current Mirror: Behaviour and Bandwidth Enhancement

This paper presents a high performance, resistively compensated low voltage current mirror using floating gate MOSFETs (FGMOS). The compensation technique desensitizes the output current and input compliance voltage with respect to the process generated variations in the threshold voltages of the mirroring transistors. Theoretical and simulation results exhibit an appreciable increase in bandwidth of the current mirror for this compensation technique. The operation of these circuits has been verified using PSpice simulations for 0.5 μ m CMOS technology at a supply voltage of ±0.75 V. A part of this paper has appeared in IEEE APCCAS 2002 and NSM 2003. S. Sharma was born on 6th July 1967 at village Bhagta, district Udhampur, J and K (India). He received MSc Physics (Electronics) degree from University of Jammu in 1991 and was awarded University Gold Medal. After qualifying NET (CSIR), he joined as Lecturer in 1995 in the department of Physics and Electronics of the same University. He is presently a Senior Lecturer and pursuing for Ph.D. degree in the area of Analog Integrated Circuits. He has eight papers published in National/International Conferences/Journals. He is a life member of IETE (India). S.S. Rajput was born on July 1, 1957, at village Bashir Pur, District Bijnor UP India. He received his B. E. in Electronics and Communication Engineering and M. E. in Solid State Electronics Engineering from University of Roorkee, Roorkee, India (Now IIT, Roorkee) in 1978 and 1981 respectively and was awarded University gold medal in 1981. He earned his Ph.D. degree from Indian Institute of Technology, Delhi in 2002 and his topic of research was “Low voltage current mode analog circuit structures and their applications”. He joined National Physical Laboratory, New Delhi, India as Scientist B in 1983, where he is presently serving as Scientist EII. He has worked for the design, development, testing and fabrication of an instrument meant for space exploration under the ISRO-NPL joint program for development of scientific instruments for the Indian Satellite SROSS-C and SROSS-C2 missions. His research interests include low voltage analog VLSI, instrument design for space applications, Digital Signal Processing, Fault tolerant design, and fault detection. He has chaired the many sessions in Indian as well as International conferences. He is Fellow member of IETE (India). He has been awarded best paper award for IETE Journal of Education for the year 2002. He has delivered many invited talks on Low Voltage Analog VLSI. Few tutorials have been presented in International Conferences on his Research Work. He has more than 30 publications in national and international journals. L.K. Mangotra was born on 14th April 1944 at Jammu, India. He received M.Sc. (Physics) from University of Kashmir in 1968 and Ph.D. (High Energy Physics) from University of Jammu in 1974. He worked as Assistant Director in Forensic Laboratory of J and K Govt. from 1974–78. He joined Physics Department, University of Jammu as Lecturer in 1978 and became Professor in 1988. He has 131 publications in International Journals and 41 papers in proceedings of International/National Conferences. He has number of visits to foreign Universities in connection with research and has been awarded various Fellowships. He is a member of various Professional/Academic/Administrative bodies. Presently, Prof. Mangotra is an Advisor to University of Jammu for Modernization of University Infrastructure and Principal Investigator for Jammu University and Coordinator of All India Universities in the International Collaborative research project “ALICE” in High Energy Physics sponsored by Department of Atomic Energy and Department of Science and Technology, Govt. of India. S.S. Jamuar was born on 27th November 1949. He received his BSc. Engineering Degree in Electronics and Communication from Bihar Institute of Technology, Sindri in 1967, M. Tech and Ph.D. in Electrical Engineering from Indian Institute of Technology, Kanpur, India in 1970 and 1977 respectively. He worked as Research Assistant, Senior Research Fellow and Senior Research Assistant from 1969 to 1975 at IIT Kanpur. During 1975–76, he was with Hindustan Aeronautics Ltd., Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT Kanpur, where he was involved in the design of various types of Laser Systems. He joined department of Electrical Engineering of IIT Delhi in 1977, where he became Professor in 1991. He is presently Professor in the department of Electrical and Electronic Engineering Department, Faculty of Engineering, University Putra Malaysia, Malaysia. His area of research interest includes Electronic Circuit Design, Instrumentation and Communication systems. He is recipient of Meghnad Saha Memorial Award 1976 from IETE, Distinguished Alumni Award from BIT Sindri in 1999. Dr. Jamuar is senior member of IEEE and Fellow member of IETE (India). He is presently the Chair for CASS Chapter of IEEE Malaysia Section.     

Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic

A very low voltage transconductor for video frequency range applications and compatible with standard CMOS technology is described. In the proposed transconductor, except the DC level shifter circuit (DCLS), the whole transconductor uses the main supply voltage [which can be as low as 1.5 V in a standard 0.6 μm CMOS technology] while the DCLS uses a simple charge-pump circuit as its supply voltage and has a very low current consumption. In addition, proper common-mode sense and charge-pump circuits are developed for this low-voltage application. Meanwhile, some techniques to improve the frequency response, linearity, and noise performance of the proposed transconductor are described. In a standard 0.6 μm CMOS technology and single 1.5 V supply, simulations show that the proposed transconductor futures a THD of −50 dB for 1.4 V_pp and 10 MHz input signal and −60 dB for 1.4 V_pp and 1 MHz signal where the threshold voltage of MOS transistors could be as high as 1 V. Based on the proposed transconductor, a lowpass filter with 700 kHz to 8 MHz programmable cutoff frequency and a bandpass 10.7 MHz second order filter were implemented. Armin Tajalli received the B.Sc. from Sharif University of Technology (SUT), Tehran, Iran, in 1997, and M.Sc. from Tehran Polytechnic University, Tehran, Iran, in 1999. From 1998 he has joint Emad Co. as a senior design engineer were he has worked on several industrial and R&D projects on analog and mixed-mode ICs. He received the award of the Best Design Engineer from Emad Co., 2001, the Kharazmi Award of Industrial Research and Development, Iran, 2002, and Presidential Award of the Best Iranian Researchers, in 2003. He is now working toward his PhD degree at SUT. His current interests are design of high speed circuits for telecommunication systems. Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Technology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering from the University of California, Irvine, in 1987. He received the Ph.D. degree from the University of Southern California (USC) on the subject of analog IC design in 1993. From 1993 to 1996 he worked with Linear Technology Corporation as a senior analog design engineer. Since then, he has been consulting with different IC companies. He is currently a visiting professor at Sharif University of Technology. He has published more than 30 technical papers in the area of analog and mixed-signal integrated circuit design as well as analog CAD tools.     

Sparse Approximations of the LMMSE Channel Estimation in OFDM with Transmitter Diversity

The linear minimum mean-squared error (LMMSE) channel estimation for orthogonal frequency-division multiplexing (OFDM) systems requires a large number of complex multiplications. We evaluate a simplified LMMSE channel estimation algorithm in a transmit diversity environment by applying a significant weight catching (SWC) technique to the LMMSE fixed weighting matrix. The SWC technique itself is based on modifying the smoothing matrix by leaving the Γ largest values in each row and turning the rest to zeros. This allows the computational complexity of the full LMMSE processor to be reduced by more than 50%. In the well known LMMSE by singular value decomposition (SVD) technique the sparse approximation is accomplished by zeroing out all but the r largest singular values. LMMSE by SVD is the preferred approximation technique for low delay spread channels. However, in channels with large delay spreads, LMMSE by SWC is a better choice in terms of computational complexity and estimation accuracy Igor Tolochkoreceived his Dipl.-Eng. Degree in Electrical Engineering from Polytechnic Institute, Riga, Latvia in 1987 and PhD from Victoria University, Melbourne, Australia in 2005. He was a senior and later principal design engineer in mobile communications at the Riga Semiconductor Institute Alpha (1988 – 1993). During 1993 – 1998, he was involved in research and development activities in communications with different companies in Riga and Melbourne, Australia. From 1998 to 2002, he was with Ericsson Australia as a senior design engineer. Currently, he works for NEC Australia Pty. Ltd. as a senior design engineer in 3G Mobile Department. His current research interests include digital signal processing, indoor and outdoor wireless communications and error control coding. Michael Faulkner(M'84) received the B.Sc. (Eng) from Queen Mary College, London University, UK, in 1970, the M.E. degree from the University of New South Wales, Australia in 1978, and the PhD from University of Technology Sydney in 1993. From 1972 to 1975 he was with STC (now Alcatel) Australia. From 1975 to 1977 he as with the University of New South Wales, and since then as a lecturer and now professor at Victoria University of Technology, Melbourne, Australia where he is director of the Telecommunications and Micro-electronics research centre. Between 1988 and 2000 he spent four periods at Lund University, Sweden. He was co-recipient of the IEE's 1997 IERE prize for a paper on amplifier linearisation. His current interests are, signal processing, radio technology, radio systems and MIMO/OFDM.     

Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

Monolithic integration of photodetectors, analog-to-digital converters, data storage, and digital processing can improve both the performance and the efficiency of future portable image products. However, digitizing and processing a pixel at the detection site presents the design challenge to deliver a system with the required performance at the lowest cost, not just a system with the highest performance. This paper analyzes the area-time efficiency, the area efficiency, and the energy efficiency of a mixed-signal, SIMD focal plane processing architecture that executes front-end image applications with neighborhood processing. Implementations of the focal plane architecture achieve up to 81x higher area efficiency and up to 11x higher energy efficiency when compared to traditional TI DSP chips. Higher efficiency ratings are required to maintain portability while addressing technology limitations such as interconnect wiring density, heat extraction, and battery life. Systems can be implemented with a less expensive fabrication technology by increasing the number of pixels per processing element (PPE).Currently affiliated with the Department of Electrical Engineering and Computer Science at Vanderbilt University.William H. Robinson is an Assistant Professor in the Department of Electrical Engineering and Computer Science at Vanderbilt University. He received his B.S. in electrical engineering from Florida Agricultural and Mechanical University in 1996 and his M.S. in electrical engineering from the Georgia Institute of Technology (Georgia Tech) in 1998. He received his Ph.D. in electrical and computer engineering from Georgia Tech in 2003. His research explores the system-level integration of computer architecture to understand the impact of technology on architecture design. Topics of interest include computer architecture design, VLSI design, image processing, and mixed-signal integration with applications to portable imaging devices, integrated sensor technology, and system-on-a-chip multimedia processing. He is a member of the IEEE and participates in the Computer Society, the Education Society, and the Lasers and Electro-Optics Society.D. Scott Wills is a Professor of Electrical and Computer Engineering at the Georgia Institute of Technology. He received his B.S. in Physics from Georgia Tech in 1983, and his S.M., E.E., and Sc.D. in Electrical Engineering and Computer Science from M.I.T. in 1985, 1987, and 1990, respectively. His research interests include short wire VLSI architectures, high throughput portable processing systems, architectural modeling for gigascale (GSI) technology, and high efficiency image processors. He is a senior member of the IEEE and the Computer Society and he is an associate editor of IEEE Transactions on Computers.     

Enhancing Transport Layer Capability in HAPS–Satellite Integrated Architecture

The use of HAPS/UAV to enhance telecommunication capabilities has been proposed as an effective solution to support hot spot communications in limited areas. To ensure communication capabilities even in case of emergency (earthquake, power blackout, chemical/nuclear disaster, terrorist attack), when terrestrial fixed and mobile infrastructures are damaged or become unavailable, the access to satellites represents a reliable solution with worldwide coverage, even though it may suffer from shadowing impairment, especially in an urban environment. In this paper we approach an innovative and more challenging architecture foreseeing HAPS/UAV connected to the satellite in order to enlarge coverage and to allow interconnection with very remote locations. In this scenario, we have analysed TCP-based applications proposing some innovative techniques, both at protocol and at architectural level, to improve performance. In particular, we propose the use of a PEP technique, namely splitting, to speed up window growth in spite of high latency, combined with TCP Westwood as a very efficient algorithm particularly suitable and well performing over satellite links.Cesare Roseti graduated cum laude in 2003 in Electronic Engineering at University of Rome “Tor Vergata”. In 2003 and 2004, he was a visiting student at Computer Science Department of University of California, Los Angeles (UCLA). Since 2004 he is a PhD student at the Electronic Engineering Department and his research interests include satellites communications and transport protocols in heterogeneous (wired/wireless) systems.Claudio Enrico Palazzi studied computer science at University of Bologna, Campus of Cesena. He has been a student representative in several bodies of University of Bologna and, in particular, from 2000 to 2001 he was part of the Board of Governors. In 2001, he received the Sigillum Magnum of Alma Mater Studiorum University of Bologna. He graduated cum laude in 2002 with a thesis on transport protocols in wireless environments. In 2003, he was the first student enrolled in the Interlink joint PhD program in computer science by which he is currently a PhD student in Computer Science at both University of Bologna and University of California, Los Angeles (UCLA). His research interests include protocol design, implementation and performance analysis for wired/wireless networks.Michele Luglio received the Laurea degree in electronic engineering from the University of Rome “Tor Vergata”. He received the PhD degree in telecommunications in 1994. From August to December 1992 he worked as visiting staff engineering at Microwave Technology and Systems Division of Comsat Laboratories (Clarksburg, Maryland, USA). He received the Young Scientist Award from ISSSE’95. Since October 1995, he is research and teaching assistant at University of Rome “Tor Vergata” where he works on designing satellite systems for multimedia services both mobile and fixed, in the frame of projects funded by EC, ESA and ASI. He taught signal theory and collaborated in teaching digital signal processing and elements of telecommunications. In 2001 and 2002 he was visiting professor at the Computer Science Department of University of California Los Angeles (UCLA) to teach Satellite Networks class. Now he teaches satellite telecommunications and signals and transmission. He is a member of IEEE.Mario Gerla received a graduate degree in engineering from the Politecnico di Milano in 1966, and the MS and PhD degrees in engineering from UCLA in 1970 and 1973, respectively. After working for Network Analysis Corporation from 1973 to 1976, he joined the Faculty of the Computer Science Department at UCLA where he is now professor. His research interests cover the performance evaluation, design and control of distributed computer communication systems; high-speed computer networks; wireless LANs; and ad hoc wireless networks. He has worked on the design, implementation and testing of various wireless ad hoc network protocols (channel access, clustering, routing and transport) within the DARPA WAMIS, GloMo projects. Currently, he is leading the ONR MINUTEMAN project at UCLA, and is designing a robust, scalable wireless ad hoc network architecture for unmanned intelligent agents in defense and homeland security scenarios. He is also conducting research on QoS routing, multicasting protocols and TCP transport for the Next-Generation Internet (see www.cs.ucla.edu/NRL for recent publications). He became IEEE Fellow in 2002.M. Yahya “Medy” Sanadidi was born in Damanhour, Egypt. He received his high school diploma from College Saint Marc, and his BSc in electrical engineering (computer and automatic control section) from the University of Alexandria, Egypt. Dr. Sanadidi received his PhD in computer science from UCLA in 1982. He is currently a research professor at the UCLA Computer Science Department. As co-principal investigator on NSF-sponsored research, he is leading research in modeling and evaluation of high-performance Internet protocols. He teaches undergraduate and graduate courses at UCLA on queuing systems and computer networks. Dr. Sanadidi was a manager and senior consulting engineer at Teradata/AT&T/NCR from 1991 to 1999 and led several groups responsible for performance modeling and analysis, operating systems, and parallel query optimization. From 1984 to 1991, he held the position of computer scientist at Citicorp, where he pursued R&D projects in wireless metropolitan area data communications and other networking technologies. In particular, between 1984 and 1987, he lead the design and prototyping of a wireless MAN for home banking and credit card verification applications. From 1981 to 1983, Dr. Sanadidi was an assistant professor at the Computer Science Department, University of Maryland, College Park, Maryland. There, he taught performance modeling, computer architecture and operating systems, and was principal investigator for NSA-sponsored research on global data communications networks. Dr. Sanadidi has consulted for industrial concerns, has co-authored conference as well as journal papers, and holds two patents in performance modeling. He participated as reviewer and as program committee member of professional conferences. His current research interests are focused on congestion control and adaptive multimedia streaming protocols in heterogeneous (wired/wireless) networks.James Stepanek received his BS in computer science from Harvey Mudd College in 1994 and his MS in computer science from University of California, Los Angeles (UCLA) in 2001 where he is currently enrolled in the PhD program. He is also currently a member of the technical staff in the Computer Systems Research Department of The Aerospace Corporation. His research interests include wireless and satellite networks.     

A Wide Tuning Range, Fractional Multiplying Delay-Locked Loop Topology for Frequency Hopping Applications

This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1–2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N_C) in which M, k, and N_C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between two consecutive integer numbers. Operating in 2.5 GHz, total circuit including digital part consumes 15.5 mW from 1.8 V supply voltage. At the proposed architecture, reference clock is injected into a ring oscillator in specified times and to the specified delay-stages to synthesize the fractional frequency multiplication as well as resetting the accumulated jitter during previous cycles. Operating in maximum speed, simulated RMS (root-mean-square) and PTP (peak-to-peak) jitter values are 1.8 and 14.5 ps, respectively, while the settling time is 5 us. Armin Tajalli received the B.Sc. from Sharif University of Technology (SUT), Tehran, Iran, in 1997, and M.Sc. from Tehran Polytechnic University, Tehran, Iran, in 1999. From 1998 he has joint Emad Co. as a senior design engineer where he has worked on several industrial and R&D projects on analog and mixed-mode ICs. He received the award of the Best Design Engineer from Emad Co., 2001, the Kharazmi Award of Industrial Research and Development, Iran, 2002, and Presidential Award of the Best Iranian Researchers, in 2003. He is now working toward his Ph.D. degree at SUT. His current interests are design of high speed circuits for telecommunication systems. Pooya Torkzadeh was born in Isfahan, on April 21, 1980. He received the B.Sc. degree from Isfahan University of Technology (IUT), Isfahan, in 2002 and the M.Sc. degree from Sharif University of Technology (SUT), Tehran, in 2004, both in electrical engineering. From 2002 to 2004, he was an Assistant with SUT and the member of Sharif Integrated Circuit And System Group (SICAS). His major activities are in Electronics Integrated Circuit Designing and Digital Signal Processing (DSP). He specializes in CMOS Integrated Circuits particularly for Clock Generation, Clock-Data Recovery Systems, and Sigma-Delta Analogue to Digital Converter Applications. Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Technology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering from the University of California, Irvine, in 1987. He received the Ph.D. degree from the University of Southern California (USC) on the subject of analog IC design in 1993. From 1993 to 1996 he worked with Linear Technology Corporation as a senior analog design engineer. Since then, he has been consulting with different IC companies. He is currently a visiting professor at Sharif University of Technology. He has published more than 30 technical papers in the area of analog and mixed-signal integrated circuit design as well as analog CAD tools.     

Optimization of lithographic masks using genetic algorithms

Due to its cost effectiveness and reliability, wet-chemical etching of silicon is still one of the key technologies for producing bulk-silicon microstructures. In this paper we present an approach for the design of advanced mask sets for anisotropic, wet-chemical etching of silicon. The optimization method of genetic algorithms is used to derive suitable masks for cases where geometrically calculated compensation structures fail. The underlying etch simulation is described as well as the optimization algorithm itself. Design tasks of current research projects are used as examples to illustrate the advantage of using the presented tool. Udo Triltsch was born in Bergisch Gladbach, Germany, in 1976. He received the Dipl.-Ing. degree for Mechanical Engineering from the Technical University of Braunschweig, Germany, in 2002. He is currently working towards his Ph.D. at the Institute for Microtechnology, Braunschweig, Germany. His research interests include: design methodology for MEMS, process simulation and knowledge management. Anurak Phataralaoha was born in Bangkok, Thailand, in 1973. He received the B. Eng. degree for Production Engineering from KMUTT, Thailand in 1995 and Dipl.-Ing. degree for Mechanical Engineering from Technical University of Clausthal, Germany in 2002. He is currently working towards his Ph.D. at the Institute for Microtechnology, Braunschweig, Germany. His research interests include: 3D-tactile sensors, micro machining for silicon, Tribological micro guide. Stephanus Büttgenbach obtained the Diploma and Ph.D. degrees in physics from the University of Bonn, Germany, in 1970 and 1973, respectively. From 1974 to 1985, he was with the Institute of Applied Physics of the University of Bonn, working on atomic and laser spectroscopy. In 1983, he was promoted to Professor of Physics. From 1977 to 1985, he was also a Scientific Associate at CERN in Geneva, Switzerland. In 1985, Dr. Büttgenbach joined the Hahn-Schickard-Society of Applied Research at Stuttgart as Head of the Department of Microtechnology, where he worked on micromechanics, laser microfabrication, and resonant sensors. From 1988 to 1991, he was the Founding Director of the Institute of Micro and Information Technology of the Hahn-Schickard-Society. In 1991, Dr. Büttgenbach became Professor of Microtechnology at the Technical University of Braunschweig. His current research centers on the development and application of micro sensors, micro actuators, and micro systems. Currently, he is Vice President of the Technical University of Braunschweig, where his areas of responsibility are research and technology transfer. Dima Straube was born in Berlin, Germany, in 1977. He received the Dipl.-Ing. degree for Civil Engineering from Technical University of Berlin, Germany, in 2002. He is currently working towards his Ph.D. at the Institute for Engineering Design, Braunschweig. His research interests include: design methodology for MEMS, computer aided design and tolerance management. Hans-Joachim Franke was born in Helmstedt, Germany, on February 14, 1944. He received his diploma in mechanical engineering (Dipl.-Ing.) from the Technical University of Braunschweig, Germany, in 1969. From 1969 to 1976 he was research assistant of Prof. Roth at the Institute for Engineering Design. In 1976 he received his Ph.D. degree in mechanical engineering. From 1976 to 1988 he had diverse executive positions at the KSB-AG in Frankenthal, Germany, a company, which produces pumps and valves. Since 1988 he has been the director of the Institute for Engineering Design of the Technical University of Braunschweig. His research interests are in the areas of design methodology, computer aided design and machine elements.     

Performance Simulation of a Microwave Micro-Electromechanical System Shunt Switch Using Chatoyant

In this paper we demonstrate the capabilities of our mixed-signal, multi-domain system level simulation tool, Chatoyant, to model and simulate an RF MEMS shunt switch. We verify our mechanical simulations and analysis by comparison to results from commercial simulation packages, ANSYS and CoventorWare. We show that our modeling accuracy and simulation speed are comparable to these commercial tools for specific analysis. We conclude by showing the unique capabilities of a system tool based on a modular hierarchal approach that allows one to model not only the individual components of the system but also the subtle interactions resulting in specific system behaviors.Michael Bails received his B.A. in Economics from the University of Vermont in 1995 and a B.S. in Electrical Engineering from the University of Pittsburgh in 2002 (cum laude). He worked as an undergraduate researcher in optical MEMS for Benchmark Photonics, a Pittsburgh-based start-up company from 2001 to 2002. Mr. Bails is currently pursuing his M.S. in the Department of Electrical and Computer Engineering at the University of Pittsburgh, where he is a recipient of the Rath Fellowship. His interests are in MEMS modeling with an emphasis on statistical process variations. Mr. Bails is a student member of IEEE.José A. Martínez is an Electrical Engineering Ph.D. student at the University of Pittsburgh. He received his MS from the University of Pittsburgh (2000) in Electrical Engineering. He received the BS (magna cum laude) in Electrical Engineering from the Universidad de Oriente (UDO), Venezuela, in 1993. Mr. Martínez was granted the José Feliz Rivas’ medal for high academic achievement by the Venezuelan government (1993), and scholarships by the Venezuelan Fundayacucho Society (1993) and CONICIT-UDO (1994) institution. Since 1997 he has been working in the Optoelectronic computing group at the University of Pittsburgh. His research interests include behavioral simulation, reduction order techniques, modeling of MEMs and OMEMs, CAD, VLSI and computer architecture. Mr. Martínez is a member of IEEE/LEOS, and OSA.Steven P. Levitan is the John A. Jurenko Professor of Computer Engineering in the Department of Electrical and Computer Engineering. He received the B.S. degree from Case Western Reserve University in 1972. From 1972 to 1977 he worked for Xylogic Systems designing hardware for computerized text processing systems. He received his M.S. and Ph.D. in Computer Science from the University of Massachusetts, Amherst. During that time he also worked for Digital Equipment Corporation, and Viewlogic Systems, as a consultant in HDL simulation and synthesis. He was an Assistant Professor from 1984 to 1986 in the Electrical and Computer Engineering Department at the University of Massachusetts. In 1987, Dr. Levitan joined the Electrical Engineering faculty at the University of Pittsburgh where he holds a joint appointment in the Department of Computer Science. He is Past Chair of the ACM Special Interest Group on Design Automation (SIGDA). He was awarded the ACM/SIGDA Distinguished Service Award for over a decade of service to ACM/SIGDA and the EDA Industry in 2002. He is on the technical advisory board for The Technology Collaborative. He is a senior member of the IEEE/Computer Society and a member of the Optical Society of America, the Association for Computing Machinery, and the International Society for Optical Engineering. He is a member of the ACM/IEEE Design Automation Conference Executive Committee.Jason Boles received the B.S. degree in computer engineering from the University of Pittsburgh, Pittsburgh, PA, in 2001, where he is currently pursuing the M.S. degree in electrical engineering. His research interests include hardware acceleration techniques for simulation, system level modeling, computer-aided design (CAD), as well as systems-on-chip design and verification. Mr. Boles is a student member of IEEE.Ilya V. Avdeev is currently with ANSYS, Inc (Canonsburg, PA). He received his B.S. and M.S. degrees both in mechanical engineering from St. Petersburg State Polytechnical University (Russia) in 1997 and 1999 respectively. He received his Ph.D. in mechanical engineering from the University of Pittsburgh in 2003. His dissertation was on modeling strongly-coupled MEMS. He has been an inaugural John Swanson Doctoral Fellow and was awarded numerous scholarships and personal grants during his undergraduate and graduate studies. His research interests include mathematical modeling of coupled-field effects, new finite element techniques and methods, design and simulation of MEMS/NEMS, and acoustics. He is a member of ASME and IEEE.Michael R. Lovell is the Associate Dean for Research and an Associate Professor of Industrial and Mechanical Engineering in the School of Engineering at the University of Pittsburgh. Dr. Lovell received his PhD in Mechanical Engineering in 1994 from the University of Pittsburgh. He joined the Mechanical Engineering Department at Pittsburgh in January of 2000 after three years of service as an Assistant Professor at the University of Kentucky and four years of service as a senior development engineer at ANSYS Inc. Professor Lovell is a W. K. Whiteford Endowed Faculty Fellow, has served as the Executive Director of the Swanson Center for Product Innovation since May of 2000, and has been the Director of the Swanson Institute for Technical Excellence since September of 2002. Among his accomplishments, Professor Lovell is a recipient of the NSF CAREER award (1997), the SME Outstanding Young Manufacturing Engineer Award (1999), and won the FAG Outstanding International Publication on Bearings (1998). Dr. Lovell’s primary research interests are in the areas of tribology, advanced computation, and micro and nano systems.Donald M. Chiarulli, Professor of Computer Science. Dr. Chiarulli received his BS degree (Physics, 1976) from Louisiana State University, MSc (Computer Science, 1979) from Virginia Polytechnic Institute, and PhD (Computer Science, 1986) from Louisiana State University. He was an Instructor/Research Associate at LSU from 1979 to 1986, and has been at the University of Pittsburgh since 1986. Dr. Chiarulli’s research interests are in photonic and optoelectronic computing systems architecture. Dr Chiarulli’s research has been recognized with Best Paper Awards at the International Conference on Neural Networks (ICNN-98) and the Design Automation Conference (DAC-00). He is also the co-inventor on three patents relating to computing systems and optoelectronics. He has served on the technical program committees of numerous conferences for both research and education issues. Dr. Chiarulli serves on the editorial board of the Journal of Parallel and Distributed Systems and is a member of the IEEE. SPIE, and OSA.     

A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects

During back-end manufacturing process of IC, intervention of spot defects induces extra and missing material of interconnects causing circuit failures. Interconnect narrowing occurs when spot defects induce interconnects missing material without resulting in a complete cut. The narrow sites of defective interconnects favor electromigration that makes narrow interconnects more likely to induce a chip failure than regular interconnects. In this paper, an innovative layout sensitivity model accounting for “narrow” defects is derived. The paper also pioneers estimation of the probability of narrow interconnects in the die. The layout sensitivity model for narrow interconnects is tested and compared to actual and simulated data. Our layout sensitivity model predicts the probability of narrowing with 3.1% error, on average. The model is then combined with electromigration constraints to predict mean-time-to-failure of chips manufactured in future technologies down to 32 nm node. The paper concludes with some other possible applications of the narrow interconnect predictive model.