Run-time demand estimation and modulation of on-chip decaps at system level for leakage power reduction in multicore chips

The leakage power of decaps occupies a large portion of total chip leakage power. In this paper we propose an approximate approach to estimate the amount of the required “on” capacitance of each decap at runtime to achieve runtime decap modulation in multicore chips, and further develop two techniques (incremental calculation and sparsification) to improve the approximate approach. Results on a set of benchmarks show that our approach can achieve about 45% saving in decap leakage on average, and the approximate approach can further reduce the computation cost by up to 22× with accuracy loss of less than 1%.     

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs

Control of on-chip power supply noise has become a major challenge for continuous scaling of CMOS technology. Conventional passive decoupling capacitors (decaps) exhibit significant area and leakage penalties. To improve the efficiency of power supply regulation, this paper proposes a distributed active decap circuit for use in digital integrated circuits (ICs). The proposed design uses an operational amplifier to boost the performance of conventional decaps. Simulations proved its enhanced decoupling effect in comparison with passive decaps. The proposed active decap also shows advantages in providing additional damping to the on-chip resonant noise. To verify the performance from the proposed circuit, a 0.18-$mu$ m test chip with on-chip noise generators and sensors has been fabricated. Measurements show a 4-11$times$ boost in decap value over conventional passive decaps for frequencies up to 1 GHz with a total area saving of 40%. Local supply noise distribution and decap gating capability were also examined from the test chip.      

Partitioning-based decoupling capacitor budgeting via sequence of linear programming

In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) as the optimization engine, and partitioning scheme for dealing with large-sized circuits. We show that by directly optimizing the decoupling capacitor (decap) areas as the objective function and using the time-domain adjoint method, SLP can deliver much better quality in terms of decap budget than existing methods based on the merged time-domain adjoint method. The partitioning strategy further improves the scalability of the proposed algorithm and makes it efficient for larger circuits. The resulting algorithm is general enough for any P/G network. Experimental results demonstrate the advantage of the proposed method over existing state-of-the-art methods in terms of solution quality at a mild computation cost increase.     

Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity

Leakage power is becoming the dominant component of chip power consumption with continued CMOS scaling. An important but commonly unnoticed fact is that leaky transistors act as resistors that help dampen the mid-frequency power supply noise. This paper focuses on the damping effect of various on-chip current components including the leakage current which becomes significant in scaled technologies. By developing physics-based damping models for active and leakage currents, we show that leakage, particularly gate tunneling leakage, provides more damping than strong-inversion current. The proposed models were validated in a 32-nm predictive CMOS technology under process–voltage–temperature (PVT) variations. Examples on large circuits such as SRAM caches are shown to illustrate the application of the proposed model. Simulation results show that the leakage induced damping effect can compensate the speed degradation at high temperatures by 7% or offer 61% saving in decap area and leakage power.      

Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors

The interaction between substrate and devices is normally neglected during the design of on-chip MOS decoupling capacitors (decaps). However, it may significantly influence the decap performance to reduce high-frequency power supply noise. In this paper we propose a novel six-parameter analytical decap model which accounts for substrate and device interactions. Our model has been compared against state-of-the-art decap models. Moreover, it has been extensively validated through simulations and measurements. For 65 nm LP-CMOS, a close correlation has been obtained over a large frequency range from 10 MHz up to 10 GHz. Furthermore, we introduce the maximum decap admittance as a new metric for decap performance qualification. Closed-form expressions have been derived to calculate maximum admittance. Finally, we determine the relationship between relevant figure-of-merit parameters for decap design optimization.     

A combined gate replacement and input vector control approach for leakage current reduction

Input vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage of internal gates at high logic levels. In this paper, we propose a technique to overcome this limitation by replacing those internal gates in their worst leakage states by other library gates while maintaining the circuit's correct functionality during the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction when the MLV is not effective. We then present a divide-and-conquer approach that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits. Our experimental results on all the MCNC91 benchmark circuits reveal that 1) the gate replacement technique alone can achieve 10% leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; and 3) compared with the leakage achieved by optimal MLV in small circuits, the gate replacement heuristic and the divide-and-conquer approach can reduce on average 13% and 17% leakage, respectively.     

Optimal wire sizing and buffer insertion for low power and ageneralized delay model

We present efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion. Our algorithms are able to minimize a cost function subject to given timing constraints; we focus on minimization of dynamic power dissipation, but the algorithm is also easily adaptable to, for example, area minimization. In addition, the algorithm efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility. An extension of our basic algorithm accommodates a generalized delay model which takes into account the effect of signal slew on buffer delay which can contribute substantially to overall delay. To the best of our knowledge, our approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality. The effectiveness of these methods is demonstrated experimentally     

Power/Ground Network Optimization Considering Decap Leakage Currents

In this brief, the authors take a first look at the leakage effects of decaps in power/ground (P/G) grid optimization. Through the use of an approximate leakage current model, it is revealed that simple usage of the leakage model in traditional optimization methods cannot help in reducing noises on P/G grids, and it even hurts power consumption due to overadded decaps. Therefore, it is necessary to develop an efficient method to budget decaps when leakage effect is considered. Here, a new two-stage approach to solve this problem is proposed. Experimental results demonstrate the effectiveness of our new method     

Duet: an accurate leakage estimation and optimization tool fordual-Vt circuits

Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, the method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual V_t processes. The approach is the first to consider the assignment of both the V_t and the width of a transistor, simultaneously. The optimization approach uses incremental calculation of leakage and performance sensitivities and can take into account a partially defined circuit state constraint for the standby mode of the device     

Multi-objective module placement for 3-D system-on-package

System-on-package (SOP) is a viable alternative to system-on-chip (SOC) for meeting the rigorous requirements of today's mixed-signal system integration. Thermal integrity is arguably the most crucial issue in three-dimensional (3-D) SOP due to the compact nature of the 3-D integration. In addition, the power supply noise issue becomes more serious as the supply voltage continues to decrease while the number of active devices consuming power increases. We propose a 3-D module and decap (decoupling capacitance) placement algorithm that evenly distributes the thermal profile and reduces the power supply noise. In addition, we allocate white spaces around the modules that require decaps to suppress the power supply noise while minimizing the area overhead. In our experimentation, we achieve improvements in both maximum temperature and decap amount with only small increase in area, wirelength, and runtime.     

Leakage power analysis and reduction during behavioral synthesis

This paper presents a high-level leakage power analysis and reduction algorithm. The algorithm uses device-level models for leakage to precharacterize a given register-transfer level module library. This is used to estimate the power consumption of a circuit due to leakage. The algorithm can also identify and extract the frequently idle modules in the datapath, which may be targeted for low-leakage optimization. Leakage optimization is based on the use of dual threshold voltage (V/sub T/) technology. The algorithm prioritizes modules giving a high-level synthesis system an indication of where most gains for leakage reduction may be found. We tested our algorithm using a number of benchmarks from various sources. We ran a series of experiments by integrating our algorithm into a low-power high-level synthesis system. In addition to reducing the power consumption due to switching activity, our algorithm provides the high-level synthesis system with the ability to detect and reduce leakage power consumption, hence, further reducing total power consumption. This is shown over a number of technology generations. The trend in these generations indicates that leakage becomes the dominant component of power at smaller feature size and lower supply voltages. Results show that using a dual-V/sub T/ library during high-level synthesis can reduce leakage power by an average of 58% for the different technology generations. Total power can be reduced by an average of 15.0%-45.0% for 0.18-0.07 /spl mu/m technologies, respectively. The contribution of leakage power to overall power consumption ranges from 22.6% to 56.2%. Our approach reduced these values to 11.7%-26.9%.     

A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structure

Optimization of leakage power is essential for nanoscale CMOS (nano-CMOS) technology based integrated circuits for numerous reasons, including improving battery life of the system in which they are used as well as enhancing reliability. Leakage optimization at an early stage of the design cycle such as the register-transfer level (RTL) or architectural level provides more degrees of freedom to design engineers and ensures that the design is optimized at higher levels before proceeding to the next and more detailed phases of the design cycle. In this paper, an RTL optimization approach is presented that targets leakage-power optimization while performing simultaneous scheduling, allocation and binding. The optimization approach uses a nature-inspired firefly algorithm so that large digital integrated circuits can be effectively handled without convergence issues. The firefly algorithm optimizes the cost of leakage delay product (LDP) under various resource constraints. As a specific example, gate-oxide leakage is optimized using a 45 nm CMOS dual-oxide based pre-characterized datapath library. Experimental results over various architectural level benchmark integrated circuits show that average leakage optimization of 90% can be obtained. For a comparative perspective, an integer linear programming (ILP) based algorithm is also presented and it is observed that the firefly algorithm is as accurate as ILP while converging much faster. To the best of the authors׳ knowledge, this is the first ever paper that applies firefly based algorithms for RTL optimization.     

Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries

Leakage current is of great concern for designs in nanometer technologies. In 90- and 65-nm technologies, subthreshold leakage current dominates total leakage current. For a typical ASIC circuit running at several hundred megahertz frequencies, the subthreshold leakage power can be as high as 60% of total power. An important method for minimizing power in ASIC libraries is reducing leakage current. In this article, a complete automated leakage optimization flow that changes channel lengths and widths with cell delay and active area constraints was discussed. Optimization results show that there is ~30% leakage current reduction with a few percent active area and delay increase. There is increase in dynamic power, but the net total power reduction is significant. A uniform increase of 10% in gate length results in ~35% leakage reduction at the cost of ~12% delay degradation. The total cell area changes are minimal in both cases. The optimization flow begins with SPICE net lists from an existing library, optimizes leakage currents subject to performance metrics and active area increase constraints, and finishes with new layout generation and characterization. Investigations indicate that the leakage optimization has little impact on cell noise margin and layout parasitic modifications do not affect optimization results. The efficient automatic layout-to-layout cell leakage optimization flow is most suitable for leakage minimization and library migration for 90- and 65-nm ASIC libraries. Future work includes applying the flow to situations where layout-dependent DFM and process variation objective functions are also optimized     

Bus encoding for total power reduction using a leakage-aware buffer configuration

Power consumption, particularly runtime leakage, in long on-chip buses has grown to be an unacceptable portion of the total power budget due to heavy buffer insertion used to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We utilize a buffer design approach with a selective use of high-threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.     

基于近似计算技术的FPRM电路面积优化

近似计算技术通过降低电路输出精度实现电路功耗、面积、速度等方面的优化.本文针对RM（Reed-Muller）逻辑中"异或"运算特点，提出了基于近似计算技术的适合FPRM逻辑的电路面积优化算法，包括基于不相交运算的RM逻辑错误率计算方法，及在错误率约束下，有利于面积优化的近似FPRM函数搜索方法等.优化算法用MCNC（Microelectronics Center of North Carolina）电路进行测试.实验结果表明，提出的算法可以处理输入变量个数为199个的大电路，在平均错误率为5.7%下，平均电路面积减少62.0%，并在实现面积优化的同时有利于实现电路的动态功耗的优化且对电路时延影响不大.     

体声波双工器的优化设计方法

体声波(BAW)双工器中Rx滤波器对Tx滤波器的负载效应,会使Tx滤波器的插入损耗性能退化而带外抑制性能过剩,进而使得BAW双工器性能不佳。为了解决这一问题,提出了一种BAW双工器的优化设计方法。设置BAW双工器中Tx滤波器的串联薄膜体声波谐振器(FBAR)单元谐振区面积,及并联FBAR单元与串联FBAR单元谐振区面积比值为两组优化变量,通过牺牲Tx滤波器过剩带外抑制性能的方式,采用基于梯度的优化算法计算得到了两组优化变量的最终取值。以一个工作在FDD-LTE band 7的BAW双工器优化设计案例展示了该方法的应用流程。优化设计结果的仿真验证表明,Tx滤波器的插入损耗性能从2dB提升至1.1dB,带内波动性能从1dB提升至0.3dB。由此验证了该方法的可行性。     

支持向量机漏电特征模型的电力设施漏电识别

针对电力设施中漏电引起的故障问题,提出了新型的漏电特性分析方法,该方法融合了基于支持向量机的漏电算法模型,实现了电力设施漏电特性的图像采集和A/D转换处理,最后输出后的数据信息通过DSP计算模块进行计算,最终输出电力设施的强电漏电信息或者弱电漏电信息,实现了电力设施漏电信息的识别.该研究将传统技术中的漏电难以分析的问题...     

Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits

Sleep transistor (ST) insertion is a valuable leakage reduction technique in circuit standby mode. Fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improve circuit noise margins. In this paper, we introduce a novel two-phase FGSTI technique which consists of ST placement and ST sizing. These two phases are formally modeled using mixed integer linear programming (MILP) models. When the circuit timing relaxation is not large enough to assign ST everywhere, leakage feedback (LF) gates, which are used to avoid floating states, induce large area and dynamic power overhead. An extended multi-object ST placement model is further proposed to reduce the leakage current and the LF gate number simultaneously. Finally, heuristic algorithms are developed to speed up the ST placement phase. Our experimental results on the ISCAS'85 benchmarks reveal that: 1) the two-phase FGSTI technique achieves better results than the simultaneous ST placement and sizing method; 2) when the circuit timing relaxation varies from 0% to 5%, the multi-object ST placement model can achieve on average 4 $times$-9 $times$ LF gate number reduction, while the leakage difference is only about 8% of original circuit leakage; 3) our heuristic algorithm is 1000 $times$ faster than the MILP method within an acceptable loss of accuracy.      

一种适用于门级网表的混合式静态功耗优化方法

进入深亚微米集成电路设计阶段,静态功耗所占整体功耗的比例快速增大,使之成为当前设计流程中的关键优化步骤。该文提出一种适用于门级网表的混合式静态功耗优化方法。该方法结合了整数规划和启发式算法,以减小电路时序裕量的方式换取电路静态功耗的改善。整体优化流程从一个满足时序约束的设计开始,首先利用整数规划为网表中的逻辑门单元寻找一个较低静态功耗的最优替换单元;其次结合当前所用门单元和最优替换单元的物理和电学参数,按优先级方式逐层替换电路中所有的逻辑门节点;最后利用启发式方法修复可能出现的最大延时违规情况。整体优化流程将在上述步骤中不断迭代直至无法将现有时序裕量转换为功耗的改善。针对通用测试电路的实验结果表明,采用该方法优化后电路静态功耗平均减小10%以上,最高达26%;与其它方法相比,该方法不仅大幅降低了功耗,而且避免了优化后电路最大延时的过度恶化,其最大延时违反量小于5 ps。     

基于循环向量协同优化电路的NBTI效应和泄漏功耗

当晶体管的特征尺寸减小到45 nm时,电路的可靠性已经成为影响系统设计一个关键性因素。负偏压温度不稳定性(NBTI)和泄露功耗引起的电路可靠性现象的主要原因,导致关键门的老化加重,关键路径延迟增加,最终使得芯片失效,影响系统的正常工作。为了缓解NBTI效应和泄露功耗对电路可靠性的影响,延长电路的使用寿命,文中提出了循环向量方法进行协同优化。在ISCAS85基准电路,利用本方法协同优化实验,NBTI效应平均延迟相对改善了10%,泄漏功耗平均降低了15%,证明了循环向量方法的可行性。