Combining synchronous and asynchronous timing schemes for high-performance systems

Globally asynchronous, locally synchronous (GALS) design is emerging as the architecture of choice for certain applications. In a GALS system, the circuitry in each timing domain is locally synchronized, and different clock domains are glued together according to asynchronous communication schemes. This issue of IEEE Design & Test introduces some basic design and validation issues of the GALS architecture. The editorial from the guest editors outlines the scope of this special theme. In addition to the special theme, this issue also includes a special section highlighting the International Test Conference (ITC). Finally, there is a short report of highlights from the 2007 Design Automation Conference held earlier this year.     

Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC

In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchronous design methodologies. In principle, any functional synchronous block can be encapsulated as a locally synchronous island to form a GALS module. There are, however, several important trade-offs and design decisions involved in doing so. Partitioning a design into several GALS compatible modules is still the most difficult task facing GALS system designers. The controlling state machine of a synchronous functional block may need to be enhanced significantly to accommodate varying latencies involved in data transfers between GALS modules.Such design challenges can not be easily generalized, and in this paper, are presented based on the experiences of designing a GALS system that implements a cryptographic algorithm. The example design uses the GALS methodology to improve resistance against cryptographic power attacks. The problem of side channel attacks against hardware implementations of cryptographic algorithms are briefly presented first, and the GALS architecture featuring several countermeasures against such attacks is introduced. The main part of the paper concentrates on the design decisions involved in the development of this architecture.     

A Survey and Taxonomy of GALS Design Styles

Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to market, large SoC designs must integrate many functional blocks with minimal design effort. These blocks are usually designed using standard synchronous methods and often have different clocking requirements. A GALS approach can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries. SoCs may also achieve power savings by clocking different blocks at their minimum speeds. For example, Scott et al. describe the advantages of GALS design for an embedded-processor peripheral bus.     

Special issue on formal methods for globally asynchronous and locally synchronous (GALS) systems

This special issue is based on innovative ideas presented and discussed during the first International Workshop on Formal Methods for Globally Asynchronous and Locally Synchronous Systems (FMGALS) held in conjunction with the Formal Methods in Europe (FME) conference in Pisa, Italy, in the fall of 2003. This one-day workshop was initiated to bring together researchers in the area of formal methods, system design languages, asynchronous hardware design, and GALS design. The event was held in co-operation with ACM SIGDA and ACM SIGARCH. Since this first incarnation, another FMGALS workshop was held in Verona, Italy in 2005. A special issue for that event is already planned. One great outcome of the first workshop is that an FMGALS community has been established through a moderated mailing list. Information and research result exchanges are taking place among the various research communities who are engaged in research aimed at providing theoretical foundations of GALS design, industrial GALS design practices, and de-synchronization theory proposed by the Synchronous Programming community. Selected papers from the 2003 workshop were invited for this special issue together with an open call for papers soliciting novel contributions on the topics of this conference. Rigorous reviews of 12 submissions led to the selection of five papers. In this editorial statement, we outline the premise and the context of this special issue, and briefly introduce the papers selected.     

A Highly Scalable GALS Crossbar Using Token Ring Arbitration

With increases in die size and clock frequency, driving signals across dies is becoming increasingly more difficult. To reduce clock skew and power, the general trend is to use multiple clock domains on a single die, making both synchronous and asynchronous interclock domain communication possible. The 2005 International Technology Roadmap for Semiconductors states that asynchronous global signaling is required to handle multiple clock domains. According to the ITRS, the globally asynchronous, locally synchronous (GALS) methodology should address this problem. This methodology enables the use of a clocked design for smaller-scale functional units, and this has been the standard approach in industry. The GALS methodology also makes it possible to connect synchronous functional units using robust asynchronous interconnects. The efficient design of an asynchronous crossbar is one of the most promising implementations of the GALS methodology. In this article, we present a low-latency crossbar that uses a distributed arbitration mechanism in the form of token rings. We further improve the latency of this implementation by implementing asynchronous-to-synchronous and synchronous-to-asynchronous interface logic using bidirectional signals. These signals serve as requests and acknowledges, and they exhibit a very fast GasP-like implementation - although, unlike GasP, this implementation is not self-resetting.     

异步微处理器设计方法研究

随着半导体工艺的发展,同步微处理器面临的时钟分布、功耗、设计复杂性等问题日益突出,异步微处理器得到广泛的研究和关注。在分析异步握手协议与控制部件的基础上,总结了异步微处理器设计的主要方法,详细阐述了异步控制器综合、基于传统同步设计工具的异步设计方法、去同步技术等热点问题,并介绍了典型的异步微处理器。     

Formal modelling and verification of GALS systems using GRL and CADP

A GALS (Globally Asynchronous, Locally Synchronous) system consists of several synchronous components that evolve concurrently and interact with each other asynchronously. The design of GALS systems is tedious and error-prone due to the high degree of synchronous and asynchronous concurrency present in complex architectures. In this paper, we present GRL (GALS Representation Language), a formal language designed to model GALS systems, for the purpose of formal verification of the asynchronous aspects. GRL combines the synchronous reactive model underlying dataflow languages and the asynchronous concurrent model underlying process algebras. We propose a translation from GRL to LNT, a value-passing concurrent language with classical process algebra flavour. This makes possible the analysis of GRL specifications using all the state-of-the-art simulation and verification functionalities provided by the CADP toolbox.     

Design of asynchronous circuits using synchronous CAD tools

Poor CAD support hinders wide acceptance of asynchronous methodologies, and asynchronous design tools are far behind synchronous commercial tools. A new design flow, NCL_X, based entirely on commercial CAD tools, targets a subclass of asynchronous circuits called null convention logic. NCL_X shows significant area improvement over other flows for this subclass     

Asynchronous interconnect for synchronous SoC design

System-on-chip (SoC) designs integrate a variety of cores and I/O interfaces, which usually operate at different clock frequencies. Communication between unlocked clock domains requires careful synchronization, which inevitably introduces metastability and some uncertainty in timing. Thus, any chip with multiple clock domains is already globally asynchronous. We have devised a more elegant and efficient solution to the multiple-clock-domain problem. Instead of gluing synchronous domains directly to each other with clock-domain bridges, we use asynchronous-circuit design techniques to handle all clock-domain crossing as well as all cross-chip communication and routing. The phase-locked loop (PLL) and clock distribution can be entirely local to each synchronous core, easing timing closure and improving the reusability of cores across multiple designs. Our solution, Nexus, is a globally asynchronous, locally synchronous (GALS) interconnect that features a 16-port, 36-bit asynchronous crossbar. The crossbar connects through asynchronous channels to clock-domain converters for each synchronous module. To ensure that Nexus will work robustly in a commercial application, we developed and applied many verification and test strategies, including novel variations of noise analysis, timing analysis, and fault and delay testing.     

异步电路的计算机辅助设计软件

异步电路由于没有时钟频率的限制,所以较同步电路有很多优点,其研究也越来越广泛,是未来解决计算机CPU设计的一种重要方案。异步电路的计算机辅助设计软件代表了异步电路当前研究的前沿,通过研究这些软件可以对异步电路的模型有更为深入的认识。论文整理列举了有关异步电路的63种软件工具,并将其分为设计、仿真、相关设计工具、前端设计、综合和验证6个方面。最后,在这些软件中选取两种设计软件对一个简单的例子进行了设计实现,以体现异步电路的设计特点。     

A Framework for Modeling the Distributed Deployment of Synchronous Designs

Synchronous specifications are appealing in the design of large scale hardware and software systems because of their properties that facilitate verification and synthesis.When the target architecture is a distributed system, implementing a synchronous specification as a synchronous design may be inefficient in terms of both size (memory for software implementations or area for hardware implementations) and performance. A more elaborate implementation style where the basic synchronous paradigm is adapted to distributed architectures by introducing elements of asynchrony is, hence, highly desirable. Building on the tagged-signal model, we present a modeling for the distributed deployment of synchronous design. We offer a comparative exposition of various design approaches (synchronous, asynchronous, GALS, latency-insensitive, and synchronous programming) and we provide some insight on the role of signal absence in modeling synchronization in distributed concurrent systems. Finally, we compare two distinct methodologies, desynchronization and latency-insensitive design, and we elaborate on possible options to combine their results. This research was supported in part by the NSF under the project ITR (CCR-0225610), the Gigascale System Research Center (GSRC), and by the European Commission under the projects COLUMBUS, IST-2002-38314, and ARTIST, IST-2001-34820.     

Simulating asynchronous hardware on multiprocessor platforms: the case of AMULET1

Synchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Hence, recently, there has been a resurgence of interest in asynchronous digital design techniques which promise to liberate digital design from the inherent problems of synchronous systems. This activity has revealed a need for modelling and simulation techniques suitable for the asynchronous design style. The concurrent process algebra communicating sequential processes (CSP) and its executable counterpart, occam, are increasingly advocated as particularly suitable for this purpose. This paper focuses on issues related to the execution of CSP/occam models of asynchronous hardware on multiprocessor machines, including I/O, monitoring and debugging, partition, mapping and load balancing. These issues are addressed in the context of occarm, an occam simulation model of the AMULET1 asynchronous microprocessor; however, the solutions devised are more general and may be applied to other systems too. Copyright © 2001 John Wiley & Sons, Ltd.     

Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor

Multiple clock domains is one solution to the increasing problem of propagating the clock signal across increasingly larger and faster chips. The ability to independently scale frequency and voltage in each domain creates a powerful means of reducing power dissipation. A multiple clock domain (MCD) microarchitecture, which uses a globally asynchronous, locally synchronous (GALS) clocking style, permits future aggressive frequency increases, maintains a synchronous design methodology, and exploits the trend of making functional blocks more autonomous. In MCD, each processor domain is internally synchronous, but domains operate asynchronously with respect to one another. Designers still apply existing synchronous design techniques to each domain, but global clock skew is no longer a constraint. Moreover, domains can have independent voltage and frequency control, enabling dynamic voltage scaling at the domain level.     

同步FTP上载／下载程序的实现技术

通常意义上的FTP（文件传输协议）客户程序都是指纯粹的异步上载／下载程序，但在实际应用开发中，FTP功能往往需要与特定的应用相结合，对于某些特殊的应用，通常的异步FTP程序设计方法不适用系统的需求，需要设计同步的FTP上载／下载程序，但开发工具如VB不提供直接的同步FTP支持。文章结合实际的系统开发，探讨了在特定应用中实现同步FTP上载／下载程序的方法和技术。     

SystemJ: A GALS language for system level design

In this paper we present the syntax, semantics, and compilation of a new system-level programming language called SystemJ. SystemJ is a multiclock language supporting the Globally Asynchronous Locally Synchronous (GALS) model of computation. The synchronous reactive (SR) model is used for synchronous parts of the modelled system, and those parts, which represent individual clock-domains, are coupled asynchronously each to the other on the top-level of system design. SystemJ is based on Java language, which is used to describe “instantaneous” data transformations. Hence, SystemJ is well suited for both software-based embedded and distributed systems. SystemJ offers effective modelling of (1) data transformations through the power of Java, (2) control and synchronous concurrency through the SR paradigm and (3) asynchronous concurrency through clock domains and rendezvous. The language is based on semantics that is amenable to efficient code generation and partial automatic verification. The SystemJ micro-step semantics provide asynchronous and synchronous extensions over the semantics of other SR languages such as Esterel and provide an ideal platform for efficient software implementation.     

Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale

It is with great pleasure that we introduce this special issue on Advanced Technologies and Reliable Design for Nanotechnology Systems to the IEEE Design & Test readership. We have selected four articles to cover a wide spectrum of techniques and applications for the reliable design of nanoscale systems; the techniques aim to circumvent the high defect rates and transient errors expected in advanced nanoscale technologies. Written by outstanding researchers in the field, these articles cover experimental and speculative topics. As with all special issues, these topics only represent the techniques and methodologies available today.     

A GALS Infrastructure for a Massively Parallel Multiprocessor

This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking concerns for different parts of the die, leading to greater power efficiency.     

Communication Issues in the Design and Analysis of Parallel Algorithms

As multiple processor systems become more widely accepted the importance of parallel programming increases. In this paper, approaches to the design and analysis of parallel algorithms are investigated. Through several examples, the importance of interprocessor communication in parallel processing is demonstrated. Various techniques that are applicable in the design and analysis of parallel algorithms are examined with emphasis on those techniques that incorporate communication aspects. The paper discusses several models of synchronous and asynchronous parallel computation and their use in analyzing algorithms. Relatively primitive methodologies for designing parallel algorithms are discussed and the need for more general and practical methodologies is indicated.     

VLSI asynchronous systems: specification and synthesis

Most of today's digital systems are realized using synchronous (i.e. globally clocked) VLSI circuits. For many reasons, it is becoming increasingly hard to build large synchronous circuits. Although several techniques for building non-clocked (i.e. asynchronous) sequential circuits have been known for some time, they have been largely ignored by the digital design community. Recently, however, asynchronous circuits have been enjoying a revival. After reviewing recent research in this area, we take a simple collection of examples and, through them, explain our design system for specifying and synthesizing asynchronous circuits. We show that by being able to work in a framework where circuit activities do not have to coincide with clock pulses, designers obtain several avenues for circuit optimization that are highly promising for creating efficient and modularly expandable circuits.