Low-Temperature Silicon-to-Silicon Anodic Bonding Using Sodium-Rich Glass for MEMS Applications

In the present work, silicon-to-silicon anodic bonding has been accomplished using an intermediate sodium-rich glass layer deposited by a radiofrequency magnetron sputtering process. The bonding was carried out at low direct-current voltage of about 80 V at 365°C. The alkali ion (sodium) concentration in the deposited film, the surface roughness of the film, and the flatness of the silicon wafers were studied in detail and closely monitored to improve the bond strength of the bonded silicon wafers. The effect of chemical mechanical polishing (CMP) on the surface roughness of the deposited film was also investigated. The average roughness of the deposited film was found to be ~6 Å, being reduced to 2 Å after CMP. It was observed that the concentration of sodium ions in the deposited film varied significantly with the sputtering parameters. Scanning electron microscopy was used to obtain cross-sectional images of the bonded pair. The bonding energy of the bonded wafer pair was measured using the crack-opening method. The bonding energy was found to vary from 0.3 J/m² to 2.1 J/m² for different bonding conditions. To demonstrate the application of the process developed, a sealed cavity was created using the silicon-to-silicon anodic bonding technique, which can be used for fabrication of devices such as capacitive pressure sensors and Fabry– Perot-based pressure sensors. Also, a matrix of microwells was fabricated using this technique, which can be used in various biomicroelectromechanical system applications.     

Thin-film transistors on plastic and glass substrates using silicon deposited by microwave plasma ECR-CVD

Thin-film transistors (TFTs) were fabricated on polyimide and glass substrates at low temperatures using microwave ECR-CVD deposited amorphous and nanocrystalline silicon as active layers. The amorphous Si TFT fabricated at 200 /spl deg/C on the polyimide foil had a saturation region field effect mobility of 4.5 cm/sup 2//V-s, a linear region mobility of 5.1 cm/sup 2//V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/decade, and an ON/OFF current ratio of 7.9 /spl times/ 10/sup 6/. This large mobility and high ON/OFF current ratio were attributed to the high-quality channel materials with less dangling bond defect states. Nanocrystalline Si TFTs fabricated on glass substrates at 400 /spl deg/C showed a saturation region mobility of 14.1 cm/sup 2//V-s, a linear region mobility of 15.3 cm/sup 2//V-s, a threshold voltage of 3.6 V, and an ON/OFF current ratio of 6.7 /spl times/ 10/sup 6/. TFT performance was mostly independent of substrate type when fabrication conditions were the same.     

Tensile tests of micro anchors anodically bonded between Pyrex glass and aluminum thin film coated on silicon wafer

Micro anchor is a kind of typical structures in micro/nano electromechanical systems (MEMS/NEMS), and it can be made by anodic bonding process, with thin films of metal or alloy as an intermediate layer. At the relative low temperature and voltage, specimens with actually sized micro anchor structures were anodically bonded using Pyrex 7740 glass and patterned crystalline silicon chips coated with aluminum thin film with a thickness comprised between 50 nm and 230 nm. To evaluate the bonding quality, tensile pulling tests have been finished with newly designed flexible fixtures for these specimens. The experimental results exhibit that the bonding tensile strength increases with the bonding temperature and voltage, but it decreases with the increase of the thickness of Al intermediate layer. This kind of thickness effect of the intermediate layer was not mentioned in the literature on anodic bonding.     

Room-temperature CW operation of InGaAsP lasers on Si fabricated by wafer bonding

1.3-/spl mu/m InGaAsP-InP lasers have been successfully fabricated on Si substrates by wafer bonding with heat treatment at 400/spl deg/C. A pressure of 4 kg/cm/sup 2/ has been applied on the wafers before the heat treatment and this pressure application has enabled us to achieve bonding strength required for the device fabrication even when the bonding temperature is as low as 400/spl deg/C. Room-temperature continuous-wave operation with threshold current of 49 mA has been achieved for 7-/spl mu/m-wide mesa lasers.     

High-Pressure Oxidation for Thin Gate InsuIator Process

High-pressure oxidation of silicon was performed at a pressure of 8.9 kg/cm/sup 2/ at a temperature range of 650 to 950/spl deg/C. The oxidation temperature dependence of the film density, refractive index, chemical etching rate, and residual stress was measured. The film density of the oxide film was found to increase with decreasing oxidation temperature. The refractive index of the film also increased with decreasing oxidation temperature. The residual stress was found to be dependent on the oxidation temperature. The dielectric breakdown strength of the oxide film was measured by the voltage ramping method. The defect density of the oxide film calculated from the distribution of dielectric breakdown strength slightly decreased with decreasing oxidation temperature. The surface-state density of the oxide film was about 1.1 X 10/sup 11/ cm/sup -2/ throughout the oxidation temperature range. The oxide grown on a doped polysilicon layer at a temperature of 750/spl deg/C was five times as thick as the oxide simultaneously grown on the silicon substrate. The high-pressure and low-temperature oxidation was applied to the fabrication process of a device with a double polysilicon layer structure.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

High-performance poly-Si TFTs on plastic substrates using a nano-structured separation layer approach

We demonstrate a manufacturable, large-area separation approach for producing high-performance polycrystalline silicon thin-film transistors on flexible plastic substrates. The approach allows the use of high growth-temperature gate oxides and removes the need for hydrogenation. The process flow starts with the deposition of a nano-structured high surface-to-volume ratio film on a reuseable "mother" substrate. This film functions as a sacrificial release layer and is Si-based for process compatibility. After high-temperature TFT fabrication (up to 1100/spl deg/C) is carried to completion on the sacrificial film coated mother substrate, a thick plastic top layer film is applied, and the sacrificial layer is removed by chemical attack. By using this separation process, the temperature, smoothness, and mechanical limitations posed by plastic substrates are completely circumvented. Both excellent n-channel and p-channel TFTs on plastic have been produced. We report here on p-channel TFTs on separated plastic with a linear field effect (hole) mobility of 174 cm/sup 2//V/spl middot/s, on/off current ratio of >10/sup 8/ at V/sub ds/=-0.1 V, off current of <10/sup -11/ A//spl mu/m-channel-width at V/sub ds/=-0.1 V, sub-V/sub t/ swing of /spl sim/200 mV/dec, and threshold voltage of -1.1 V.     

Room-temperature microfluidics packaging using sequential plasma activation process

A sequential plasma activation process consisting of oxygen reactive ion etching (RIE) plasma and nitrogen radical plasma was applied for microfluidics packaging at room temperature. Si/glass and glass/glass wafers were activated by the oxygen RIE plasma followed by nitrogen microwave radicals. Then, the activated wafers were brought into contact in atmospheric pressure air with hand-applied pressure where they remained for 24 h. The wafers were bonded throughout the entire area and the bonding strength of the interface was as strong as the parents bulk wafers without any post-annealing process or wet chemical cleaning steps. Bonding strength considerably increased with the nitrogen radical treatment after oxygen RIE activation prior to bonding. Chemical reliability tests showed that the bonded interfaces of Si/Si could significantly withstand exposure to various microfluidics chemicals. Si/glass and glass/glass cavities formed by the sequential plasma activation process indicated hermetic sealing behavior. SiO/sub x/N/sub y/ was observed in the sequentially plasma-treated glass wafer, and it is attributed to binding of nitrogen with Si and oxygen and the implantation of N/sub 2/ radical in the wafer. High bonding strength observed is attributed to a diffusion of absorbing water onto the wafer surfaces and a reaction between silicon oxynitride layers on the mating wafers. T-shape microfluidic channels were fabricated on glass wafers by bulk micromachining and the sequential plasma-activated bonding process at room temperature.     

5 V temperature regulated voltage reference

A 5 V internally temperature regulated voltage reference integrated circuit, which achieves 0.3 ppm//spl deg/C TC over the temperature range -55/spl deg/C to 125/spl deg/C, is described. It is built using a buried zener reference in a dielectrically isolated complementary bipolar process which employs laser trimmed NiCr thin film resistors and a high thermal resistance epoxy die attach.     

CMOS integrated silicon pressure sensor

The sensor described includes a four-arm piezoresistance bridge circuit, an amplifier, and a bridge excitation circuit. This circuit is used to stabilize changes in sensitivity due to variations in temperature and supply voltage. The sensor was fabricated using a self-aligned double-poly Si gate p-well CMOS process combined with an electrochemical etch-stop technique using N/SUB 2/H/SUB 4/-H/SUB 2/O anisotropic etchant for the thin-square diaphragm formation. The silicon wafer was electrostatically adhered to a glass plate to minimize thermally induced stress. Less than a /spl plusmn/0.5% sensitivity shift and less than a /spl plusmn/5-mV offset shift were obtained in the 0-70/spl deg/C range, with a 1-V/kg/cm/SUP 2/ pressure sensitivity. By using a novel excitation technique, a sensitivity change of less than /spl plusmn/1.5% under a /spl plusmn/10% supply voltage variation was also achieved.     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Effective cleaning process and its influence on surface roughness in anodic bonding for semiconductor device packaging

Wafer cleanliness and surface roughness play a paramount role in an anodic bonding process. Impurities and the roughness on the wafer surface result in unbonded areas which lead to fringes and Newton׳s rings. With an augment in surface roughness, lesser area will be in stroke thus making more pressure and voltage to be applied onto the wafers for better bonding. Eventually it became mandatory to choose the best cleaning process for the bonding technology that can substantially reduce the impurities and surface roughness. In this paper, we investigate the bonding of silicon/oxidized silicon on Pyrex (CORNING 7740) glass with respect to surface roughness and cleanliness of the wafers by performing three renowned cleaning processes such as degreasing, piranha, RCA 1& 2 (SC‐Standard Cleaning 1 and 2) and found that RCA compromises the best between the roughness and cleanliness. Studies were also extended to find out the effects of applied voltage and load on the bonded surface. It was observed for samples cleaned with RCA, an increase of 45% in maximum current and decrease of 75% in total bonding time with the applied load and voltage among all the cleaning techniques used. Three dimensional structures for pressure sensor application were successfully bonded by selecting the appropriate load and cleaning process. Atomic force microscopy analysis was done to investigate the surface roughness on silicon/oxidized silicon and Pyrex glass for different cleaning processes. Scanning electron microscopy and optical imaging were performed on the interface for the surface integrity of the bonded samples.     

Analysis, design, and performance of micropower circuits for a capacitive pressure sensor IC

An integrated circuit has been designed, built, and testing as part of a capacitive pressure transducer. High-accuracy compact micropower circuits utilizing a standard bipolar IC process without any special components or trimming are used. The key circuits for achieving this performance are a Schmitt trigger oscillator and a bandgap voltage reference. The sensor circuits consume 200 /spl mu/W at 3.5 V, can resolve capacitance changes of 300 p.p.m., measure temperature to /spl plusmn/0.1/spl deg/C over a limited temperature range, and presently occupy 4 mm/SUP 2/ on a 2 mm/spl times/6 mm implantable monolithic silicon pressure sensor. Further scaling of the sensor is discussed showing that a reduction of area by a factor of 4 is achievable.     

Silicon-to-steel bonding using rapid thermal annealing

This paper presents the rapid, low-temperature bonding between silicon and steel using the rapid thermal annealing process. Three different thin-film adhesion layer systems including silver, gold, and nickel were utilized as the intermediate bonding material to assist the eutectic Pb/Sn bonding between silicon and steel. The bonding temperature was set at 220/spl deg/C for 20 s, with a 20-s ramp-up time. Five experiments were conducted to determine the strength of the bond, including static tensile and compressive four-point bend tests, axial extension tests, tensile bending fatigue tests, and corrosion resistance tests. The test results have shown that the gold adhesion layer is the most robust, demonstrating minimal creep during fatigue tests, no delamination during the tensile or compressive four-point bend tests, and acceptable strength during the axial extension tests. Additionally, all adhesion layers have withstood four months of submersion in various high-temperature solutions and lubricants without failure. Simulations of the axial stresses and strains that developed during the four-point bend and axial extension tests were performed and showed that the presence of the silicon die provides a local reinforcement of the bond as observed in the experimental tests.     

MOS voltage reference based on polysilicon gate work function difference

A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.     

Photoresist deposition without spinning

A technique for resist deposition using a novel fluid ejection method is presented in this paper. An ejector has been developed to deposit photoresist on silicon wafers without spinning. Drop-on-demand coating of the wafer reduces waste and the cost of coating wafers. Shipley 1400-21, 1400-27, 1805, and 1813 resists were used to coat sample 3- and 4-in wafers. Later, these wafers were exposed and developed. The deposited resist film was 3.5 /spl mu/m thick and had a surface roughness of about 0.2 /spl mu/m. The ultimate goal is to deposit resist films with a thickness of the order of 0.5 /spl mu/m and a surface roughness of the order of 30 /spl Aring/, which is currently achieved for 200-mm silicon wafers by using a spinning method. Such goals can be attained by using micromachined multiple ejectors or with better control over the deposition environment. In the micromachined configuration, thousands of ejectors are made into a silicon die, as presented by Percin et al. (2002), and thus allow for a full coating of a wafer in a few seconds. Coating in a clean environment will allow the lithography of circuits for microelectronic applications. Other potential applications for the technology in the semiconductor manufacturing are in deposition of low-k materials, wafer cleaning, manufacturing of organic LEDs and organic FETs, direct lithography, nanolithography, and coating for hard-disk drives.     

Memory characteristics of MOSFETs with densely stacked silicon nanocrystal Layers in the gate oxide synthesized by low-energy ion beam

Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO/sub 2/ layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of /spl sim/ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 10/sup 5/ W/E cycles even at a high operation temperature of 150/spl deg/C. They also have good retention characteristics with an extrapolated ten-year memory window of /spl sim/ 0.3 V at 100/spl deg/C.     

1 V CMOS current reference with 50 ppm//spl deg/C temperature coefficient

A CMOS current reference circuit is presented, which can work properly with a supply voltage higher than 1 V. By compensating the temperature performance of the resistor, this circuit gives out a current with a temperature coefficient of 50 ppm//spl deg/C over the temperature range of (0/spl deg/C, 110/spl deg/C) and a 0.5% variation for a supply voltage of 1 to 2.3 V.     

Interfacial microstructures and glass strengthening in anodic-bonded Al sheet/glass and sputtered Al film/glass

Two anodic bond interfaces were fabricated at 300 °C, between glass and either an Al sheet or a sputter-deposited Al film, and their microstructures and bending strengths were comparatively studied. In the Al sheet/glass interface, numerous local intrusions of crystalline Al₂O₃ with a long (100–350 nm) dendritic structure were formed in the glass adjacent to the aluminum. However, in the sputter-deposited Al film/glass interface, a continuous, thin (∼30 nm) amorphous layer with Al-oxide nanocrystals along the interface was present without the formation of dendrites after anodic bonding. The dendritic structures in the Al sheet/glass are attributed to an electrostatic instability imposed by the roughness and local oxidation of the Al sheet surface or, presumably, by microheating via gas discharge at the interface. The bending fracture strength for both types of bonded glasses increased by approximately 1.7 times compared with that of the bare glass due to the interfacial reaction.