Germanium-on-insulator substrates by wafer bonding

Single-crystal Ge-on-insulator (GOI) substrates, made by bonding a hydrogen-implanted Ge substrate to a thermally oxidized, silicon handle wafer, are studied for properties relevant to device fabrication. The stages of the layer transfer process are examined through transmission electron microscopy (TEM) from the initial hydrogen implant through the final Ge film polish. The completed GOI substrate is characterized for film uniformity, surface quality, contamination, stress, defectivity, and thermal robustness using a variety of techniques and found to be acceptable for initial device processing.     

Room temperature wafer bonding of silicon, oxidized silicon, and crystalline quartz

The use of plasma immersion as preparation for room temperature wafer bonding has been investigated. Silicon wafers have been successfully bonded at room temperature after exposure to oxygen or argon plasma. Oxidized silicon wafers and crystalline quartz have been bonded after exposure to oxygen plasma. The bonded interfaces exhibit very high surface energies, comparable to what can be achieved with annealing steps in the range of 600–800°C using normal wet chemical activation before bonding. The high mechanical stability obtained after bonding at room temperature is explained by an increased dynamic in water removal from the bonded interface allowing covalent bonds to be formed. Electrical measurements were used to investigate the usefulness of plasma bonded interfaces for electronic devices.     

Development of reliable low temperature wafer level hermetic bonding using composite seal joint

A reliable composite metal seal comprising both intermetallic compounds (IMC) and solder joints, which are formed by transient liquid phase bonding and soldering respectively, is proposed and demonstrated in wafer level bonding experiments. Hermetic sealing is demonstrated on 8-in. wafers using low volume Cu/Sn materials at process temperatures as low as 280 °C. It is shown that the composite seal is stable when subjected to temperatures of 250 °C, and that it provides better hermeticity and reliability than an IMC seal alone.     

Low temperature bonding technology for 3D integration

3D integration provides a promising solution to achieve system level integration with high function density, small form factor, enhanced transmission speed and low power consumption. Stacked bonding is the key technology to enable the communication between different strata of the 3D integration system. Low temperature bonding approaches are explored in industry to solve the performance degradation issue of the integrated devices. In this paper, various low temperature bonding technologies are reviewed and introduced, as well as the latest developments in world-wide companies and research institutes. The outlook for industrial application is also addressed in the paper.     

Germanium on sapphire by wafer bonding

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 × 10^?6 K^?1) and sapphire (5 × 10^?6 K^?1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm²/V s have been fabricated onto the thick germanium on sapphire layer.     

Microstructure examination of copper wafer bonding

The microstructure morphologies and oxide distribution of copper bonded wafers were examined by means of transmission electron microscopy (TEM) and energy dispersion spectrometer (EDS). Cu wafers exhibit good bond properties when wafer contact occurs at 400°C/4000 mbar for 30 min, followed by an anneal at 400°C for 30 min in N₂ ambient atmosphere. The distribution of different defects showed that the bonded layer became a homogeneous layer under these bonding conditions. The oxidation distribution in the bonded layer is uniform and sparse. Possible bonding mechanisms are discussed.     

微流控分析芯片制作中的低温键合技术

微流控分析芯片制作方法的研究是微流控分析的基础。制作性能良好的微流控分析芯片时,基片与盖片的键合技术十分重要。本文针对近年来发展迅速的低温键合技术,对各种方法进行了评价,并对其发展前景进行了展望。     

Intermediate wafer level bonding and interface behavior

The paper presents a new silicon wafer bonding technique. The high-resolution bonding pad is defined through photolithography process. Photosensitive materials with patternable characteristics are served as the adhesive intermediate bonding layer between the silicon wafers. Several types of photosensitive materials such as SU-8 (negative photoresist), AZ-4620 (positive photoresist), SP341 (polyimide), JSR (negative photoresist) and BCB (benzocylbutene) are tested and characterized for their bonding strength. An infrared (IR) imaging system is established to examine the bonding results. The results indicate that SU-8 is the best bonding material with a bonding strength up to 213 kg/cm² (20.6 MPa) at bonding temperature less than 90 °C. The resolution of bonding pad of 10 μm can be achieved. The developed low temperature bonding technique is particularly suitable for the integration of microstructures and microelectronics involved in MEMS and VLSI packaging processes.     

Benzocyclobutene wafer bonding for III-V nanophotonic guiding structures

An adhesive wafer bonding technique for the fabrication of nanophotonic guiding structures, the design of which consists of a III-V semiconductor core buried in a polymer matrix, is reported. The bonding was realised owing to benzocyclobutene. Nanostructures are perfectly embedded in the void-free matrix to form high density photonic circuits.     

Thin-film devices fabricated with benzocyclobutene adhesive wafer bonding

In this paper, we present and elaborate on die to wafer bonding technology with benzocyclobutene (BCB). This technology allows to fabricate a variety of reliable waferbonded components in a fairly simple way using only standard cleanroom equipment. We demonstrate the fabrication of passive devices such as microring resonators, as well as active components such as lasers and LEDs. We show good performance of these devices by presenting measurements of their characteristics. Furthermore, these devices were subjected to damp-heat testing, demonstrating the good quality of the BCB-bonding procedure. Finally, due to the low thermal conductivity of BCB, thermal management needs some attention. We present an analysis of the thermal problem and suggest a possible solution.     

Integrated GaAs Schottky mixers by spin-on-dielectric wafer bonding

A novel wafer bonding process has been used to integrate high quality GaAs devices on quartz substrates. The method of adhesion by spin-on-dielectric temperature enhanced reflow (MASTER) uses a spin-on-dielectric as a bonding agent to achieve a robust bond that in no way degrades either high frequency performance or reliability. A 585 GHz integrated mixer fabricated using this process has achieved record double-sideband mixer noise temperatures of 1,150 K at room temperature and 880 K at 77 K. Furthermore, the integrated mixers require no mechanical tuning, are easy to assemble, and repeatable. Precise control of the circuit geometry, coupled with the reduction of parasitic elements, allows greater accuracy of computer simulations and will therefore lead to better high frequency performance and bandwidth. This new technology is easily extended to other circuit designs and will allow the development of a new generation of submillimeter-wave integrated circuits     

Vertically coupled microring resonators using polymer wafer bonding

A new technique is presented to make vertically coupled semiconductor microring resonators that eases the fabrication process with devices more robust to ring-to-waveguide misalignments. Single-mode microring optical channel dropping filters are demonstrated for the first time in this configuration with Qs greater than 3000 and an on-resonance channel extinction greater than 12 dB. A 1×4 multiplexer/demultiplexer crossbar array with second-order microrings was also made and exhibited channel-to-channel crosstalk lower than 10 dB     

Heterogeneous silicon integration by ultra-high vacuum wafer bonding

Heterogeneous integration of technologically important materials, such as SiC/Si, GaN/Si, Ge/Si, Si/nano-Si/Si, SiC-on-insulator (SiCOI), and ZrO₂/SiO₂/Si, was successfully made by ultra-high vacuum (UHV) wafer bonding. A unique, UHV bonding unit, especially designed to control interface structure, chemistry, and crystallographic orientation within narrow limits, was used to produce homophase and heterophase planar interfaces. In-situ thin-film-deposition capability in conjunction with the wafer bonding offered even more flexibility for producing integrated artificial structures. Prebonding surface preparation was critically important for the formation of strong bonded interfaces. The substrate-surface morphology was examined by atomic-force microscopy (AFM) prior to bonding. In-situ Auger spectroscopy measurements of surface chemistry were invaluable predictors of bonding behaviors. Plasma processing very effectively cleaned the substrates, achieving a near-perfect interfacial bond at the atomic scale. The integrity of the bonded interfaces was studied in the light of their structural and chemical characteristics analyzed by high-resolution, analytical electron microscopy.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Overlap optimization in semiconductor waveguides by wafer bonding

In this work, we show that the use of a wafer-bonding technique, wherein an inverted half-waveguide structure is bonded on the upright half to form a complete waveguide, optimizes the overlap factor present in three-wave parametric interactions realized in 43m semiconductor waveguides. These optimized waveguides can be used for efficient frequency-mixing devices which detect or emit infrared light.     

Low temperature direct bonding: An attractive technique for heterostructures build-up

Low temperature direct bonding has been used extensively for assembling materials or components in the microelectronics and microsystem industries. We review here some key features of this technique both from the experimental and practical point of views. We give also some indications on the physical and chemical mechanisms involved in this attractive process, to better identify the important parameters impacting the quality and reliability of the technique. We describe mechanisms and report results on Si and SiO₂ bonding processes. Emphasis is put on improvements that allow obtaining strong and high quality bonding in low temperature process. We demonstrate that direct bonding can be applied as well to metal bonding, mainly to obtain conductive bonding, provided an efficient process can be used for surface preparation, e.g. CMP smoothing. More generally we show that direct bonding is well suited for many heterostructures via low temperature process for instance.     

Fabrication of buried corrugated waveguides by wafer direct bonding

A new fabrication method of deeply buried corrugated waveguides is presented. It uses a direct bonding process and allows us to make efficient grating couplers in waveguides. The efficiency of the grating is enhanced by enclosing air in its grooves during the fabrication process. A demonstrator based on a waveguide produced by ion exchange has been fabricated and tested. Theoretical and experimental results are compared     

SOI MOSFET with buried body strap by wafer bonding

Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFET's with effective channel length of 0.17 μm have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact     

用于MEMS器件芯片级封装的金-硅键合技术研究

MEMS器件大都含有可动的硅结构 ,在器件加工过程中 ,特别是在封装过程中极易受损 ,大大影响器件的成品率。如果能在MEMS器件可动结构完成以后 ,加上一层封盖保护 ,可以显著提高器件的成品率和可靠性。本文提出了一种用于MEMS芯片封盖保护的金 硅键合新结构 ,实验证明此方法简单实用 ,效果良好。该技术与器件制造工艺兼容 ,键合温度低 ,有足够的键合强度 ,不损坏器件结构 ,实现了MEMS器件的芯片级封装。我们已经将此技术成功地应用于射流陀螺的制造工艺中