An introduction to fast wafer level reliability monitoring for integrated circuit mass production

The continuous verification of process reliability is essential to semiconductor manufacturing. The tool that accomplishes this task in the required short time is the fast wafer level reliability monitoring (fWLR). The basic approaches for this task are described in this introductory overview. It summarizes sampling plans, discusses the feasibility of using fWLR for screening and describes the data assessment and application of control cards. Beyond these general topics many of the fWLR stress methods are described in detail: Dielectric stressing by means of an exponential current ramp is compared to ramped voltage stress. Especially for thin oxides the methods differ regarding the soft breakdown detection and the time they consume. Another task of fWLR is the detection of plasma induced damage, which can be achieved by applying a revealing stress to MOSFETs with antenna. The design challenges of the structures and the test method as well as the data assessment are described in detail. An important section deals with fWLR for interconnects. In this section the appropriate test structures (including thermal simulations) are illustrated and fast electromigration stresses are discussed and the details of standard wafer level electromigration accelerated test (SWEAT) are included. For contacts and vias a simple method to check reliability is presented. Finally the monitoring of device reliability is treated. It is shown that using indirect parameters that correlate well to standard parameters such as the drain current can be beneficial for fWLR. For both, the interconnects and the devices, it is essential to have locally heated test structures in order to keep the stress time low. The detection and verification of mobile ions can also be performed with such a self-heated structure. For the described methods examples are given to illustrate the usefulness.     

Study of unipolar pulsed ramp and combined ramped/constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9–28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way.     

Quality assessment of thin oxides using constant and ramped stress measurements

Two methods are proposed for obtaining extrinsic oxide lifetime data using fast ramped tests. It is shown that the intersection point between the extrinsic and intrinsic branches of a Weibull plot coincides for ramped and constant stress tests. This is the basis of our fast qualification approach, where intrinsic data are obtained by constant voltage stress and extrinsic data are cumulated with a fast ramped test. The correctness of our approaches is supported by constant voltage and exponentially ramped current measurements.     

Fast wafer level reliability monitoring as a tool to achieve automotive quality for a wafer process

This work describes and discusses fast wafer level reliability (fWLR) Monitoring as a supporting procedure on productive wafers to achieve stringent quality requirements of automotive, medical and/or aviation applications. Examples are given for the various reliability topics: dielectrics, devices, metallisation, plasma charging with respect to required test structures, stress methods and data analysis. Application areas of fWLR are highlighted and limitations considered. Further aspects such as relevant reliability parameters, sampling strategies and out of control action plans are discussed.     

Plasma process induced damage detection by fast wafer level reliability monitoring for automotive applications

Plasma process induced damage (PID) poses a device lifetime risk to all semiconductor products containing MOS gate dielectrics. This risk increases for smaller technology nodes. In this work we will present how to protect automotive products from PID. Products need to be made robust against PID by design checks with antenna rules determined in technology reliability qualifications. Additionally, damage that is invisible at zero hour, i.e. in parameter or product tests, needs to be detected by fast wafer level reliability (fWLR) monitoring on the fully produced wafer. The application and details of different stress types for charging cases are presented and discussed.     

Quantifying charging damage in gate oxides of antenna structures for WLR monitoring

A new method to quantify the reliability risk for gate oxide with plasma induced charging damage (PID) is established. Based on existing antenna test methodology the quantity of inflicted damage is expressed in a physical meaningful number by means of a simple model applicable for thick oxides (>5 nm).This model takes trap activation, trap filling, detrapping and also traps generation under constant current test condition (“revealing stress”, “diagnostic stress”) into account. For the corresponding development of the measurable external supply voltage with time an equation is derived. Experimental test data from different oxide thicknesses are fitted to this model equation to obtain its main parameters, the cross section values. These cross section values describe the probabilities for the different trap/detrap processes during stress. Cross section values thus found extend published data for lower electric fields to high electric fields necessary for a fast test.The number of plasma induced traps, which was added to the oxide during wafer processing, can now be determined by applying an electron trapping rate (ETR) test method, and combining it with our dynamic trap generation/filling model. The obtained number of PID related traps opens a path to calculate the corresponding reduction of oxide lifetime. Real measurement data are used to illustrate the method and its applicability to fast wafer level reliability (fWLR) monitoring.     

Implications of a localised defect model for wafer level reliability measurements of thin dielectrics

In this paper a simple model of an oxide defect as a region of localised oxide thinning is used to explore the relationship between the most commonly used measurements of dielectric reliability. For each measurement it shows how the measured parameters depend on the area and effective thickness of the defect. The work shows that in constant voltage and ramped voltage stress the area and thickness of the defect may be easily separated in the measured parameters. However, in constant current and ramped current measurements all measured parameters are dependent on both area and thickness which makes the extraction of area and thickness more difficult. It is shown that, in order to be able to project from one measurement to any other, the defect area and thickness must be determined. In particular, if projections of charge to breakdown are required then the use of a model which only includes defect thinning as proposed by Lee et al, [1], is not sufficient.     

Dielectric breakdown distributions for void containing silicon substrates

Distributions of gate oxide failure in various types of silicon substrate materials have been investigated for a wide range of oxide thicknesses. Silicon substrates containing various well-characterized void distributions along with defect-free materials were tested using special low-series resistance capacitor structures. Results of both ramped field tests of variable ramp rate and constant field tests were performed and analyzed within the framework of Weibull statistics. Ramped field tests are not “time zero dielectric breakdown” tests as is commonly asserted. They can in fact be very useful in extrapolating time dependent failure. The same set of Weibull parameters can be used to describe both ramped field and constant field wearout tests if an appropriate model for the time dependent damage accumulation during the field ramp is used. There are implications for reliability predication and the burn-in screening of device populations containing such defects.     

Evaluation of performance–reliability trade-offs in a Si–Ge BiCMOS process using fast wafer level techniques

Fast wafer-level reliability (fWLR) techniques are successfully implemented in order to investigate several gate oxide reliability–performance tradeoffs that affect the architecture of a high speed BiCMOS process. Fast feedback of device and reliability parameters is required during process development in order to avoid failures during process qualification. This study highlights some performance–reliability tradeoffs that had to be overcome during the development of a modern BiCMOS process.     

Gate oxide integrity dependence on substrate characteristics and SiO2 thickness

Gate oxide integrity (GOI) has been investigated for a wide range of oxide thicknesses, from 5 to 50 nm. Silicon substrates containing voids of number densities along with defect-free (perfect) polished and epitaxial wafers were tested. Oxide reliability was monitored by linear ramped field tests at variable ramp rate and by constant current and field tests using a doped polysilicon gate as the cathode. The field and time parameters characterizing the distributions of each breakdown mode have been extracted by Weibull analysis. In general, more than one mode of breakdown is found in a given sampled substrate type. The average field of the breakdown shifts to higher fields with decreasing oxide thickness. In the void-related mode, a constant countable number of defects for a given substrate type are “activated” at sufficiently high fields independent of oxide thickness. Void-free epi and “perfect” substrates show a single, non-intrinsic breakdown mode. This mode is also found in the void containing materials in the part of their distribution, unaffected by voids.     

Variation-resilient quantifiable plasma process induced damage monitoring

Many wafer manufacturing processes use plasma or other charge-based effects. The resulting currents can damage or destroy MOS gate oxides of transistors in products. This plasma induced damage (PID) can be in form of a reduction of the required lifetime of the devices, which can result in systematic early product failures in the field. PID damage and the resulting reliability reduction can be invisible in zero hour parameter and product tests, which can make it particularly dangerous.Products have to be made robust against PID by antenna design rules determined during technology development and verified in qualification measurements. To prevent early product fails due to unnoticed process excursions, fast wafer level reliability (fWLR) monitoring on the fully processed product wafer is required. The performance of PID fWLR on suitable test structures and the application of the fast diagnostic stresses will be presented. Details on options for data analysis for fast, sensitive and precise process excursion detection will be discussed based on a set of productive fWLR data following this methodology where false alarms are prevented.For some excursions detected by the fast diagnostic stresses the effect on the device lifetimes will be analysed with long term MOS device stresses. The physical reason for this will be discussed in a simple model of the devices' band structures.     

Tunnel barrier properties of stressed ferromagnetic tunneljunctions

The oxide breakdown properties of ultra-thin (-1 nm) naturally oxidised Al₂O₃ tunnel barriers in magnetic tunnel junctions were studied using ramped and constant stress experiments. During stress measurements at 1.35 V, a fast breakdown of the junction was observed. The time-to-breakdown is evaluated using Weibull statistics, as commonly utilised in SiO₂ reliability studies     

Influence of charge trapping on oxide scaling down

The aim of this work is the characterization, in terms of trapped charge and charge to breakdown, of the quality of an oxide with reduced thickness. A comparison between two evaluation methods, the widely used exponentially ramped current stress (ERCS) and the constant current stress (CCS), is established obtaining contradictory results. A measurement of the charge trapped in the oxide bulk is performed by sensing the modification of the Fowler–Nordheim barrier under constant current stress. Using this technique it is possible to correlate the charge trapping characteristics with the charge to breakdown and to explain the inconsistencies.     

Oxide reliability: influence of interface roughness, structure layout, and depletion layer formation

The charge to breakdown Q_bd and the breakdown voltage V_bd distributions obtained on 7.5 and 12 nm thick gate oxides (GOX) using two different wafer level reliability current ramp algorithms are discussed in terms of the GOX interface roughness and the depletion effects during the stress. The observed influence of the interface roughness on the GOX properties seems to be very sensitive to the gate polarity during the stress or the injection direction of electrons. Especially the roughness of the interface through which electrons are injected into the gate oxide influences the oxide reliability. The effect of the interface roughness turned out to depend strongly on the test acceleration level. A possibility of masking of the roughness (reduction of the “effective roughness”) of the GOX/Si interface as a result of strong depletion at higher accelerations is discussed.     

Limitations and noise in interferometric systems using frequency ramped single-mode diode lasers

Frequency ramped diode laser sensing and measurement systems suffer from a variety of limitations and noise sources. Nonlinearities in the frequency ramp produce unwanted sidebands in the frequency spectra of the system output and make accurate distance determination difficult in the frequency domain. Thermally induced drifts in the laser frequency prohibit long-term sensitive phase measurements even with a reference interferometer. It is shown that phase noise due to the fundamental linewidth of the diode laser and not bias current noise determines the noise floor of most FMCW systems in the regimes away from (1/f) noise. Time domain techniques suffer from low resolution because only a few data points can be taken during each frequency ramp and thus achieve poor averaging of the phase noise. The signal to noise ratio (SNR) of frequency ramped systems is shown to be lower (10-30 dB) than the theoretical prediction for an unmodulated heterodyne system, which was substantiated by showing that the minimum detectable phase is somewhat higher than that predicted by the idealized model.     

MasterDrive变频器使用外加斜坡给定的研究与应用

西门子MasterDrive变频器内部带有一个复杂功能的斜坡发生器,用于将阶跃给定增加斜坡后发给速度调节器。在某些场合比如设备需要复杂起动特性的时候,变频器需要接收外加的带斜坡的速度给定,这就需要对其进行特殊的设置。本文对外加含斜坡速度给定信号进行了分析,并提出了处理方法,最后举例说明了该方法的实际应用情况。     

A new algorithm for transforming exponential current ramp breakdown distributions into constant current TDDB space, and the implications for gate oxide QBD measurement methods

Charge-to-breakdown (Q_BD) is one of the manufacturing parameters that is used as a measure of oxide quality. In this work the influence of the measurement conditions on Q_BD is examined, as well as the relationship between Q_BD and oxide thickness. Using oxides ranging from 45 to 80 Å, two Q_BD measurement methods are employed: constant current stress (CCS) and an exponential current ramp (ECR). A variety of current densities (for the constant current stress) and step durations (for the exponential current ramp) are studied. It is shown that not only does Q_BD depend on oxide thickness, but that Q_BD depends strongly on the measurement conditions, and that, depending on the test conditions, Q_BD can increase or decrease as the oxide thickness decreases. It is also shown that there is a strong agreement between the Q_BD measured with a constant current stress and the Q_BD measured with an exponential current ramp. Finally, an algorithm is proposed for transforming the Q_BD distribution obtained from a series of exponential current ramps into the Q_BD and/or t_BD domains of constant current stressing.     

A new and flexible scheme for hot-electron programming ofnonvolatile memory cells

A new hot electron writing scheme for flash EEPROMs is proposed that combines a positive source to bulk voltage and a ramped voltage on the control gate. The scheme exploits the equilibrium between hot electron injection and displacement current at the floating gate electrode in order to achieve a transient regime where the drain current of the cell is virtually constant. The new method allows one to accurately control the threshold voltage and the programming drain current that is essentially determined by the slope of the control gate ramp and can thus be traded off with programming time over a wide range of values. The main features of the new scheme are experimentally demonstrated on up-to-date 0.6 μm stacked gate flash EEPROM devices     

Statistical nature of hard breakdown recovery in high-κ dielectric stacks studied using ramped voltage stress

In replacing the conventional SiO₂ gate dielectric with high-κ materials, new challenges emerge on understanding the kinetics of dielectric breakdown due to the different properties of the new bulk oxide and the interfacial layers at the substrate and gate electrode interface as well. Among several complexities, dielectric relaxation and recovery have received a lot of attention due to their promising applications in resistive random access memory (RRAM). In this study, we explore the stochastic nature of hard breakdown recovery in HfO₂, taking advantage of ramped voltage stress (RVS) measurements, which are theoretically equivalent to the widely used constant voltage stress (CVS), while being significantly less time-consuming. We found that the possibility of recovery is largely dependent on the ramp rate during RVS as the dielectric needs adequate time and sufficient thermal budget to recover. The clustering model is found to be a good fit to the RVS data sets for post-recovery subsequent breakdown events and the extent of defect clustering is found to be more intense after increasing number of recovery events. The breakdown mechanism in the stack is confirmed by measuring the resistance change trends with temperature.     

Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics

Hard breakdown (HBD) is shown to be a gradual process with the gate current increasing at a predictable rate exponentially dependent on the instantaneous stress voltage and oxide thickness. This is contrary to conventional wisdom that maintains that HBD is a fast thermally driven process. The HBD degradation rate (DR) for a 15 /spl Aring/ oxide scales from >1 mA/s at 4 V to <1 nA/s at 2 V, extrapolating to <10 fA/s at use voltage. Adding the HBD evolution time to the standard time-to-breakdown potentially reduces the projected fail rate of gate dielectrics by orders of magnitude.