A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented     

A 27-MHz digital-to-analog video processor

The authors describe a circuit intended for the restitution of a digital video signal into its analog red, green, and blue components. Sampling parameters according to CCIR recommendation 601 have been adopted for the digital interface. The circuit consists mainly of a complex digital processing part and three digital-to-analog converters. All of these functions have been implemented in a 38-mm² CMOS chip. The design goal was achieved by the development of an efficient 2-μm CMOS technology dedicated to analog and digital applications     

A PAL/NTSC digital video encoder on 0.6-μm CMOS with 66 dBtypical SNR, 0.4% differential gain, and 0.2° differentialphase

A digital video encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2°, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4×4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7×7 mm). The digital logic has 47 k gates and achieves an average power dissipation of 0.37 μW/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, Θ J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70°C     

A 1.2.1 post-filter for color-difference interpolation of a MACvideo signal

The design and implementation of a digital video application-specific integrated circuit (ASIC) that performs the line interpolation of the missing color samples of a digitized multiplex analog component (MAC) video signal are described. The main part of this circuit is a specific 864×8-bit memory designed as a double-chroma digital delay line. The design is based on 2-μm double-metal N -well CMOS technology. The chip area is 35.6 mm² and it operates with a clock rate of 13.5 MHz. This circuit, which also performs phasing and blanking of the 8-bit digitized luminance and chrominance samples, is a part of a digital decoder used for the reception of video TV signals coded according to the MAC family system     

A 30-MHz mixed analog/digital signal processor

A multiplying encoder architecture that is implemented in the design of a mixed analog and digital signal processor is presented. The processor is suitable for performing both high-speed A/D conversion and digital filtering in a single chip. The device can resolve the input with 8 b at 30 Msample/s and perform 28 multiply and 28 add operations per sample under typical conditions. The processor is designed for a 28-tap programmable FIR (finite impulse response) filter with analog input signal which can be used for waveform shaping of the modem to obtain the desired transmission performance for business satellite communication and mobile communication. The chip is fabricated in a 1-μm double-polysilicon and double-metal CMOS technology. The chip size is 9.73×8.14 mm², and the chip operates with a single +5.0-V power supply. Typical power dissipation is 950 mW; 330 mW is dissipated in analog and 620 mW is in the digital block     

一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路

提出了一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路.通过引入一个使用亚阈值技术的基准源,电路实现了温度补偿,从而使得系统时钟在～40～100℃的范围内保持稳定.在模块设计中,提出了一些新的电路结构来降低系统功耗,其中包括一种零静态功耗的上电复位电路和一种新的稳压电路.该射频/模拟前端电路采用不带肖特基二极管0.18μm CMOS EEP-ROM工艺流片实现,它与数字基带、EEPROM一起实现了一个完整的标签芯片.测试结果表明,该芯片的最低电源电压要求为0.75V.在该最低电压下,射频/模拟前端电路的总电流为4.6μA.     

基于DM6446的视频编码器的硬件设计

设计了一套基于TMS320DM6446的视频压缩系统.主芯片采用TI公司的TMS320DM6446,模拟视频信号送入解码器TVP5150后,解码为符合ITU-R BT.656标准的数字视频信号,BT.656数字视频信号被送往TMS320DM6446,TMS320DM6446内嵌DSP实现视频信号的H.264压缩.内嵌A...     

CCD成像系统的模拟自校图形设计

目前航天遥感领域CCD自校图形都是数字式的,仅能在数字链路上检测FPGA逻辑模块和图像数据传输模块,而视频AD模块一直未能实现在轨检测。提出了一种驱动芯片+数模转换芯片的架构,搭建了易行可靠的电路,仿照CCD视频信号格式,并与CCD信号通过电容直接耦合到视频AD输入端。选用FPGA模块来产生与CCD像素时钟同频的逻辑信号,然后输出给驱动芯片EL7156。驱动芯片的低压输出取决于FPGA控制的数模转换芯片的模拟输出,高压输出不变,从而实现灰度变化。当CCD正常工作时,FPGA模块控制模拟自校图形输出为高阻状态,对CCD工作影响微乎其微。试验结果表明:模拟自校图形能与CCD视频信号互不干扰,并可与之分时送入视频AD模块,达到检测整个CCD成像系统工作状态的目的。该电路可检测多个视频AD模块,简单易行且占用很小的PCB空间,所选芯片具有航天应用可靠性。     

A total solution for a 9600-b/s modem transmitter chip

A single-chip analog transmitter (TX chip) for a V29-V32 9600-b/s modem has been implemented in a 3-μm CMOS n-well process. A high level of integration permits a low-cost, high-performance modem to be built. The TX chip is composed of analog, switched capacitor, and digital circuits. The important functions realized are the phase-point generator, the cosine roll-off low-pass filter, the modulator, and the programmable equalization filters. The chip occupies 29 mm² and dissipates 300 mW     

基亏DSP的多路音／视频采集处理系统设计

采用TI公司的TMS320DM642型数字媒体数字信号处理器（DSP）设计多路音／视频采集处理系统，实现实时处理4路模拟视频和音频输入、1路模拟／数字视频和1路模拟音频信号输出的功能，该系统可适应PAL／NTSC标准复合视频CVBS或分量视频Y／C格式的模拟信号和标准麦克风或立体声音频模拟输入，具有PAL／NTSC标准S端子或数字RGB模拟／数字信号输出和标准立体声音频模拟输出。并给出软／硬件设计原理和电路。     

A 14-bit 10-μs subranging A/D converter with S/H

A microprocessor-compatible, 14-bit, 10-μs subranging analog-to-digital converter with a sample/hold amplifier (SHA) is described. The chip architecture is based on a five-cycle subranging flash technique using both analog and digital error correction. The conversion speed is enhanced by an analog correction method, whereby redundant bit currents allow digital/analog converter updates without changing bits determined in previous cycles. The residue signal path uses simple circuitry and is highly differential. Prototype performance has been demonstrated     

A self-calibrating single-chip CMOS camera with logarithmicresponse

A high-dynamic-range CMOS image sensor consisting of nonintegrating, continuously working photoreceptors with logarithmic response is presented. The nonuniformity problem caused by the device-to-device variations is greatly reduced by an implemented analog self-calibration. After performing this calibration, the remaining fixed pattern noise amounts to 3.8% (RMS) of an intensity decade at a uniform illumination of 1 W/m². The sensor provides a resolution of 384×288 pixels and a dynamic range of 6 decades in the intensity region from 3 mW/m² to 3 kW/m². It contains all components required for operating as a camera-on-a-chip. The image data can be read out either via a single analog line (video standard) or via a digital interface after undergoing an analog-to-digital conversion on the chip. Additional features like automatic exposure control, averaging of adjacent pixels, and digital zoom have been implemented, making the sensor suitable for a wide field of applications     

A power and area efficient CMOS clock/data recovery circuit forhigh-speed serial interfaces

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm² for the digital PLL and 0.44 mm² for the analog PLL. It can handle an input data rate up to 280 Mb/s     

基于PCI的视频信号发生器的实现方法

提出了一种基于PCI总线的视频图像数据发送系统的设计和实现方法.主要介绍系统的硬件实现方法和软件的实现流程.该系统利用PLX9054作为PCI的接口芯片,用FPGA实现9054PCI 接口芯片与发送系统总线之间的控制,D/A转换芯片完成同步信号和视频图像数据的组合,并转换成模拟视频信号,作为发送系统的输出.该系统为图像跟踪与识别系统提供一个定量的性能测试设备.     

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.     

A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

A 10-bit 20-MHz A/D converter for high-quality video systems such as high-definition television, video tape recorders for business use, and digital video cameras is described. This LSI circuit uses a standard two-step parallel architecture, includes automatic gain adjustment and digital two-bit error correction, and has a sample-and-hold circuit on the chip. It is fabricated by a 4.5-GHz f_T. 3-μm-rule standard bipolar technology. Its die size is 25 mm² , and its power consumption is 900 mW, which is about half of the lowest values reported to date. The converter can digitize video signals of up to 8.5 MHz at a conversion frequency of 20 MHz. The error in differential gain is 0.5 percent, and the error in differential phase is 0.5°     

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Static testing of analog‐to‐digital (A/D) and digital‐to‐analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built‐in self‐test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.     

A video codec LSI for high-definition TV systems withone-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16×12.10-mm² chip. A standard cell layout method and a 1.2-μm CMOS logic LSI process were used     

A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSPusing partial response signaling with maximum likelihood detection

A mixed-signal, 7.0 Mbyte/s PRML (partial-response maximum likelihood) read/write channel is discussed in this paper. PR-IV (minimum signal bandwidth) for signal encoding is used, along with ML (maximum likelihood) detection to achieve superior error rate performance. Signal equalization is provided using a programmable ten-tap FIR (finite impulse response) digital filter. This read/write channel is implemented on a single chip using analog circuits and 20 K CMOS logic gates. The 7.5 mm square chip uses a 5 V, 1 μm, BiCMOS process with a 6 GHz n-p-n and a 1 GHz p-n-p and is packaged in a 100-lead metal QFPK (quad flat pack)     

A monolithic 14 bit/20 /spl mu/s dual channel A/D converter

A 14-bit monolithic coarse-fine integration A/D converter with 20-/spl mu/s conversion time is described. The IC has internal sample-and-integrate circuits and dual-channel A/D conversion capability. Overall performance, including sample-and-integrate circuits, is 0.01% distortion and 84-dB S/N ratio. All of the analog/digital circuits for dual-channel A/D conversion are integrated on a single chip by using an advanced nitride self-aligned (advanced-NSA) process.