A 5-ns GaAs 16-kb SRAM

A GaAs 4 K×4-b static-Ram (SRAM) with high speed and high reliability has been developed for practical systems. By adopting a novel basic circuit technique to the peripheral circuits, the RAM operates over a wide temperature range. By using a novel memory cell, the soft-error rate is reduced to less than that of commercial silicon emitter-coupled-logic (ECL) RAMs. Furthermore, by adopting a triple-level interconnection process, the chip area is reduced to 58% of that using a double-level one. The RAM operates at a single supply voltage of 1.8 V. At an ambient temperature of between 25 and 100°C, the RAM is guaranteed a 5.0-ns access time, 2.0-W power dissipation, and ±0.1-V supply voltage tolerance     

A 200-mW GaAs 1 K SRAM with 2-ns cycle time

A very high-speed and low-power 1024/spl times/1 SRAM has been designed and fabricated using a normally-off recessed-gate FET technology. Minimum gate length is 0.7 /spl mu/m. A minimum access time of 1.4 ns has been obtained with a power dissipation of 210 mW. The memory cell area is 1197 /spl mu/m/SUP 2/ and the chip size is 1.91/spl times/2.21 mm/SUP 2/. The output voltage swing across a 50-/spl Omega/ load is 700 mV. The maximum simulated yield for 1 K SRAMs is discussed theoretically. A mean standard deviation in threshold voltage less than 15 mV is required to obtain 100% design yield. The SRAM has been shown to be fully operational using the march and checkerboard tests and exhibits read and write cycle times of 2 ns.     

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

A 7-ns 140-mW 1-Mb CMOS SRAM was developed to provide fast access and low power dissipation by using high-speed circuits for a 3-V power supply: a current-sense amplifier and pre-output buffer. The current-sense amplifier shows three times the gain of a conventional voltage-sense amplifier and saves 60% of power dissipation while maintaining a very short sensing delay. The pre-output buffer reduces output delays by 0.5 ns to 0.75 ns. The 6.6-μm² high-density memory cell uses a parallel transistor layout and phase-shifting photolithography. The critical charge that brings about soft error in a memory cell can be drastically increased by adjusting the resistances of poly-PMOS gate electrodes. This can be done without increasing process complexity or memory cell area. The 1-Mb SRAM was fabricated using 0.3-μm CMOS quadrupole-poly and double-metal technology. The chip measures 3.96 mm×7.4 mm (29 mm²)     

A 1.2-ns HEMT 64-kb SRAM

A 1.2-ns emitter-coupled-logic (ECL)-compatible 64-kb static RAM using 0.60-μm gate high-electron-mobility-transistor (HEMT) technology was developed. To achieve fast access time, the memory cell array was divided into sixteen 4-kb memory planes and a data-line equalization technique was adopted. The chip power consumption was suppressed to 5.9 W by using three power supply voltages (-1.0, -2.0, and -3.6 V) and a normally off (E/D) source-follower buffer for the word driver circuit. A new device fabrication technique, the HEMT double-etch-stop process, enabled the RAM to be fabricated in simple and fewer processing steps and reduced the chip dimensions to 7.4×6.5 mm     

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fullypipelined architecture

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined     

A 2.5-ns, 40-mW, 4/spl times/4 GaAs multiplier in two's complement mode

The design, fabrication, and testing of a very fast GaAs 4/spl times/4 parallel multiplier based on the modified Booth's algorithm are described. The multiplier includes novel transfer logic cells and is the first high-performance GaAs two's-complement multiplier. The circuit, fabricated with 1-/spl mu/m aligned process, exhibits a multiplication time of 2.5 ns (typical 2.7 ns) on the critical path, with a 40-mW power consumption. Per gate the average delay is 120 ps, at 0.2-mW dissipation.     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

A 15-ns 4-Mb CMOS SRAM

A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (×4 or ×1) bit organization has been developed based on a 0.55-μm triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (TDW) are three key circuits which have been utilized in addition to the 0.55-μm CMOS technology to achieve the remarkable access time of 15 ns. Bit organization of either ×4 or ×1 can be selected purely electrically, and does not require any pin connection procedure     

优化阵列结构的5 ns 32 kb CMOS SRAM及其外围电路

设计了一个地址有效时间为５ｎｓ的３２ｋｂ（２ｋ×１６位）ＣＭＯＳ静态随机存储器。设计中采用优化的阵列结构、分段字线译码,以达到１．７５ｍＷ／ＭＨｚ的低功耗;采用位线平衡技术、高速两级敏感放大器及可预置电压的数据输出缓冲,以提高存储器的读写频率。同时,利用两级敏感放大器的层次式结构降低数据线的电压幅度,进一步降低了功耗。     

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm ² memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers     

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current senseamplifiers

A 4-Mb CMOS SRAM with 3.84 μm² TFT load cells is fabricated using 0.25-μm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells     

A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads

A 25-ns 4-Mbit CMOS SRAM with 512 K word*8-bit organization has been developed. The RAM was fabricated using a 0.5- mu m double-poly and double-aluminum CMOS technology and was assembled in a 32-pin 400-mil DIP. A small cell size of 3.6*5.875 mu m/sup 2/ and a chip size of 7.46*17.41 mm/sup 2/ were obtained. A fast address access time of 25 ns with a single 3.3-V supply voltage has been achieved using the newly developed dynamic bit-line load (DBL) circuit scheme incorporated with an address transition detector (ATD), divided word-line structure (DWL), three-stage sense amplifier, and low-noise output circuit approach. A low operating current of 46 mA at 40 MHz and low standby currents of 70 mu A (TTL) and 5 mu A (CMOS) were also attained.<>     

A 4-ns 4K×1-bit two-port BiCMOS SRAM

The authors introduce a two-port BiCMOS static random-access memory (SRAM) cell that combines ECL-level word-line voltage swings and emitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAMs while preserving the high density and low power of CMOS memory arrays. The memory can be read and written simultaneously and is therefore well-suited to applications such as high-speed caches and video memories. A read access time of 3.8 ns at a power dissipation of 520 mW has been achieved in an experimental 4K×1-bit two-port memory integrated in a 1.5-μm 5-GHz BiCMOS technology. The access time in this prototype design is nearly temperature-insensitive, increasing to only 4 ns at a case temperature of 100°C     

A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture

A 20 ns 4-Mb CMOS SRAM operating at a single supply voltage of 3.3 V is described. The fast access time has been achieved by a newly proposed word-decoding architecture and a high-speed sense amplifier combined with the address transition detection (ATD) technique. The RAM has the fast address mode, which achieves quicker than 10-ns access, and the 16-b parallel test mode for the reduction of test time. A 0.6-μm process technology featuring quadruple-polysilicon and double-metal wiring is adopted to integrate more than 16 million transistors in a 8.35-mm×18.0-mm die     

A 21-mW 4-Mb CMOS SRAM for battery operation

The authors describe a 21-mW 4-mB CMOS SRAM for the application of memory systems which operate on 3-V batteries. A low active power is achieved by novel circuit technologies. A thin-film transistor (TFT) load memory cell effectively reduces standby current to 0.4 μA. A new multibit test circuit, which permits measurement of access time, is also introduced for a reduction of the test time. The authors describe the characteristics of the TFT memory cell and the improved memory cell design for stable cell operation. The 0.6-μm process technology used to fabricate the 4-Mb SRAM and the chip performance are outlined     

A 23-ns 4-Mb CMOS SRAM with 0.2-μA standby current

A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5-μm CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 μm² and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm²     

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits

The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-μm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme

The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line scheme to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-kb 4-T SRAM is measured to consume 0.32 mW in the standby mode, and a 3.8-ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz     

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM

A 0.3-μm 4-Mb BiCMOS SRAM with a 6-ns access time at a minimum supply voltage of 1.5 V has been developed. Circuit technologies contributing to the low-voltage, high-speed operations include: (1) boost-BiNMOS gates for address decoding circuits; (2) an optimized word-boost technique for a highly-resistive-load memory cell; (3) a stepped-down CML cascoded bipolar sense amplifier; (4) optimum boost-voltage detection circuits with dummies for boost-voltage generators