基于嵌套循环指令分析的片上存储器分配策略

本文提出了一种无Cache情况下基于嵌套循环指令分析的片上存储器(On-chip memory)分配策略.该策略分析程序中循环指令,控制划分粒度将所有函数切割成块,然后使用背包算法和优先级算法组合的分配算法,选择合适块放入片上存储器,达到优化程序性能的目的.实验结果表明,该策略能够显著提高程序性能,平均提高一倍,甚至更高,同时它能够预知优化后程序执行时间的变化,最高误差为2%.     

基于扩展控制流图的片上存储器分配策略

本文提出一种基于扩展控制流图(ECFG)的片上存储器(Scratch-Pad Memory,SPM)分配策略,该策略首先把程序划分为全局变量、全局堆栈、指令块等节点,用包含节点和节点间关系的ECFG来描述应用程序,接着采用考虑了节点间关系的改进的背包算法把选中的节点分配到SPM中.实验表明该策略比采用单纯背包算法的SPM分配策略减少应用程序执行时间11%,比不使用SPM时减少56%,大大提高了SoC存储子系统的性能.     

低码率语音编码器实现中的片上Cache分配策略

针对DSP上低码率语音编码器的实现和优化问题,研究了片上Cache的分配策略.根据指令Cache的大小,以及程序处理的数据量的大小,将程序分成大小合理的段,分阶段载入Cache中.对数据Cache的分配考虑了Cache结构和数据本身的特点,使有限的数据Cache得到充分的利用.全面考察数据的生命期,使已经载入数据Cac...     

基于性能分析的片上影子堆栈存储器设计

针对堆栈访问局部性特征,通过建立片上影子堆栈存储器(Shadow Stack Scratch-Pad Memory,简称S~3PM),将堆栈访问热点映射至SPM,从而减少堆栈访问时内核对外存的访问次数,提高系统性能.在研究S~3PM的基础上,还对包含指令、数据和堆栈优化的SoC存储子系统进行总体设计空间探索,从而合理分配SPM资源.实验结果表明,7个基准测试程序仅使用128字节的S~3PM映射堆栈,可以取得最高30.8%,平均12.4%的性能提升.     

基于片上存储器的SDRAM换行访问低功耗设计策略

在以SDRAM为主的存储系统中,SDRAM的换行访问产生了大量的功耗开销,减少换行次数可以降低存储系统功耗。本文提出了引入片上存储器来降低SDRAM换行次数的低功耗设计策略。该策略首先对指令执行流进行分析,并统计出在对堆栈和全局变量的访问时产生了频繁换行;然后将堆栈放入片上堆栈存储器;同时借助有芯片面积约束的贪婪算法确定了片上数据存储器的大小和所存放的全局变量。实验结果表明,引入较小的片上存储器就使得换行次数大大降低,功耗显著下降,减少换行访问的功耗平均下降了24%。     

嵌入式非易失性存储器在SoC物理设计中的应用

嵌入式非易失性存储器以其同时具备数据可更改性及掉电保存性而已被越来越广泛的应用于SoC物理设计。文中结合一款电力网控制芯片R36的实际设计案例,分析了该器件的应用特点,并从用途、性能、容量选择等方面说明了通过非易失性存储器对降低芯片成本、提高速度及可靠性应用方法。     

嵌入式存储器面面观

随着超大规模集成电路工艺的发展,人类已经进入了超深亚微米时代。先进的工艺使得人们能够把包括处理器、存储器、模拟电路、接口逻辑甚至射频电路集成到一个大规模的芯片上,形成所谓的SoC（片上系统）。作为SoC重要组成部分的嵌入式存储器,在SoC中所占的比重（面积）将逐渐增大。到2010年,约90％的硅片面积都将被具有不同功能的存储器所占据,如图1所示。     

SoC嵌入式flash存储器的内建自测试设计

深亚微米技术背景下，嵌入式存储器在片上系统芯片(system-on-a-chip，SoC)中占有越来越多的芯片面积．嵌入式存储器的测试正面临诸多新的挑战。本文论述了两种适合SoC芯片中嵌入式flash存储器的内建自测试设计方案。详细讨论了专用硬件方式内建自测试的设计及其实现，并且提出了一种新型的软硬协同方式的内建自测试设计。这种新型的测试方案目标在于结合专用硬件方式内建自测试方案并有效利用SoC芯片上现有的资源，以保证满足测试过程中的功耗限制，同时在测试时间和芯片面积占用及性能之间寻求平衡。最后对两种方案的优缺点进行了分析对比。     

片上网络的动态虚通道分配策略

针对片上网络（NoC）的传统的静态虚通道分配不能很好适应非平衡的业务负荷问题,本论文提出了NoC动态虚通道分配策略。在静态虚通道分配基础上,动态分配虚通道通过实时监测节点端口的包流量的方向,决定分配给该端口的虚通道数目。动态虚通道资源可以在所有端口间共享,并根据通信业务需求动态调度。在二维meshNoC上的仿真表明,动态虚通道分配策略不仅节约了存储器资源,而且对NoC传输延时有一定的改善。     

Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications

In multimedia applications, run-time memory management support has to allow real-time memory de/allocation, retrieving and processing of data. Thus, its implementation must be designed to combine high speed, low power, large data storage capacity and a high memory bandwidth. In this paper, we assess the performance of our new system-level exploration methodology to optimise the memory management of typical multimedia applications in an extensively used 3D reconstruction image system [1, 2]. This methodology is based on an analysis of the number of memory accesses, normalised memory footprint¹ and energy estimations for the system studied. This results in an improvement of normalised memory footprint up to 44.2% and the estimated energy dissipation up to 22.6% over conventional static memory implementations in an optimised version of the driver application. Finally, our final version is able to scale perfectly the memory consumed in the system for a wide range of input parameters whereas the statically optimised version is unable to do this.The original version of this paper first appeared in the Proceedings of Signal Processing Systems 2003.Marc Leeman has as professional research interests hardware/software co-design, code optimisation in general and optimisation of dynamic data types and dynamic memory management for low power embedded systems in particular. Personal interests include Open and Free software development, software configuration and GNU/Debian package maintenance. He received an engineering degree, a master in artificial intelligence and a Ph.D. in electrical engineering in 1997, 1998 and 2004 respectively, all at the K.U. Leuven. He is a member of the IEEE Computer Society. Currently, he works as an R&D Engineer for Barco Control-rooms Division (BCD) on hardware/software co-design for streaming video products.David Atienza received the M.Sc. degree in Computer Sciences from the Complutense University of Madrid (UCM), Spain in 2001. Since then he has joined the Department of Computer Architecture and Automation of Complutense University of Madrid as a sandwich Ph.D. student half-time at the Inter-university Micro-Electronics Centre (IMEC), Heverlee, Belgium. His research interests include optimisation of dynamic memory management on multimedia and wireless network applications for low power and high performance embedded systems, computer architecture and high-level design automation.Geert Deconinck is Associate Professor (hoofddocent) at the K.U. Leuven (Belgium) since 2003 and staff member of the research group ELECTA (Electrical Energy and Computing Architectures). His research interests include the design and assessment of software-based solutions to meet dependability, real-time, and cost constraints for embedded systems. In this field, he has authored and co-authored more than 120 publications in international journals and conference proceedings. He received his M.Sc. in Electrical Engineering and his Ph.D. in Applied Sciences from the K.U. Leuven, Belgium in 1991 and 1996 respectively. He was a visiting professor (bijzonder gastdocent) at the K.U. Leuven in 1999–2003. - Flanders (Belgium) in the period 1997–2003.Vincenzo De Florio received his MSc degree in computer science in 1987 and his PhD degree in engineering in 2000, respectively from the University of Bari, Italy, and the University of Leuven, Belgium. He is currently post-doctoral researcher at the University of Antwerp, where he is doing research on adaptive and dependable mobile applications. Previously he had been researcher and lecturer with Tecnopolis/SASIAM (ECMI School for Advanced Studies in Industrial and Applied Mathematics) and member of Tecnopolis/Robotic lab, where he was responsible for design of parallel robotic vision applications. Currently he is also a reviewer for several conferences and for the Journal of System Architectures.José M. Mendías received the M.Sc. and Ph.D. degrees in physics from the Complutense University of Madrid in 1992 and 1998, respectively. He joined the Department of Computer Architecture and Systems Engineering, Complutense University in 1992 as a lecturer, and became an associate professor in 2001. Since 2002, he is Vice-dean of the Computer Science Faculty at the same University. His current research interests include design automation, computer architecture and formal methods.Chantal Ykman-Couvreur is born in 1956. She received the mathematics degree from the Facultes Universitaires Notre-Dame de la Paix of Namur in 1979. She first worked at PHILIPS Research Laboratory of Belgium, from 1979 until 1991. Her main activities were concentrated on information theory and coding, cryptography and multi-level logic synthesis for VLSI circuits. Then, she joined IMEC, where she was responsible at IMEC for the dynamic memory management and the system-level design flow in the Matisse compiler for network protocol components (ATM, Internet Protocol, etc). Currently, she works on the task concurrency management design flow in the Matador project.Francky Catthoor received the engineering degree and a Ph.D. in electrical engineering from the Katholieke Universiteit Leuven, Belgium in 1982 and 1987 respectively. Since 1987, he has headed several research domains in the area of high-level and system synthesis techniques and architectural methodologies, all within the Design Technology for Integrated Information and Telecom Systems (DESICS—formerly VSDM) division at the Inter-university Micro-Electronics Centre (IMEC), Heverlee, Belgium. Currently he is an IMEC fellow. He is part-time full professor at the EE department of the K.U. Leuven.In 1986 he received the Young Scientist Award from the Marconi International Fellowship Council. He has been associate editor for several IEEE and ACM journals, like Transactions on VLSI Signal Processing, Transactions on Multi-media, and ACM TODAES. He was the program chair of several conferences including ISSS97 and SIPS01.Rudy Lauwereins is vice-president of IMEC, Belgiums Interuniversity Micro-Electronic Centre, which performs research and development, ahead of industrial needs by 3 to 10 years, in microelectronics, nano-technology, enabling design methods and technologies for ICT systems. He leads the DESICS division of 185 researchers, currently focused on the development of re-configurable architectures, design methods and tools for wireless and multimedia applications. He is also a part-time Professor at the Katholieke Universiteit Leuven, Belgium. He had obtained a Ph.D. in Electrical Engineering in 1989. Rudy Lauwereins served in numerous international program committees and organisational committees, and gave many invited and keynote speeches. He is vice-chair of the board of DSP Valley and member of the board of several spin-off companies. He is a senior member of the IEEE.     

Multi-Module Multi-Port Memory Design for Low Power Embedded Systems

In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints for embedded applications. Our procedure consists of application of loop transformations and reordering of array accesses to reduce the memory bandwidth followed by memory allocation and assignment procedures based on ILP models and heuristic-based algorithms. The specific problems include determination of (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match well with those obtained by the ILP methods.     

Delphi内存管理与内存泄漏探析

综述了Delphi环境下动态内存分配与释放的方法，分析了内存泄漏的可能原因，并列举了开发“智能型远程作业系统”过程中出现的有关内存泄漏的几个实例。     

Memory Design and Exploration for Low Power, Embedded Systems

In this paper, we describe a procedure for memory design and exploration for low power embedded systems. Our system consists of an instruction cache and a data cache on-chip, and a large memory off-chip. In the first step, we try to reduce the power consumption due to memory traffic by applying memory-optimizing transformations such as loop transformations. Next we use a memory exploration procedure to choose a cache configuration (cache size and line size) that satisfies the system requirements of area, number of cycles and energy consumption. We include energy in the performance metrics, since for different cache configurations, the variation in energy consumption is quite different from the variation in the number of cycles. The memory exploration procedure is very efficient since it exploits the trends in the cycles and energy characteristics to reduce the search space significantly.     

FPGA片内高速存储器的设计和应用

当前在高速数据采集和信号处理系统中，高速存储器的应用十分普遍，而FPGA片内存储器是大存储量高速存储应用的可行方案。本文在简要说明FPGA片内存储器结构和特性的基础上，介绍了片内存储器的构造和仿真方法，并给出了双端口RAM应用的工程实例。FPGA片内存储器容量大、速度高，其设置灵活，便于升级，能够大大简化系统的设计，完全可以满足高速存储的设计要求。     

嵌入式闪存器件技术进展

首先介绍了嵌入式闪存器件的基本工作原理,并根据具体的技术特点和应用整理归纳出了嵌入式闪存器件的三种主流单元结构:单晶体管器件结构、分裂栅器件结构和选择晶体管加存储晶体管的两管器件结构,然后详细分析和比较了这三种器件结构的优缺点。接着进一步重点介绍嵌入式闪存器件近年来的最新发展,列举了传统浮栅器件在65 nm技术代的先进解决方案,并讨论了融合分立电荷陷阱存储概念的新型SONOS和纳米晶存储技术,介绍了该类型技术较之传统浮栅结构的突出优势以及目前的研究进展。最后,对嵌入式闪存技术在32 nm以下节点将遭遇的瓶颈以及进一步发展方向进行分析和展望,给出了可能的解决方案。     

Utilization-Aware Data Variable Allocation on NVM-Based SPM in Real-Time Embedded Systems

With the development of the nonvolatile memory (NVM), using NVM in the design of the cache and scratchpad memory (SPM) has been increased. This paper presents a...     

嵌入式存储器内建自测试的原理及实现

随着集成电路设计规模的不断增大 ,在芯片中特别是在系统芯片 SOC( system on a chip)中嵌入大量存储器的设计方法正变得越来越重要。文中详细分析了嵌入式存储器内建自测试的实现原理 ,并给出了存储器内建自测试的一种典型实现。