A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 $mu$m CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 802.16e signals.      

A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS

A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3 dBm maximum output power at a peak drain efficiency of 27% and 20.5 dBm output power at the 1 dB compression point.     

A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

26 GHz高回退效率Doherty功率放大器

针对功率回退时主路功率放大器不能有效进入饱和状态导致Doherty功率放大器回退效率低的问题,通过降低主路功率放大器的供电电压,实现了高回退效率,同时增大辅路功放管的尺寸弥补了电路的总输出功率。基于0. 1μm GaAs pHMET工艺,设计了一个26 GHz两级非对称的Doherty功率放大器。仿真结果表明,在26 GHz时增益达到16 dB,功放的饱和输出功率为27. 4 dBm,峰值功率附加效率(PAE)为40. 7%,输出功率回退7 dB时PAE仍达到38%,与传统Doherty功率放大器相比具有更高的回退效率,版图的尺寸为3. 2 mm×2. 2 mm。     

1.95GHz Doherty功率放大器设计

基于SMIC 0.18 μm RF CMOS工艺,设计了一款1.95 GHz的Doherty功率放大器.为了保持两路功放相位最大一致性,主功放(PA1)和辅功放(PA2)采用了同一种CMOS功率放大器,仅改变其偏压使其工作在不同模式.CMOS功率放大器为工作于AB类的两级放大电路,集成了输入和级间匹配网络;功分器以及λ...     

A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each other's phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39% PAE (using 1.85-V supply). The active die area is 1.2 mm/sup 2/.     

一种基于阻抗缓冲匹配技术的高效率Doherty放大器

为了在功率回退时满足功率放大器对高效率的要求,提出了一种采用阻抗缓冲匹配技术的Doherty功率放大器。通过负载牵引仿真,得到功放管的最佳基波和谐波负载阻抗。在此基础上,采用一种谐波控制阻抗匹配网络设计方法来设计主/辅路放大器的输出匹配网络,实现了高回退效率。为了验证该方法的有效性,设计并实现了一个1.635 GHz高效率Doherty功率放大器。测试结果表明,该放大器的饱和功率大于44 dBm,峰值效率为75%,6 dB功率回退时的效率为70%。该方法能有效提高Doherty功率放大器的回退效率。     

A 1.8-GHz CMOS Power Amplifier Using a Dual-Primary Transformer With Improved Efficiency in the Low Power Region

A 1.8-GHz CMOS power amplifier for a polar transmitter is implemented with a 0.18- RF CMOS process. The matching components, including the input and output transformers, were integrated. A dual-primary transformer is proposed in order to increase the efficiency in the low power region of the amplifier. The loss induced by the matching network for the low-output power region is minimized using the dual-primary transformer. The amplifier achieved a power-added efficiency of 40.7% at a maximum output power of 31.6 dBm. The dynamic range was 34 dB for a supply voltage that ranged from 0.5 to 3.3 V. The low power efficiency was 32% at the output power of 16 dBm.     

A 2.45-GHz 0.13-μm CMOS PA With Parallel Amplification

In this paper, a fully integrated 0.13-mum CMOS RF power amplifier for Bluetooth is presented. Four differential amplifiers are placed on a single chip and their outputs are combined with an on-chip LC balun structure. This technique allows to have a low impedance transformation ratio for each individual amplifier, and thus a lower power loss. The amplifier achieves a measured output power of 23 dBm at a supply voltage of 1.5 V and a drain efficiency of 35% and a global efficiency of 29%. The parallel amplification topology allows to efficiently control the output power which results in an efficiency improvement when the output power is reduced     

A 1.9-GHz Triple-Mode Class-E Power Amplifier for a Polar Transmitter

A 1.9-GHz CMOS power amplifier for polar transmitters was implemented with a 0.25-mum radio frequency CMOS process. All the matching components, including the input and output transformers, were fully integrated. The concepts of mode locking and adaptive load were applied in order to increase the efficiency and dynamic range of the amplifier. The amplifier achieved a drain efficiency of 33% at a maximum output power of 28dBm. The measured dynamic range was 34dB for a supply voltage that ranged from 0.7 to 3.3V. The measured improvement of the low power efficiency was 140% at an output power of 16dBm     

有限容值隔直电容逆E类功放的分析与设计

提出了一种高效率逆E类功率放大器的设计方法--"有限容值隔直电容设计法",不仅确保放大器保持高工作效率,而且使其具有更低的漏极峰值电压、更大的功率输出能力、更高的上限工作频率及上限输出功率.本文制作了工作于155MHz,输出功率40.07dBm,工作效率83.87%,PAE82.57%的实际电路,实测结果与理论仿真结果基本一致,验证了理论分析的准确性.     

基于EFJ模式的宽带高效率Doherty功率放大器设计

将EFJ模式功率放大器应用于Doherty功率放大器的载波功率放大器,利用EFJ类功率放大器的阻抗特性改善了Doherty功率放大器的带宽。此外,还引入后谐波控制网络来提高Doherty功率放大器的效率。功放的输入匹配电路采用阶跃式阻抗匹配来进一步拓展工作带宽。使用CGH40010F GaN 晶体管设计并加工完成了一款宽带高效率Doherty功率放大器。测试结果显示,在3.2~3.7GHz 频段内,饱和输出功率达到43dBm,饱和漏极效率60%~72.5%,增益大于10dB。功率回退6dB时,漏极效率40%~48.5%。     

一种高效率逆F类Doherty射频功率放大器

为了进一步提高射频功放的输出能力,基于GaN HEMT功率器件,采用平衡式结构设计了一款工作频率为3.3 GHz 3.6 GHz的高效率逆F类Doherty结构射频功放。参照功放管的寄生参数等效电路网络,为获得逆F类功放理想的开关特性,设计了具有寄生参数补偿作用的谐波控制网络来抑制功放输出端的二次、三次谐波,同时结合Doherty功放结构特点,使其在6 dB功率回退的情况下仍具有较高的输出效率。仿真后,可得到其在3.3 GHz^3.6 GHz工作频带内的输出功率在40.4 dBm^41.8 dBm内,PAE为66%~77%,最大DE达到82.6%,功率回退6 dB处,功放的DE仍在69%左右,增益平坦度约为±1.5 dB。     

A highly extended high-efficiency range Doherty power amplifier for high PAPR communication signals

In this paper, design, simulation and fabrication of a new highly extended high-efficiency range Doherty power amplifier (DPA) for high peak to average power ratio (PAPR) communication signals were presented with a main and only a single auxiliary amplifier. In order to extend the output high-efficiency range, it employed non-equal cells as main and auxiliary amplifiers in the complex combining load (CCL) methodology. As a new method, a new design parameter (\(\gamma\)) was added to the conventional complex combining load method. The effect of the new added design parameter on extension of output back-off (OBO) were analyzed and formulated. Also, to verify the proposed methodology, a DPA with 12 dB of OBO was designed, simulated and fabricated for WCDMA applications. Large signal continuous wave measurement results show the power gain of 11 dB with the drain efficiency of 53% at 12 dB of OBO. Two-tone test exhibits the third-order intermodulation distortion lower than ??34 dBc. Modulated wave simulations show over 51% of average drain efficiency and lower than ??31 dBc of adjacent channel leakage power ratio at output power level of 31.5 dBm.     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

Tournament-Shaped Magnetically Coupled Power-Combiner Architecture for RF CMOS Power Amplifier

A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-mum RF CMOS process. All of the matching components, including the input and output transformer, were fully integrated. The amplifier achieved a drain efficiency of 38% at the maximum output power of 31.7 dBm.     

一款X波段高效率GaN负载调制平衡放大器MMIC

报道了一款采用0.25μm GaN HEMT工艺的X波段高效率负载调制平衡放大器芯片。该芯片由两个射频端口的90°Lange耦合器,一对平衡功率放大器和一个控制信号功率放大器组成。通过改变同频率处控制信号的幅度与相位去调制平衡功率放大器的阻抗。在连续波测试条件下,该负载调制平衡放大器芯片在8~11 GHz范围内,最大输出功率为42.5 dBm,饱和效率为45%~55%,当输出功率回退6 dB时,效率为40%~45%。     

Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers

Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.     

新型三路Doherty功放的设计

为了提高数字电视发射机的效率,采用一种新型的三路Doherty电路。基于传输线理论和有源负载牵引理论,推导出三路Doherty的工作原理,同时利用ADS设计一个双3路Doherty电路,并用于数字电视发射机。仿真结果表明,该放大器在功率回退9.1dB时,出现第一个效率峰值点,在整个回退范围内具有3个效率峰值点。实测结果表明,在610MHz中心频率,54dBm输出功率下,该放大器的效率可达41.2%。     

CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm~2.