A subdivision scheme for hexahedral meshes

Published online: 23 July 2002     

An efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000

With the augmentation in multimedia technology, demand for high-speed real-time image compression systems has also increased. JPEG 2000 still image compression standard is developed to accommodate such application requirements. Embedded block coding with optimal truncation (EBCOT) is an essential and computationally very demanding part of the compression process of JPEG 2000 image compression standard. Various applications, such as satellite imagery, medical imaging, digital cinema, and others, require high speed and performance EBCOT architecture. In JPEG 2000 standard, the context formation block of EBCOT tier-1 contains high complexity computation and also becomes the bottleneck in this system. In this paper, we propose a fast and efficient VLSI hardware architecture design of context formation for EBCOT tier-1. A high-speed parallel bit-plane coding (BPC) hardware architecture for the EBCOT module in JPEG 2000 is proposed and implemented. Experimental results show that our design outperforms well-known techniques with respect to the processing time. It can reach 70 % reduction when compared to bit plane sequential processing.     

A methodology for efficient hardware verification

We present a methodology which helps structure the design and verification of hardware circuits. Our methodology supports reusable proofs of hardware components, provides for multiple implementations of the same specification, and allows both bottom up and top down verification styles. We provide mechanical assistance for our methodology in the Nuprl proof development system. Our method exploits Nuprl's rich type theory to encode the specification of a module in the type of the module. This allows us to elegantly describe parameterized hardware modules. The methodology is efficient because: the automated support reduces the amount of information that users must provide and the use of parameterized hardware modules eliminates redundant reasoning among proofs of hardware components. In this paper we explain our methodology and illustrate our approach with several examples of circuit verification.     

A subdivision scheme for Poisson curves and surfaces

The de Casteljau evaluation algorithm applied to a finite sequence of control points defines a Bézier curve. This evaluation procedure also generates a subdivision algorithm and the limit of the subdivision process is this same Bézier curve. Extending the de Casteljau subdivision algorithm to an infinite sequence of control points defines a new family of curves. Here, limits of this stationary non-uniform subdivision process are shown to be equivalent to curves whose control points are the original data points and whose blending functions are given by the Poisson distribution. Thus this approach generalizes standard subdivision techniques from polynomials to arbitrary analytic functions. Extensions of this new subdivision scheme from curves to tensor product surfaces are also discussed.     

Design,implementation and analysis of hardware efficient stream ciphers using LFSR based hash functions

Design and implementation of hardware efficient stream ciphers using hash functions and analysis of their periodicity and security are presented in this paper. The hash generation circuits used for the design and development of stream ciphers are low power, low hardware complexity Linear Feedback Shift Register (LFSR) based circuits. One stream cipher design uses LFSR based Toeplitz hash generation circuit together with LFSR keystream generator circuit, while the other design combines LFSR based filter generator circuit with LFSR based polynomial modular division circuit. Both designs possess good security and periodicity properties for the keystreams generated. The developed circuits can compete with the most popular classic LFSR based stream ciphers in hardware complexity at the same time providing additional advantage that the same circuit can be used for hash generation.     

A new storage scheme for an efficient implementation of the sparse matrix-vector product

The most critical point in the implementation on a vector computer of iterative methods to solve sparse linear algebraic systems is the sparse matrix-vector product. Therefor we have compared its performance under three different sparse matrix storage schemes found in literature. These schemes have been tested on a FPS M64/330 using matrices similar to those arising in finite element or finite difference discretizations.

The results are reported and discussed. On the basis of them a new storage scheme is proposed and tested in similar situations. The obtained performance is never worse and often much better than those of the other schemes we have analyzed.     

Dynamic modeling of butterfly subdivision surfaces

The authors develop integrated techniques that unify physics based modeling with geometric subdivision methodology and present a scheme for dynamic manipulation of the smooth limit surface generated by the (modified) butterfly scheme using physics based “force” tools. This procedure based surface model obtained through butterfly subdivision does not have a closed form analytic formulation (unlike other well known spline based models), and hence poses challenging problems to incorporate mass and damping distributions, internal deformation energy, forces, and other physical quantities required to develop a physics based model. Our primary contributions to computer graphics and geometric modeling include: (1) a new hierarchical formulation for locally parameterizing the butterfly subdivision surface over its initial control polyhedron, (2) formulation of dynamic butterfly subdivision surface as a set of novel finite elements, and (3) approximation of this new type of finite elements by a collection of existing finite elements subject to implicit geometric constraints. Our new physics based model can be sculpted directly by applying synthesized forces and its equilibrium is characterized by the minimum of a deformation energy subject to the imposed constraints. We demonstrate that this novel dynamic framework not only provides a direct and natural means of manipulating geometric shapes, but also facilitates hierarchical shape and nonrigid motion estimation from large range and volumetric data sets using very few degrees of freedom (control vertices that define the initial polyhedron)     

Real-time geometric deformation displacement maps using programmable hardware

Striving for photorealism, texture mapping, and its more advanced variations, bump and displacement mapping, have all become fundamental tools in computer graphics. Recently, the introduction of programmable graphics hardware has enabled the employment of displacement mapping in real-time applications. While displacement mapping facilitates the actual modification of the underlying geometry, it is constrained by being an injective mapping. Further, it is also limited because it usually maps the geometry of the (low-resolution) smooth base surfaces, typically by displacing their vertices. Drawing from recent work on deformation displacement mapping (DDM) [4], in this paper we offer real-time solutions to both these limitations. Our solutions make it possible to employ the DDM paradigm on programmable graphics hardware. By reversing the roles of the base surfaces and their geometric details, both the one-to-one constraint and the base surface resolution limitation are resolved. Furthermore, this role reversal also paves the way for other benefits such as a tremendous decrease in the memory consumption of geometric detail information in the DDM and the ability to animate the details over the base surface. We show that the presented scheme can be used effectively to generate highly complex renderings and animations, in real time, on modern graphics hardware. The capabilities of the proposed method are demonstrated for both rational parametric base surfaces and polygonal base surfaces.     

A 4-point interpolatory subdivision scheme for curve design

A 4-point interpolatory subdivision scheme with a tension parameter is analysed. It is shown that for a certain range of the tension parameter the resulting curve is C¹. The role of the tension parameter is demonstrated by a few examples. The application to surfaces and some further potential generalizations are discussed.     

Composite freeform surface reconstruction using recursive interpolating subdivision scheme

Composite freeform surface reconstruction from 3D scanned data of a physical model has become a more and more important topic in the field of CAD/CAE/CAM. By repeated application of a fixed set of recursive interpolation subdivision schemes on the initial mesh of the 3D sparse scanned data of a physical model, a polygonal model of composite freeform surface can be constructed. In the paper, the algorithm for constructing the initial triangular mesh from 3D sparse scanned data is presented. The unified recursive interpolating subdivision scheme for triangular mesh is proposed. A special quad-tree data structure is suggested to store all the necessary information of the vertices and elements of the polygonal model. Examples of composite surface reconstruction are provided to explain the distinguished superiority of subdivision scheme for reconstructing the arbitrary topological complex surface.     

A dot product neuron for hardware implementation of competitivenetworks

Competitive models based on a simple dot product neuron often deal with normalized vectors, which adds a hard computational cost. Using Euclidean distance nodes without normalization is only a partial solution, because they are less plausible from a biological point of view and the computational cost of the Euclidean distance is greater than that of the dot product. In this work the author proposes a dot product neuron, formally equivalent to a Euclidean neuron, which does not require vector normalization. The only requirement for such a neuron model is subtracting from the dot product an iteratively computed bias. A simple incremental learning rule for this neuron is also introduced. The proposed model is suitable for hardware implementation of competitive networks.     

A new interpolation subdivision scheme for triangle/quad mesh

In this paper, we present a new interpolation subdivision scheme for mixed triangle/quad meshes that is C¹ continuous. The new scheme is capable of reproducing the well-known four-point based interpolation subdivision in the quad region but does not reproduce Butterfly subdivision in the triangular part. The new scheme defines rules that produce surfaces both at the regular quad/triangle vertices and isolated, extraordinary points. We demonstrate the visually satisfying of our surfaces through several examples.     

Compact yet efficient hardware implementation of artificial neural networks with customized topology

There are several neural network implementations using either software, hardware-based or a hardware/software co-design. This work proposes a hardware architecture to implement an artificial neural network (ANN), whose topology is the multilayer perceptron (MLP). In this paper, we explore the parallelism of neural networks and allow on-the-fly changes of the number of inputs, number of layers and number of neurons per layer of the net. This reconfigurability characteristic permits that any application of ANNs may be implemented using the proposed hardware. In order to reduce the processing time that is spent in arithmetic computation, a real number is represented using a fraction of integers. In this way, the arithmetic is limited to integer operations, performed by fast combinational circuits. A simple state machine is required to control sums and products of fractions. Sigmoid is used as the activation function in the proposed implementation. It is approximated by polynomials, whose underlying computation requires only sums and products. A theorem is introduced and proven so as to cover the arithmetic strategy of the computation of the activation function. Thus, the arithmetic circuitry used to implement the neuron weighted sum is reused for computing the sigmoid. This resource sharing decreased drastically the total area of the system. After modeling and simulation for functionality validation, the proposed architecture synthesized using reconfigurable hardware. The results are promising.     

Interpolation over arbitrary topology meshes using a two-phase subdivision scheme

The construction of a smooth surface interpolating a mesh of arbitrary topological type is an important problem in many graphics applications. This paper presents a two-phase process, based on a topological modification of the control mesh and a subsequent Catmull-Clark subdivision, to construct a smooth surface that interpolates some or all of the vertices of a mesh with arbitrary topology. It is also possible to constrain the surface to have specified tangent planes at an arbitrary subset of the vertices to be interpolated. The method has the following features: 1) it is guaranteed to always work and the computation is numerically stable, 2) there is no need to solve a system of linear equations and the whole computation complexity is O(K) where K is the number of the vertices, and 3) each vertex can be associated with a scalar shape handle for local shape control. These features make interpolation using Catmull-Clark surfaces simple and, thus, make the new method itself suitable for interactive free-form shape design.     

Adaptive mesh subdivision for efficient light baking

Light baking has long been a popular technique for real-time rendering. It usually precomputes and bakes the global lighting effects as vertex attributes or textures. Vertex baking requires less memory but can cause artifacts for large triangles. Texture baking can avoid this and generate a high-quality visual effect in real-time rendering. However, it requires significant memory consumption, which may limit the real-time performance and usage. To address this problem, we propose an adaptive mesh subdivision algorithm for memory-efficient light baking, including a fast triangle subdivision level determination method and an optimized solution to calculate vertex colors. Only the subdivided mesh is required during the real-time rendering. Therefore, memory requirements can be significantly reduced while keeping the visual effect. Besides, the subdivision level is allowed to be intuitively controlled by users with a specified parameter. Our algorithm can be easily implemented on commodity graphics hardware and integrated in existing real-time applications such as online preview systems.     

An associative memory-based learning model with an efficient hardware implementation in FPGA

In this paper we propose a learning model based on a short- and long-term memory and a ranking mechanism which manages the transition of reference vectors between the two memories. Furthermore, an optimization algorithm is used to adjust the reference vectors components as well as their distribution, continuously. Comparing to other learning models like neural networks, the main advantage of the proposed model is that a pre-training phase is unnecessary and it has a hardware-friendly structure which makes it implementable by an efficient LSI architecture without requiring a large amount of resources. A prototype system is implemented on an FPGA platform and tested with real data of handwritten and printed English characters delivering satisfactory classification results.     

WCDMA中LMS自适应天线阵的硬件实现

本文针对WCDMA的特点设计了一种利用LMS算法的自适应天线阵.实现时DSP采用TI公司的TMS320C6701,并采用了零中频I/Q调制解调技术,工作于1.95GHz.该天线阵结构简单,复杂度低.