ADC系统性能测试及提高

本文简介了一种基于FPGA和DSP,对ADC系统进行性能分析并对其转换后的数字进行数据采集的方法。其中性能分析主要是针对ADC的信噪比和无杂散动态范围。同时,主要介绍了ADC系统中时钟、电源、模拟信号输入等方面性能改善的方法。并以此来提高SNR,实现对有效位数和整体性能的提高。     

高速高分辨率ADC有效位测试方法研究

介绍了ADC的有效位计算公式,分析了ADC的性能参数测试方法,给出了ADC的有效位测试解决方案。对FFT方法在ADC性能测试中的应用做了深入探讨,包括频谱泄露、相干采样和加窗函数等。采用一种改进的FFT方法对TI公司的ADS5400进行有效位测试,得到其在400 MS/s采样率的有效位ENOB=9.12 bit(fin=1.123 MHz)。     

多阶微分采样及其在高速ADC系统中的应用

首先阐明了多阶微分采样的原理，给出了更为简洁的完美重构条件。然后根据该条件导出了多阶微分采样完美重构滤波器组的频谱响应和理想的冲激响应。时理想滤渡器的冲激响应进行了延迟、截断和加窗来得到可实现的有限冲激（FIR）重构滤波器组，从而实现了高速的多阶微分采样型ADC系统。理论分析和仿真结果说明本文设计的重构滤波器组可以对多阶微分采样进行很好的重构，整个系统信纳比（SINAD）平均可迭83．3dB，无伪波动态范围（SFDR）平均达102．7dB。     

一种10 bit 1 MS/s SAR ADC的设计实现

基于0.13μm CMOS工艺,设计了一种采样率达到1 MS/s的10位逐次逼近模数转换器,其中逐次逼近数字控制逻辑采用全定制的方法,减小了数字单元的面积和功耗;比较器中的预放大器分别采用了二极管连接和开关管复位的方式将各级运放的输出短接,加快比较速度,最后一级锁存器采用改进的两级动态锁存器,进一步提升比较速度的同时降低了失调误差。实验结果表明,1.2 V电源电压下,所设计的ADC采样率达到1 MS/s,输入信号频率为12.5 kHz时,测得的输出信号信噪比为54.47 dB,SFDR为45.18 dB。     

Nanoscale triple-gate FinFET design considerations based on an analytical model of short-channel effects

In this paper,a three-dimensional(3-D)analytical model for short-channel effects(SCEs)in a nanoscale triple-gate(TG)FinFET is derived based on solving a boundary value problem using the 3-D Poisson’s equation.This model is validated using 3-D numerical simulations(TCAD Sentaurus).Results show that SCEs in a TG FinFET can be controlled by reducing either the fin thickness(D)or height(H).On the other hand,when fixing the drive capability of turn-on current,i.e.fixing the total width of the conductive channel,and changing the ratio of D and H,there exists a case where SCEs are worst,and SCEs can be reduced by either increasing or decreasing the ratio from the worst case.This SCEs model can be used to predict the minimum channel length(Lmin)of a device when D,H,and tox are fixed,while keeping SCEs at a tolerable level.Based on the analytical model,the insights into the physics of SCEs in nanoscale TG FinFET are discussed,and design considerations are investigated.     

一种13bit 40MS/s采样保持电路设计

设计了一个用于13bit40MS/s流水线ADC中的采样保持电路。该电路采用电容翻转结构,主运算放大器采用增益提高型折叠式共源共栅结构,以满足高速和高精度的要求。为减小与输入信号相关的非线性失真以获得良好的线性度,采用栅压自举开关。采用电源电压为3.3V的TSMC0.18μm工艺对电路进行设计和仿真,仿真结果表明,在40MHz的采样频率下,采用保持电路的SNDR达到84.8dB,SFDR达到92dB。     

基于Verilog-A行为级模型的三阶单环调制器设计与仿真

提出了一种三阶单环局部反馈的Sigma-Delta调制器结构.对传统的噪声传输函数引入极点加以修正,最终采用巴特沃兹高通滤波器原型确定调制器的噪声传输函数,在采用Matlab Simulink进行参数优化和仿真的基础上,编写了各电路子模块Verilog-A程序,并以此搭建整体调制器模型进行行为级建模.仿真结果表明,该三阶单环局部反馈的Sigma-Delta调制器结构能实现精度为16 bit,无杂散动态范围(SFDR)大于96 dB,时钟频率最高5.12 MHz,过采样率为128,输入信号带宽最大为20 kHz的调制器模型.     

用于高速CMOS图像传感器的电容复用型循环ADC

设计了一种用于高速CMOS图像传感器的列并行标志冗余位(RSD)循环式模/数转换器(ADC)。该ADC在每次循环中采样和量化输入信号同步进行,速度比传统的循环式ADC提高了1倍。利用电容复用技术,对于像素输出信号的相关双采样(CDS)操作和精确乘2运算,将仅使用1个运放和4组电容来实现,减小了芯片面积。通过0.18μm标准CMOS工艺完成了ADC电路设计和仿真。SPICE仿真结果表明,在4 MS/s的采样速度和1.8 V电源电压下,ADC的SNDR达到55.61 dB,有效位数为8.94 bit,功耗为1.34 mW,满足10 bit精度高速CMOS图像传感器系统的应用要求。     

一种增益增强型套筒式运算放大器的设计

设计了一种用于高速ADC中的全差分套筒式运算放大器。从ADC的应用指标出发,确定了设计目标,利用开关电容共模反馈、增益增强等技术实现了一个可用于12bit精度、100MHz采样频率的高速流水线(Pipelined)ADC中的运算放大器。基于SMIC0.13μm,3.3V工艺,Spectre仿真结果表明,该运放可以达到105.8dB的增益,单位增益带宽达到983.6MHz,而功耗仅为26.2mW。运放在4ns的时间内可以达到0.01%的建立精度,满足系统设计要求。     

激光雷达的高速数据采集系统设计

设计并实现了应用于采集激光雷达回波信号的双路高速数据采集系统I该系统采用现场可编程门阵列（FPGA）作为主控制器,闪电型芯片A139054作为高速模数转换器,通用串行总线（USB）作为与计算机数据传输接口;对系统进行了软件仿真,解决了关键线路的信号完整性问题;双通道采样率均为200MHz,分辨率为8位,缓存为5kB;实验表明：在输入为70MHz满幅正弦波的条件下,动态测量的信噪比大于43dB,动态有效位（ENOB）达到7位以上,满足了武汉大学最新研制的激光雷达对回波信号数据采集的需要。     

高阶∑△ADC中积分器的设计

基于N阱0.6μm DPDM CMOS工艺,完成了高阶∑△ADC中第一级积分器的设计。分析了开关电容积分器的非理想特性,同时设计了一个对寄生电容不敏感的同相开关电容(SC)积分器,并特别采用旁路电容减小沟道电荷注入引起的谐波失真和噪声。在cadence下的电路仿真表明,积分器具有-104.9dB等效输入噪声;利用MATLAB进行系统仿真,∑△ADC的信号噪声畸变比(SNDR)达到100.5dB,满足系统16bit的要求。     

A 4‐bit ultra‐wideband complementary metal‐oxide‐semiconductor attenuator with low root‐mean‐square amplitude error

This article presents the 4‐bit ultra‐wideband complementary metal‐oxide‐semiconductor (CMOS) attenuator in a standard 0.18‐μm CMOS process. This design adopts switched bridge‐T type topologies for each attenuation bit. Based on insertion losses and input P_1‐dB considerations, the circuit performances can be optimized by the proper bit ordering arrangement. Therefore, the bit ordering 0.5‐4‐2‐1 dB is employed in the 4‐bit attenuator. Moreover, series inductors are added between each bit to further improve the input and output return losses. Measured results demonstrate that the attenuation range of the circuit is 7.5 dB with 0.5 dB step and the root‐mean‐square (RMS) amplitude error is between 0.11 and 0.13 dB from 3.1 to 10.8 GHz. The differences between simulated and measured RMS amplitude errors are less than 0.2 dB, which demonstrates the good agreement and feasibility of the design concept. The measured input P_1‐dB is 15 dBm at 5 GHz and the chip area is 1.12 mm² including all testing pads.     

A low sampling clock,high bandwidth,master‐slave track and hold amplifier

A fully‐differential master‐slave track and hold amplifier (MSTHA), with one‐input, four‐output and nearly 20 GHz bandwidth is designed and fabricated in 0.13‐μm SiGe BiCMOS technology. Operating with a single +3.3 V supply, 0 V input direct‐voltage, 2 GHz sampling clock input and 5 dBm input power, the MSTHA achieves a spurious free dynamic range (SFDR) of less than ?31 dB up to 20 GHz, 0.5 mV_rms output noise amplitude (RMS, root of mean square) and totally power consuming about 1.3 W.     

改进的低功耗两步式ADC结构

本文提出了一种改进的两步式ADC拓扑结构。当ADC的分辨率为n位时,这种结构只需要(2~(n/2+1-2))或(2~(n-1)/2+2~(n+1/2)-2)个比较器。与传统的两步式ADC相比,其比较器数目的大大减少,使得ADC电路的功耗和芯片面积随之显著降低。此结构适用于高速便携式VLSI系统。     

智能温度传感芯片中Δ-Σ调制器的设计

从模数转换的基本理论出发,在对一阶Δ-Σ调制器原理深入解析的基础上,得到Δ-ΣADC动态输入范围的计算方法。利用Matlab simulink建立了二阶Δ-Σ调制器系统模型,对调制器电路进行仿真和参数优化,对其性能进行了有效评估。使用轨对轨折叠式共源共栅运算放大器作为调制器的积分器,增大了调制器的动态输入范围;设计的高速比较器将NMOS负载管交叉耦合从放大器输出端引入正反馈,提高了转换速度。设计实现了一款适用于14 bit温度转换芯片的二阶△-∑调制器,信噪比SNR可达87 dB。     

A millimeter‐wave CMOS power amplifier design using high‐Q slow‐wave transmission lines

A three‐stage 60‐GHz power amplifier (PA) has been implemented in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. High‐quality‐factor slow‐wave coplanar waveguides (S‐CPW) were used for input, output and inter‐stage matching networks to improve the performance. Being biased for Class‐A operation, the PA exhibits a measured power gain G of 18.3 dB at the working frequency, with a 3‐dB bandwidth of 8.5 GHz. The measured 1‐dB output compression point (OCP_1dB) and the maximum saturated output power P_sat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16%. The die area is 0.52 mm² (875 × 600 μm²) including all the pads, whereas the effective area is only 0.24 mm². In addition, the performance improvement of the PA in terms of G, OCP_1dB, P_sat, PAE and the figure of merit using S‐CPW instead of thin film microstrip have been demonstrated. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:99–109, 2016.     

A spatial power limiter using a nonlinear frequency selective surface

A novel spatial power limiter based on nonlinear frequency selective surface (FSS) is presented for high power electromagnetic (HPEM) wave protection. Embedded with Schottky diodes, the nonlinear FSS not only reflects out‐of‐band electromagnetic incidence like a filter, but also exhibits a power‐limiting characteristic, allowing low‐loss transmission for an in‐band low‐power incidence while rejecting a high‐power one. Such a FSS with 4 × 4 unit cells is designed, fabricated and measured. Results demonstrate its pass‐band centering at 2.5 GHz, power density threshold of about 0.27 W/m² and shielding effectiveness (SE) up to 20 dB at 2.5 GHz.     

LTCC‐based monolithic system‐in‐package (SiP) module for millimeter‐wave applications

A miniature LTCC system‐in‐package (SiP) module has been presented for millimeter‐wave applications. A typical heterodyne 61 GHz transmitter (Tx) has been designed and fabricated in a type of the SiP module as small as 36 × 12 × 0.9 mm³. Five active chips including a mixer, driver amplifier, power amplifier, and two frequency multipliers were mounted on the single LTCC package substrate, in which all passive circuits such as a stripline (SL) BPF, 2 × 2 array patch antenna, surface‐mount technology (SMT) pads, and intermediate frequency (IF) feeding lines have been monolithically embedded by using vertical and planar transitions. The embedded SL BPF shows the center frequency of 60.8 GHz, BW of 4.1%, and insertion loss of 3.74 dB. The gain and 3‐dB beam width of the fabricated 2 × 2 array patch antenna are 7 dBi and 36 degrees, respectively. The assembled LTCC 61 GHz Tx SiP module achieves an output power of 10.2 dBm and an up‐conversion gain of 7.3 dB. Because of the integrated BPF, an isolation level between a local oscillation (LO) and RF signal is below 26.4 dBc and the spurious level is suppressed by lower than 22.4 dBc. By using a 61 GHz receiver (Rx) consisting of off‐the‐shelf modules, wireless communication test was demonstrated by comparing measured IF spectrums at the Tx and Rx part.     

Ka-band ultra low voltage miniature sub-harmonic resistive mixer with a new broadside coupled Marchand balun in 0.18-μm CMOS technology

A Ka-band sub-harmonically pumped resistive mixer(SHPRM) was designed and fabricated using the standard 0.18-μm complementary metal-oxide-semiconductor(CMOS) technology.An area-effective asymmetric broadside coupled spiral Marchand balance-to-unbalance(balun) with magnitude and phase imbalance compensation is used in the mixer to transform local oscillation(LO) signal from single to differential mode.The results showed that the SHPRM achieves the conversion gain of-15--12.5 dB at fixed fIF=0.5 GHz with 8 dBm LO input power for the radio frequency(RF) bandwidth of 28-35 GHz.The in-band LO-intermediate freqency(IF),RF-IF,and LO-RF isolations are better than 31,34,and 36 dB,respectively.Besides,the 2LO-IF and 2LO-RF isolations are better than 60 and 45 dB,respectively.The measured input referred P1dB and 3rd-order inter-modulation intercept point(IIP3) are 0.5 and 10.5 dBm,respectively.The measurement is performed under a gate bias voltage as low as 0.1 V and the whole chip only occupies an area of 0.33 mm2 including pads.     

低压电力线OFDM系统中交织算法的改进

迎合智能电网的需求,采用先进的OFDM技术设计了低压电力线通信系统,由电力线信道特性,建立了合理的信道模型,并针对多径效应引起的频率选择性衰落和脉冲噪声引起的突发错误这两大难点,对此系统的交织算法做了改进,分别对时域和频域的连续错误进行了交织。仿真实验得出,改进后的交织算法更有效地将突发错误离散为随机错误,使系统误码率性能大约有2 dB的提高,实现了数据的更可靠传输,可广泛应用于低压电力线自动抄表领域。