An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards

In high-speed printed circuit boards, the decoupling capacitors are commonly used to mitigate the power-bus noise that causes many signal integrity problems. It is very important to determine their proper locations and values so that the power distribution network should have low impedance over a wide range of frequencies, which demands a precise power-bus model considering the decoupling capacitors. However, conventional power-bus models suffer from various problems, i.e., the numerical analyzes require huge computation while the lumped circuit models show poor accuracy. In this paper, a novel power-bus model has been proposed, which simplifies the n-port Z-parameters of a power-bus plane to a lumped T-network circuit model. It exploits the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors, while the conventional lumped models assume that all decoupling capacitors are connected in parallel, independently with each other. It also models the equivalent electrical parameters of the board parasitic precisely, while the conventional lumped models employ only the inter-plane capacitance of the power-ground planes. Although it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. Consequently, the proposed model enables a quick and accurate optimization of power distribution networks in the frequency domain by determining the locations and values of the decoupling capacitors.     

Analysis of power/ground-plane EMI decoupling performance using thepartial-element equivalent circuit technique

The design of printed circuit (PC) boards with decoupling capacitors has been the subject of debate and different opinions for many years. The design and electrical impact of the capacitors has been difficult to separate from all other electrical interactions occurring on a conventional PC board populated with integrated circuits. This work demonstrates how the partial-element equivalent circuit (PEEC) modeling technique can be used to accurately predict the performance of various decoupling design strategies. Computer modeling using the PEEC approach is very flexible due to the ease of mixing physical geometries with a large number of circuit elements. Also, the compute time for such practical mixed EM and circuit problems are relatively short. Using this technique, the usual iteration between a number of different designs of test boards can be avoided. We show that the change of the voltage across the PC board, or the voltage gradient, can be used as an effective tool for the improvement of the decoupling efficiency     

Estimating the noise mitigation effect of local decoupling in printed circuit boards

Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bits noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are developed, so that the noise mitigation effect can then be estimated using the previously developed expression. The difference between the estimates and measurements is approximately 1 dB, which demonstrates the application of these closed-form expressions in the PCB power bus designs. Shared-via decoupling, capacitors sharing vias with device power/ground pins, is also modeled as an extreme case of local decoupling.     

基于ANSYS 的DDR4 SDRAM 信号完整性仿真方法研究

半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic Random Access Memory, DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS 软 件和IBIS 5. 0 模型的DDR4 SDRAM 信号完整性仿真方法。利用IBIS 5. 0 模型中增加的复合电流(Composite Current) 、同步开关输出电流等数据,对DDR4 SDRAM 高速电路板的信号完整性进行更准确的仿真分析。仿真结果 表明:高速信号在经过印制板走线和器件封装后,信号摆幅和眼图都有明显恶化;在仿真电路的电源上增加去耦 电容后,信号抖动和收发端同步开关噪声(Synchronous Switching Noise, SSN)都得到明显改善;在不加去耦电容的 情况下,将输入信号由PRBS 码换成DBI 信号,接收端的同步开关噪声有所改善,器件功耗可以降为原来的一半。     

An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it. Full-wave methods are often employed to study the power integrity problem. While full-wave methods can be accurate, they are time and memory consuming. The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network. However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency. A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes. Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced. Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network. While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes. Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived. This allows both frequency and transient responses to be done with SPICE simulation.     

Lumped-circuit model extraction for vias in multilayer substrates

Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted in a systematic manner using this approach. A closed-form expression for via self inductance is further derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expression can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power-bus impedance as well as effective frequency range of decoupling capacitors.     

Quantifying SMT decoupling capacitor placement in dc power-busdesign for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach     

Power bus decoupling on multilayer printed circuit boards

Guidelines for the selection and placement of decoupling capacitors that work well for one-sided or two-sided printed circuit boards are not appropriate for multilayer boards with power and ground planes. Boards without internal planes take advantage of the power bus inductance to help decouple components at the higher frequencies. An effective decoupling strategy for multilayer boards must account for the low inductance and relatively high capacitance of the power bus     

Study of the ground bounce caused by power plane resonances

We describe Delta-I noise caused by power plane resonances in multilayer boards. First, we study the effect of power plane resonances on the ground bounce of the system by performing finite-difference time-domain (FDTD) simulations. We simulate the voltage fluctuations at one point of the printed circuit board (PCB) due to a current surge between the power planes in a different point. Next, two methods to prevent this ground bounce effect are investigated. The first method consists of adding lumped capacitances to the design. The effect of one large capacitor is compared to the effect of adding a “wall” of smaller capacitors. A second approach is to isolate the chips by etching a slot around the sensitive integrated circuits (ICs) and connecting both sides by a small inductor. Both methods provide excellent protection against power plane resonances     

Simultaneous switching noise mitigation in PCB using cascaded high-impedance surfaces

A novel concept for ultra-wide-bandwidth suppression of simultaneous switching noise (SSN) in high-speed printed circuit boards (PCBs) is proposed and implemented. This method consists of cascading high-impedance surfaces (HIS) with different stop bands, creating rejection over a wide frequency region. A PCB with the cascaded HIS design has been successfully fabricated and tested.     

Estimating the power bus impedance of printed circuit boards with embedded capacitance

Embedded capacitance is an alternative to discrete decoupling capacitors and is achieved by enhancing the natural capacitance between closely spaced power and return planes. This paper employs a simple cavity model to investigate the features affecting the power bus impedance of printed circuit boards with embedded capacitance.     

FDTD modeling incorporating a two-port network for I/O line EMIfiltering design

Electromagnetic interference (EMI) filters are often utilized on I/O lines to reduce high-frequency noise from being conducted off the printed circuit board (PCB) and causing EMI problems. The filtering performance is often compromised at high frequencies due to parasitics associated with the filter itself, or the PCB layout and interconnects. Finite difference time domain (FDTD) modeling can be used to quantify the effect of PCB layout and interconnects, as well as filter type, on the EMI performance of I/O line filtering. FDTD modeling of a T-type and π-type filter consisting of surface-mount ferrites and capacitors is considered herein. The FDTD method is applied to model PCB layout and interconnect features, as well as the lumped element components, including the nonlinear characteristics of ferrite surface-mount parts. The EMI filters with ferrites; are included in the modeling by incorporating the time-domain Y-parameters of the two-port network into the FDTD time-marching equations. Good agreement between the FDTD modeling and S-parameter measurements supports the new FDTD algorithm for incorporating two-port networks     

Analysis of the bounces on the power/ground plane structures byplanar circuit model and APA-E algorithm

In this paper, a novel effective numerical algorithm for analysis of the bounces on the power/ground-plane structure in printed circuit board (PCB) or multichip modules (MCMs) is proposed, which is based upon planar circuit model combined with APA-E algorithm. Firstly, the planar circuit model is developed to simulate the power/ground bounces when switching current is added in the structure. Secondly, on the basis of the abstract Pade approximant and the extrapolation algorithm, the APA-E algorithm is proposed. The classical multivariable rational Pade approximant is also constructed for comparison. Compared with finite difference time domain (FDTD) method, the new algorithm can provide a very accurate approximant in time domain, only requires little storage and CPU time. At last, attaching the decoupling capacitors for reducing the bounces on lossy power/ground-plane structures is also analyzed with this method     

多层封装基板中同步开关噪声研究

文章以栅格阵列封装(land grid array,LGA)模型为研究对象,分析了多层封装基板中的同步开关噪声(simultaneous switching noise,SSN)问题。首先利用频域仿真工具PowerSI得到了键合线和信号布线的S参数模型。然后通过在电路仿真工具HSPICE中加载封装结构的S参数模型和驱动器模型来仿真同步开关噪声。最后在设计中选取在多层基板上添加去耦电容的方式来减小同步开关噪声。仿真结果表明,通过在本LGA多层基板设计中添加110pF容值的去耦电容,可以较好地减少同步开关噪声,满足设计要求。     

基于FPGA的边界扫描测试系统设计

随着集成电路技术的快速发展,传统的PCB电路板测试所采用探针的方法已经不现实,边界扫描技术解决了这一传统的PCB板测试的难题。本文设计的边界扫描测试系统可以实现对JTAG的访问以及完成对被测电路板器件IDCODE等方面的测试。实验结果表明,该系统测试方便,简单。     

高速PCB电源完整性研究

一块成功的高速印刷电路板(PCB),需要做到信号完整性和电源完整性,首先必须降低地弹.为了滤除地弹骚扰,推荐在电源/地平面对上,安放去耦电容。     

Damping of cavity-mode resonances in PCB power-bus structures using discrete capacitors

In this paper, the impact of lumped elements connected to the power-bus of high-speed printed circuit boards is investigated and a computationally efficient expression of the resulting input impedance is derived. This result builds the theoretical basis of a novel technique suppressing cavity-mode resonances within the power-bus using discrete capacitors. Guidelines for an optimized selection and placement of these capacitors are specified. The theoretical results are well confirmed by measurements.     

Modeling and measurement of simultaneous switching noise coupling through signal via transition

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach.     

基于Sigrity仿真的串扰和SSN探讨分析

本文介绍了串扰和SSN的基本原理,并结合实例,利用Sigrity公司的软件对串扰和SSN的影响及其解决办法做了介绍。并重点介绍了通过减小布线层和参考层间的介质厚度来减小串扰,且通过添加去耦电容来使SSN对驱动电压和平面反弹的影响最小化。     

GA-optimized decoupling capacitors damping the rectangular power-bus' cavity-mode resonances

The genetic algorithm (GA) is suggested to find the decoupling capacitors for suppressing the cavity-mode resonances in the printed circuit board power-bus structure. The optimal positions and circuital values of decoupling capacitors are efficiently determined to selectively mitigate specific resonance peaks. The optimization of the damping is validated with the measurement and develops to multiresonance modes' damping.