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1.
《Solid-State Circuits, IEEE Journal of》1984,19(3):299-305
A new family of high-speed bipolar masterslice cell arrays has been developed. The chips offer ECL 10K or 100K compatibility, equivalent basic gate delays of 230 ps, and integration levels up to 7600 transistors adequate for 2600 gate functions. Extensive use of three-level series-gated current-mode logic circuitry results in a minimum speed-power product of 0.37 pJ and a maximum packing density of 130 gate functions/mm/SUP 2/. The cell library contains 81 cell types, including multicell macro building blocks. A CAD system featuring both automatic cell placement and intercell routing supports the customization of the masterslices. Processing technology is characterized by 2 /spl mu/m structures, 1:1 projection lithography, ion-implanted base and emitter, oxide isolation, and three metal layers with polyimide insulation. 相似文献
2.
《Solid-State Circuits, IEEE Journal of》1981,16(5):558-562
A bipolar 2500-gate subnanosecond masterslice LSI has been developed for use in computer mainframes. A walled-emitter structure has been realized by using double boron ion implantation with an n-type epitaxial layer to obtain high performance and high packing density. A new cell composed of a pair of adjacent gates provides high utilization of input transistors. A gate delay of 0.58 ns with power dissipation of 0.54 mW/gate has been achieved. The masterslice has been applied to an 18-bit memory data register circuit consisting of 1983 internal logic gates and has been mounted on a new 224-pin plug-in package. 相似文献
3.
《Solid-State Circuits, IEEE Journal of》1987,22(2):202-207
A 7 K-gate bipolar masterslice providing high-speed gates as well as highly functional cells has been developed. A basic mixed cell consisting of both a nonthreshold logic (NTL) gate and an LCML macrocell is introduced. A 1-/spl mu/m-rule super self-aligned process technology (SST-1A) is adopted in combination with three-level metallization technology. A basic NTL gate delay of 50 ps has been achieved with a power dissipation of 1.84 mW. For flip-flop (FF) performance using a macrocell, a toggle frequency of up to 2.6 GHz is obtained with 3.78 mW/FF. For application, a 24-bit parallel multiplier having a multiplication time of 12.8 ns is customized with a power dissipation of 5.1 W. 相似文献
4.
《Solid-State Circuits, IEEE Journal of》1984,19(4):474-479
An ECL100K-compatible, bipolar, subnanosecond macrocell array has been developed. A new macrocell structure is proposed, using a 2-/spl mu/m design rule and four-level metallization SST-2 process. A basic macrocell consisting of 10 transistors and 12 resistors is formed by the stretched Pt-Si patterns for the electrodes of base and resistor. The basic circuit structure is a two-level series-gated ECL circuit with emitter-follower output. The high performance of the 333 ps/cell and an 800-MHz toggle frequency of a master-slave flip-flop were achieved using a 0.2-mA switching current. The gate count of the chip is equivalent to 6.8 to 8.3K gates. 相似文献
5.
《Solid-State Circuits, IEEE Journal of》1982,17(5):907-912
Combining advanced 2 /spl mu/m CMOS technology with a newly developed double layer metallization technology, a high-performance 6K-gate CMOS gate array has been developed, featuring an inverter propagation delay time of 0.4 ns with a power dissipation of 10 /spl mu/W/MHz/stage. As a demonstration vehicle of the high-performance gate array, a 16 bit/spl times/16 bit parallel multiplier has been designed and fabricated in which 3365 basic cells are used. Typical multiplying time has been measured to be 130 ns at a 5 MHz clock rate with a power dissipation of 275 mW. 相似文献
6.
《Solid-State Circuits, IEEE Journal of》1987,22(2):198-201
A basic cell structure of p-n-n (a set of one p-channel and two n-channel resistors) is proposed for the cell of a variable-track masterslice (VTM) in order to increase the utilization of logic gates. The masterslice has 180 K p-channel and 360 K n-channel transistors for logic circuitry; it uses 1-3 /spl mu/m double-metal CMOS technology, and has 60 K equivalent (two-input NAND) gates without channel. A small track increment of six or nine allows fine adjustment of the track count in each routing channel. The gate density in p-n-n VTM has been increased by 10 to 30% over a conventional p-n VTM, where p-n represents CMOS pair transistors. 相似文献
7.
《Solid-State Circuits, IEEE Journal of》1978,13(5):536-541
A DSA MOS (diffusion self-aligned MOS) masterslice circuit with up to 920 gates and a delay of 3 ns per gate has been developed for random logic computer circuits, utilizing the performance and economical advantages of the LSI masterslice approach. To attain high packing density and high speed with conventional design rules, the DSA MOSFET technology has been used for the basic device. The chip comprises 50 by 16 gate cells and 116 input/output buffers. This LSI chip is two to three times better than bipolar S-TTL in packing density and is comparable in propagation delay time. As an example of an LSI device obtained through customized metallization, an 8 bit ALU is described which has an average delay time of 3 ns and a power dissipation of 3 W. 相似文献
8.
《Solid-State Circuits, IEEE Journal of》1979,14(4):764-766
A new LSI with high-speed capability and high-packing density for computer use has been successfully achieved within a short turnaround time by a new DSA MOS masterslice. Two-level metallization has been accomplished by the use of full plasma processes. The average gate delay time of the new masterslice was improved to 2 ns compared with 3 ns in the case of single-level metallization. 相似文献
9.
Depey M.P. Dell'ova F. Chateau J.-M. Mallardeau C. Fryers A.J. Woerner K. 《Solid-State Circuits, IEEE Journal of》1989,24(3):552-557
A quad 512-b static shift register consuming 1.8 mW/stage designed to demonstrate the capabilities of an advanced bipolar silicon technology is discussed. The process uses 1-μm lithography, trench isolation, polyemitter transistors, polysilicon resistors, and polycide layer for local interconnections. This VLSI circuit (over 35 K transistors, 86-mm2 chip) has been implemented on a sea-of-cells structure. An appropriate scheme has been used for the clock distribution. The experimental results show operation at a clock frequency up to 950 MHz 相似文献
10.
《Solid-State Circuits, IEEE Journal of》1987,22(1):41-46
A very large-scale integrated (VLSI) bipolar masterslice has been demonstrated. This masterslice has a loaded three-input ECL gate delay of 290 ps and an unloaded gate delay of 164 ps at a power dissipation of 1.5 mW/gate. It is fabricated by using 1.5-/spl mu/m rule super self-aligned process technology (SST), 2-/spl mu/m-wide deep U-groove isolation, and a fine 5-/spl mu/m pitch three-level metallization process. The authors describe its process features, cell design, chip structure, experimental results, and applications. 相似文献
11.
A variable step size LMS algorithm 总被引:14,自引:0,他引:14
A least-mean-square (LMS) adaptive filter with a variable step size is introduced. The step size increases or decreases as the mean-square error increases or decreases, allowing the adaptive filter to track changes in the system as well as produce a small steady state error. The convergence and steady-state behavior of the algorithm are analyzed. The results reduce to well-known results when specialized to the constant-step-size case. Simulation results are presented to support the analysis and to compare the performance of the algorithm with the usual LMS algorithm and another variable-step-size algorithm. They show that its performance compares favorably with these existing algorithms 相似文献
12.
《Solid-State Circuits, IEEE Journal of》1979,14(5):829-832
Describes the design and implementation of a bipolar subnanosecond gate arrays with a complexity up to 700 gates. There are three different basic arrays with either 24 or 36 cells or 24 cells plus a 128 bit RAM. Each cell has the logic power of a small MSI. The masterslice is ECL compatible. 相似文献
13.
《Solid-State Circuits, IEEE Journal of》1985,20(5):1032-1035
A bipolar masterslice chip with an integration level of 9000 gates is described. Internal gate delays down to 150 ps are achieved by utilizing an advanced processiong technology, OXIS III, and a CML circuit technique with three levels of series gating. The 128 mm/SUP 2/ chip has a typical power dissipation of 20 W. I/O levels at 256 logic pins are standard ECL 100 or 10K. 相似文献
14.
《Solid-State Circuits, IEEE Journal of》1985,20(5):1005-1011
A 24K-gate CMOS gate array has been developed using triple-level wiring and a hierarchical layout method. A typical delay time is 1.6 ns with a fanout of 3 and a 3-mm metal interconnect length. The master chip was designed to be freely divided into blocks. A previously developed digital signal processor has been realized on the array. The design time was reduced to 25% of the normal design cycle although the chip size is 3.3 times larger than was realized by a handcrafted design. 相似文献
15.
《Solid-State Circuits, IEEE Journal of》1984,19(5):657-663
An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained. Typical delay times of inverter, two-input NAND, and two-input NOR gates are 0.67, 0.87, and 0.99 ns, respectively, under a typical loading condition (three fan outs and 2 mm first metal). It is shown that ECL speed with CMOS power can be achieved in a system by using the CMOS/SOS gate array. Advantages of the SOS device on speed performance are also discussed. 相似文献
16.
17.
Sato K. Kobayashi M. Hida H. Miyazawa H. Shirai Y. Fujita K. Nakao T. Ishihara M. 《Solid-State Circuits, IEEE Journal of》1992,27(11):1608-1613
A system integrated LSI chip (SLSI) that contains eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array, for a graphics application system is described. To implement the SLSI on a silicon chip, three key techniques have been developed: (1) system redundancy for defect relief; (2) chip configuration and fabrication with blade masking to achieve a hybrid 38.16×50.4-mm2 chip; and (3) large-capability and high-reliability 324-pin 54×86-mm2 plastic pin grid array package. Using a system redundancy technique, a 60% yield for the SLSI is achieved with a 40% yield for the DRAM itself. That is twice the 30% yield of the conventional repair scheme. Access times are 65 ns for the DRAM and 14 ns for the SRAM with a 3.9-W chip power dissipation 相似文献
18.
A variable-gain amplifier (VGA) with a gain range of 50 dB has been implemented in a standard 3 μm CMOS process using parasitic lateral and vertical bipolar transistors to form the core of the circuit. The bipolar transistors had been characterized extensively. The VGA has a bandwidth larger than 3 MHz over the whole gain range and operates on a single 5 V power supply. The active area is about 0.8×0.9 mm2 相似文献
19.
《Solid-State Circuits, IEEE Journal of》1980,15(5):802-808
Describes a bipolar 18 bit register arithmetic logic unit (RALU) with 1300-gate complexity using an advanced bipolar process named Advanced PSA (APSA). The high-performance of the Advanced PSA transistor has made it possible to achieve a 400 ps delay time with 2.5 mW for a basic low level CML (LCML) circuit. The read-modify-write cycle time is 7 ns in an 18-bit ALU operation. Furthermore, with four RALU chips, a 72-bit ALU can be set up to operate at 100 MHz owing to the improved logic implementation. A 132 pin gang-lead bonding is employed for this LSI. 相似文献
20.
《Solid-State Circuits, IEEE Journal of》1972,7(4):297-298
A novel memory cell is described that is used in several IBM processors. It is fast, insensitive to disturbance by reading and half-selects, and delivers a large sense signal. 相似文献