Impact of defects on the high-κ/MG stack: The electrical characterization challenge

The integration of high-κ dielectrics in MOSFET devices is beset by many problems. In this paper a review on the impact of defects in high-κ materials on the MOSFET electrical characteristics is presented. Beside the quality of the bulk of the dielectric itself, the interfaces between the high-κ and the interfacial oxide layer and the gate electrode are of crucial importance. When poly-Si is used as gate electrode, the defects at the poly-Si/high-κ interface control the band alignment as well as the gate depletion. The quality and thickness of the interfacial SiO₂ controls both the carrier mobility in the channel as well as the kinetics of charging and discharging of pre-existing high-κ defects. The quality of the interfacial layer has also important consequences for reliability specifications like negative bias instability and dielectric breakdown.     

Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey

In this paper, we report on several different approaches that were implemented on both capacitor and scaled planar MOS transistor devices in order to prevent or undo the commonly observed V_T/V_fb-shift and –instability for Hf-based high-κ gate stacks in conjunction with a poly-Si electrode. While the latter issue can eventually be mitigated, the V_T-shift problem jeopardizes initial high-κ integration with poly-Si for the 65 nm and also for the 45 nm node. The different attempts to circumvent this problem include (1) bulk modifications of the high-κ stack/process, (2) the use of various thin capping layers at the poly/high-κ interface and (3) chemical and process modifications of the gate electrode deposition. We have observed that, although considerable improvements have been made in terms of e.g. yield, performance and instability, none of these techniques succeeded in obtaining V_T-values in line with the ITRS device specifications, i.e. avoiding Fermi Level Pinning to occur for poly-Si/Hf(Si)O(N) stacks.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Initial and PBTI-induced traps and charges in Hf-based oxides/TiN stacks

Positive voltage instabilities are studied for Nmos transistors with hafnium-based high-κ gate stacks. Using an optimized dedicated fast measurement setup, dynamic transient measurements of drain current are performed over more than ten decades of time. The two main phenomena involved, a reversible one known as hysteresis and a nonreversible one known as PBTI are clearly experimentally separated and studied in detail. A physical model is presented, explaining the dynamic behaviour and leading to precise traps physical characteristics and profiles inside the HfO₂ layer. PBTI defects in HfO₂ are shown to be of a different nature than hysteresis traps. A turn-around effect is evidenced for PBTI above which physical mechanisms seem to change; it has important implications on lifetime determination methodology. Finally, HfSiON experiments are presented for both hysteresis and PBTI and they show that this material is much less critical than HfO₂.     

Charge trapping characterization of MOCVD HfO2/p-Si interfaces at cryogenic temperatures

The paper focuses on the study of charge trapping processes in high-k MOS structures at cryogenic temperatures. It was shown, that there is extremely strong trapping in shallow electron and hole traps, localized in the high-k dielectrics. Concentration of shallow electron traps is as much as 10¹³ cm⁻², while abnormal small capture cross-sections (4.5–8 × 10⁻²⁴ cm² for different samples, accordingly) suggests localization of shallow emitting electron traps in transition layer “high-k dielectric/Si”, more, than at the interface. Shallow hole traps with concentration near 10¹² cm⁻² are separated from silicon valence band with energy barrier in the range 10–39 meV for different samples.     

Extracting the relative dielectric constant for “high-κ layers” from CV measurements – Errors and error propagation

The paper pursues an investigation of the errors associated with the extraction of the dielectric constant (i.e., κ value) from capacitance–voltage measurements on metal oxide semiconductor capacitors. The existence of a transition layer between the high-κ dielectric and the silicon substrate is a factor that affects – in general – the assessment of the electrical data, as well as the extraction of κ. A methodology which accounts for this transition layer and the errors related to other parameters involved in the κ value extraction is presented; moreover, we apply this methodology to experimental CV results on HfO₂/SiO_x/Si structures produced in different conditions.     

Monte carlo study of mobility in Si devices with -based oxides

HfO₂-based high-κ dielectrics are among the most likely candidates to replace SiO₂ and the currently favoured oxinitride in the next generation of MOSFETs. High-κ materials allow the use of a thicker gate dielectric, maintaining the gate capacitance with reduced gate leakage. However, they lead to a fundamental mobility degradation due to the coupling of carriers to surface soft (low-energy) optical phonons. Comparing the vertical field dependence of the mobility for HfO₂ and SiO₂, the severe degradation in mobility in the presence of high-κ becomes evident. The introduction of a SiO₂ interfacial layer between the channel and the HfO₂ mitigates this degradation, by increasing the effective distance between the carriers and the SO phonons, thus decreasing the interaction strength, this does though lead to an increase in the equivalent oxide thickness (EOT) of the gate dielectric. The material of choice for the first commercial introduction of high-κ gate stacks is Hafnium Silicate (Si_xHf_1-xO₂). This alloy stands up better to the processing challenges and as a result suffers less from dielectric fluctuations. We show that as the fraction of Hf increases within the alloy, the inversion layer mobility is shown to decrease due to the corresponding decrease in the energy of the surface optical phonons and increase in the dielectric constant of the oxide.     

Full-band tunneling in high-κ dielectric MOS structures

High-κ oxides such as ZrO₂ and HfO₂ have attracted great interest, due to their physical properties, suitable to replacement of SiO₂ as gate dielectric materials. In this work, we investigate the tunneling properties of ZrO₂ and HfO₂ high-κ oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab initio band dispersions. Transmission coefficients and tunneling current have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with equivalent oxide thickness.     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

Interfaces between - and silicon

As the epitaxy of crystalline LaAlO₃ has not been realized yet, we investigated the use of a γ-Al₂O₃ buffer layer between the high-κ and the substrate. We firstly studied the structural matching of γ-Al₂O₃(0 0 1) with a Si(0 0 1)-p(2×1) reconstructed surface. According to experimental data and computations in the density functional theory framework, we found stable interfaces between γ-Al₂O₃ and Si which encounters surface reconstruction changes. These interfaces satisfy the criterion of an insulating buffer layer.     

Radiation damage of Ge-on-Si devices

The radiation damage induced by 2-MeV electrons and 70-MeV protons in p⁺n diodes and p-channel MOS transistors, fabricated in epitaxial Ge-on-Si substrates is reported for the first time. For irradiation above 5×10¹⁵ e/cm², it is noted that both the reverse and forward current increase, and that the forward current is lower after irradiation for a forward voltage larger than about 0.5 V. The reason for this might be an increased resistivity of the Ge-on-Si substrate. For p-MOSFETs, for a 1×10¹⁶ e/cm² dose, a slight negative shift of the threshold voltage and a decrease of the drain current for input and output characteristics have been observed. In addition, g_m decreases after irradiation. The degradation of the transistor performance is thought to be due to irradiation-induced positive charges in the high-κ gate dielectric. The induced lattice defects are also mainly responsible for the leakage current increase of the irradiated diodes.     

A threshold-voltage model of SiGe-channel pMOSFET without Si cap layer

An analytical model on the threshold voltage of SiGe-channel pMOSFET with high-κ gate dielectric is developed by solving the Poisson’s equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data, and good agreements are obtained. This model can be used for the design of SiGe-channel pMOSFET, thus determining its optimal parameters.     

Templates for LaAlO3 epitaxy on silicon

As direct epitaxy of crystalline LaAlO₃ on silicon has not been realized yet, we investigated the use of a template between the high-κ and the substrate. We performed calculations in the Density Functional Theory framework for two possible templates: a Sr_0.5O monolayer and a 0.5 nm thick γ-Al₂O₃(0 0 1) layer. We firstly found that in the Sr_0.5O monolayer case, care must be taken for the LaAlO₃ starting sequence in order to expect good band offsets with silicon. In the γ-Al₂O₃ case, a more complex engineering of the interface is needed. Nonetheless, we found stable interfaces and a surface reconstruction in agreement with experimental observations. Moreover, these interfaces exhibit insulating properties and insight calculations for a Si–γ-Al₂O₃–LaAlO₃ superstructure lead us to a 1.9 eV conduction band offset.     

Study of passivation defects by electroluminescence in AlGaN/GaN HEMTS on SiC

This paper presents a new method of passivation control by electroluminescence (EL) in 0.15 μm AlGaN/GaN HEMT. The electroluminescence signature in one finger HEMTs (W = 1 × 100 μm), and eight fingers ones (W = 8 × 125 μm), is modified by defects located at the passivation/semiconductor interface and is characterized by a light emission along the drain contact. This abnormal emission reveals some modification of the electric field distribution in the gate-drain space probably induced by traps located at the passivation/semiconductor interface. These traps contribute to the creation of a virtual gate in the gate-drain space.     

Process integration and nanometer-scale electrical characterization of crystalline high-k gate dielectrics

Crystalline praseodymium oxide (Pr₂O₃) high-k gate dielectric has been successfully integrated into a polysilicon gate CMOS technology. Fully functional MOSFETs with an equivalent oxide thickness (EOT) of 1.8 nm and gate leakages below 10⁻⁶ A/cm² have been fabricated. However, at this early stage of development the transistors show Vt-instabilities and unusual high gate leakage for L > 10 μm. As a first attempt to explain the observed macroscopic device characteristics, topographical and electrical measurements at the nanometer scale have been performed directly on the Pr₂O₃ surface by Conductive Atomic Force Microscopy (C-AFM). This technique allows to discriminate between structural defect sites and charge trapping centers.     

Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

A note on trap recombination in high voltage device structures

The carrier lifetime is a very important parameter influencing all important characteristics of bipolar devices both discrete and integrated structures and carrier lifetime tailoring is an important part of power semiconductor device technology. In presented paper, recombination through traps (centres with a deep energy level between edge of bandgap and Fermi level) is discussed in more details. It has been shown that some traps can considerably influence recombination rate in silicon and that at some traps a considerable temperature dependence of the centre cross-sections may be found. This is demonstrated in the case of iridium traps with a deep energy level 0.28 eV below the conduction band which capture cross-section temperature dependence has been found σ_p+σ_n∝T^−6.5. Further, the problem on low injection carrier lifetime in low-doped layers of high voltage semiconductor devices is also discussed.     

Bond strain and defects at interfaces in high-k gate stacks

The performance and reliability of aggressively-scaled field effect transistors are determined in large part by electronically-active defects and defect precursors at the Si–SiO₂, and internal SiO₂–high-k dielectric interfaces. A crucial aspect of reducing interfacial defects and defect precursors is associated with bond strain-driven bonding interfacial self-organizations that take place during high temperature annealing in inert ambients. The interfacial self-organizations, and intrinsic interface defects are addressed through an extension of bond constraint theory from bulk glasses to interfaces between non-crystalline SiO₂, and (i) crystalline Si, and (ii) non-crystalline and crystalline alternative gate dielectric materials.     

Structural and vibrational properties of high-dielectric oxides, HfO2 and TiO2: A comparative study

Within the framework of density functional theory, we have computed structural and vibrational properties of high-κ dielectric oxides, HfO₂ and TiO₂. We have considered different polytypes of these oxides and computed the corresponding static dielectric constants in order to investigate what are the more promising materials suitable for technological application. We found the flourite phase of hafnium dioxide, that is a promising candidate as gate oxide in ultra-scaled complementary metal-oxide-semiconductor (CMOS) technology, is structurally unstable due to the presence of soft phonon modes that have wave-vectors in the region of the Brillouin zone containing the K- and X-points. According to our results, the fluorite TiO₂ is structurally unstable as well but, contrary to HfO₂, the soft phonon modes have wave-vectors in the whole Brilouin zone. Calculations of the thermodynamical properties of the baddeleyite HfO₂, the stable phase at ambient condition, complete the work.     

Growth of lanthanum oxide films for application as a gate dielectric in CMOS technology

We have investigated properties of insulating lanthanum oxide (La₂O₃) films in connection with the replacement of silicon oxide (SiO₂) gate dielectrics in new generation of CMOS devices. The La₂O₃ layers were grown using metal organic chemical vapour deposition (MOCVD) at 500 °C. X-ray diffraction analysis revealed polycrystalline character of the films grown above 500 °C. The X-ray photoemission spectroscopy detected lanthanum carbonate as a principal impurity in the films and lanthanum silicate at the interface with silicon. Density of oxide charge, interface trap density, leakage currents and dielectric constant ( κ) were extracted from the C-V and I-V measurements. Electrical properties, in particular dielectric constant of the MOCVD grown La₂O₃ are discussed with regard to the film preparation conditions. The as grown film had κ11. Electrical measurements indicate possible presence of oxygen vacancies in oxide layer. The O₂-annealed La₂O₃ film had κ17.