A CMOS UWB Pulse Generator for 6–10 GHz Applications

A CMOS ultra wideband (UWB) pulse generator with low energy dissipation and high peak amplitude is presented for 6–10 GHz applications. The pulse generator complies with the FCC spectral mask for indoor UWB systems. It consists of a glitch generator, a pulsed oscillator, and a pulse shaping filter. The pulsed oscillator is switched on by the glitch signal only for a short duration, so as to make a UWB pulse. For sub-nanosecond pulse generation, a pulsed oscillator with fast transient response is proposed. A pulse shaping filter makes the oscillator output fall into the FCC spectral mask. The pulse generator is fabricated using a 0.18 $mu$ m CMOS process. The core chip has a size of 0.11 mm $^{2}$. It shows pulse duration of about 500 ps with ${-}10$ dB bandwidth of 4.5 GHz from 5.9 to 10.4 GHz. The energy consumption is 27.6 pJ per pulse with a peak-to-peak amplitude of 673 mV on a 50 $Omega$ output load. The generated pulses are very coherent with 1.8 ps RMS jitter.      

A CMOS Ultra Low-Power and Highly Efficient UWB-IR Transmitter for WPAN Applications

This brief presents an on–off $LC$ oscillator-based ultrawideband impulse radio (UWB-IR) transmitter for long-range application. A thorough theoretical analysis of the pulse generation is provided. Implemented in a 0.18-$muhbox{m}$ CMOS, the transmitter works in the UWB lower band of 3–5 GHz and consumes an ultralow average power of 236 $muhbox{W}$ at 1.8-V power supply. UWB pulses with a bandwidth of 2 GHz and 10-dB sidelobe suppression are generated. The transmitter can deliver a large differential output swing of 4.9 V under 100-$Omega$ load with the highest power efficiency of 25.4% to date. It is targeted for wireless sensor network (WSNs) and wireless personal area network (WPAN) applications.      

An Energy-Efficient All-Digital UWB Transmitter Employing Dual Capacitively-Coupled Pulse-Shaping Drivers

This paper presents an all-digital, non-coherent, pulsed-UWB transmitter. By exploiting relaxed center frequency tolerances in non-coherent wideband communication, the transmitter synthesizes UWB pulses from an energy-efficient, single-ended digital ring oscillator. Dual capacitively coupled digital power amplifiers (PAs) are used in tandem to attenuate low frequency content typically associated with single-ended digital circuits driving single-ended antennas. Furthermore, four level digital pulse shaping is employed to attenuate RF sidelobes, resulting in FCC compliant operation in the 3.5, 4.0, and 4.5 GHz IEEE 802.15.4a bands without the use of any off-chip filters or large passive components. The transmitter is fabricated in a 90 nm CMOS process and occupies a core area of 0.07 mm$^2$ . The entirely digital architecture consumes zero static bias current, resulting in an energy efficiency of 17.5 pJ/pulse at data rates up to 15.6 Mb/s.      

High-Voltage High-Efficiency Ultrawideband Pulse Synthesizer

A novel ultrawideband pulse synthesizer based on distributed amplifier topology is presented. The basic concept is to combine different delayed Gaussian pulses with both positive and negative polarities to form an UWB pulse. Compared to other ultrawideband pulse-formation methods, this method can have both high-efficiency and high-voltage output. The prototype circuit based on 0.25-$mu$m pHEMT transistors is fabricated, and the fabricated pulse synthesizer consumes only 1-mA current under 5-V power supply with high energy efficiency of 10.1% at 10-MHz pulse repetition frequency (PRF). Measurement results show that with 1.5 -V amplitude and 240-ps Gaussian input pulse, the output pulse of the designed UWB pulse synthesizer is centered at 4 GHz with 4.5-V peak to peak amplitude (into 50-ohms load) and 1.0-ns duration at 50% of the peak pulse envelope.      

Photonic Monocycle Pulse Frequency Up-Conversion for Ultrawideband-Over-Fiber Applications

We demonstrate a photonic monocycle pulse frequency up-conversion scheme for ultrawideband (UWB)-over-fiber applications using nonlinear polarization rotation arising in a semiconductor optical amplifier. For the first time, we have successfully realized the photonic up-conversion of UWB monocycle pulses with an optical local oscillator signal at 24 GHz in the whole -band. The up-converted UWB monocycle pulse at 24 GHz exhibits a power spectrum density fitting the UWB emission mask. After electrical down-conversion, the UWB monocycle pulse has shown low distortion induced by the optical mixing process.     

Low-power ultra-wideband wavelets generator with fast start-up circuit

A low-power fully integrated ultra-wideband (UWB) wavelet generator is presented. This UWB generator is intended for low-power and low-complexity UWB radio technology using the noncoherent energy collection approach. The wavelet generator is based on a cross-coupled inductance-capacitance (LC) oscillator. It can be directly driven by two digital signals, which can modulate the length, position, and phase of the output wavelet. An additional digital circuit improves the startup time of the oscillator so that the oscillator and output buffers can be switched off between each wavelet generation. The entire chip-including output buffers-uses a 0.18-/spl mu/m CMOS technology. When operating at 10 megapulses per second (Mp/s) with a 1.2-GHz bandwidth wavelet, the generator provides a typical average output power of -20 dBm and consumes only 1.8 mW. The differential output signal is a multicycle waveform centered at 4.5 GHz.     

Experimental Demonstration of All-Optical 781.25-Mb/s Binary Phase-Coded UWB Signal Generation and Transmission

In this letter, an all-optical incoherent scheme for generation of binary phase-coded ultra-wideband (UWB) impulse radio signals is proposed. The generated UWB pulses utilize relaxation oscillations of an optically injected distributed feedback laser that are binary phase encoded (0 and $pi$) and meet the requirements of Federal Communications Commission regulations. We experimentally demonstrated a 781.25-Mb/s UWB-over-fiber transmission system. A digital-signal-processing-based receiver is employed to calculate the bit-error rate. Our proposed system has potential application in future high-speed UWB impulse radio over optical fiber access networks.      

Super-Regenerative Architecture for UWB Pulse Detection: From Theory to RF Front-End Design

This paper presents an optimization of the super-regenerative architecture for impulse-based ultrawideband (UWB) technology dedicated to low-data-rate applications. The receiver belongs to the noncoherent category but enables nanosecond resolution for efficient location and tracking applications. Relying on analytical developments, this paper demonstrates how the super-regenerative architecture can suit the UWB context. Such a receiver enables a high RF gain and pulse-matched filter effect with tied power consumption to be achieved, thanks to the suitable control of the inherent unstable behavior. Bit-error-rate simulations based on this architecture are conducted and show a required $Eb/n_{0}$ of 12.5 dB at $10^{-4}$ in the additive white Gaussian noise channel. RF impairment impacts are evaluated and demonstrate good tolerance to the oscillator central frequency accordance and synchronization issue. Specifications of the circuit and controlled signal are drawn up. To validate this concept, the design of the RF front is performed in the CMOS 0.13-${rm mu}hbox{m}$ technology. It includes an LNA, a transconductance stage, and the detector formed by a fully integrated $LC$ -NMOS oscillator. This circuit consumes less than 10 mA for an RF gain above 50 dB and a 1-GHz-wide input signal bandwidth. The measured sensitivity is $-99 hbox{dBm}$ at $10^{-3}$ for a 1-Mb/s pulse rate for binary modulation.      

A 0.25-mm CMOS T/R switch for UWB wireless communications

A T/R switch, fabricated using standard 0.25-/spl mu/m CMOS process, for ultra wide-band (UWB) wireless communications is presented. The switch is designed based on the concept of synthetic transmission line, utilizing both CPW and CMOS transistors, to achieve not only an extremely wide bandwidth but also a linear phase response necessary for time-domain UWB applications. On-chip measurement is completed in both frequency and time domains. Frequency-domain measured results show insertion loss of 2.2-4.2 dB, isolation from 34-48 dB, and highly linear transmission phase from 0.45 MHz to 13 GHz. These results are quite consistent with the calculations. Particularly, the time-domain pulse measurement shows that the output pulses resemble closely the input pulses with very little reflection, demonstrating the switch's suitability for true time-domain UWB applications. The developed switch is ready to be integrated with other CMOS RFICs to form on-chip transceivers for various UWB applications.     

Multi-Modulus LC Injection-Locked Frequency Dividers Using Single-Ended Injection

A new wide-locking range multi-modulus LC-tank injection locked frequency divider (ILFD) is proposed and was fabricated in a 0.18 $mu {rm m}$ CMOS process. The ILFD circuit is realized with a complementary MOS LC-tank oscillator and an injection composite composed of an inductor in series with an injection MOS. The two output terminals of the injection composite are connected to the resonator outputs. The ILFD can be used as a first-harmonic oscillator (ILO), even-modulo or odd-modulo oscillator depending upon the incident frequency of injection signal. At the supply voltage of 1.5 V, the free-running frequency is from 4.85 to 5.13 GHz, the current and power consumption of the divider without buffers are 2.78 and 4.17 mW, respectively. At the incident power of 0 dBm, the locking range in the divide-by-1(2, 3, 4) mode is from the incident frequency 3.72 to 8.69 (8.42 to 10.95, 13.66 to 16.03, 19.13 to 20.5) GHz.      

Energy-Efficient Low-Complexity CMOS Pulse Generator for Multiband UWB Impulse Radio

This paper presents an energy-efficient low-complexity pulse-generator design technique for multiband impulse-radio ultrawide-band (IR-UWB) system in 0.18-${mu}hbox{m}$ CMOS technology. The short pulses are generated based on the on/off switching operation of an oscillator with subband switching functionality, which is mandatory for multiband IR-UWB systems. The relation between the oscillator switching operation and the resulting output pulse envelope, which determines pulse spectral characteristics, is analyzed, and the design guidelines for topology and component values are presented. Measurements show the output pulses with the duration of 3.5 ns, which corresponds to 520-MHz bandwidth. The output pulse spectrum centered at 3.8 GHz fully complies with the Federal Communication Commission spectral mask with more than 25 dB of sidelobe suppression without the need for additional filtering. Thus, the low-complexity pulse generator can maintain its simplicity for low cost with core chip size of 0.3 $hbox{mm}^{2}$. The pulse generator shows an excellent energy efficiency with average energy dissipation of 16.8 pJ per pulse from 1.5-V supply. The proposed pulse generator is best suited for energy-detection IR-UWB systems.      

Low Phase-Noise Planar Oscillators Employing Elliptic-Response Bandpass Filters

In this paper, a low phase-noise planar oscillator employing an elliptic bandpass filter as a frequency stabilization element within its feedback loop is presented. The oscillator phase noise is significantly reduced by taking advantage of the group-delay peaks formed at the passband edges of the elliptic filter. A filter optimization technique for low phase-noise oscillator designs is introduced and applied to a four-pole bandpass elliptic filter. An $X$-band oscillator using the optimized filter in the feedback loop is designed and tested. At the oscillation frequency of 8.05 GHz, the measured phase noise is $-$143.5 dBc/Hz at 1-MHz offset frequency. The oscillator exhibits an output power of 3.5 dBm with an dc–RF efficiency of 10%. To the authors' best knowledge, this is the lowest phase noise performance for an $X$-band planar microwave oscillator.      

A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier

A single phase-locked loop (PLL) frequency synthesizer for a Mode-1 multiband orthogonal frequency-division multiplexing (MB-OFDM) ultrawideband (UWB) system is realized in 0.13-$mu hbox{m}$ CMOS. A current-reused multiply-by-1.5 circuit and a multiphase coupled ring oscillator are adopted to reduce the power consumption. For a 4.488-GHz signal, the measured image sideband is $-$40 dBc. The measured switching time from 3.342 to 4.488 GHz is 1.5 ns. The area is $0.85 times 0.9 hbox{mm}^{2}$ and the power is 31.2 mW for a 1.2-V supply voltage.      

Minimizing Phase Noise Variation in CMOS Ring Oscillators

The variation of phase noise across the frequency of operation of a CMOS ring oscillator is described analytically. The delay element of the ring oscillator considered comprises of a source-coupled differential pair with an active load element. In this circuit topology where the frequency of oscillation is varied by changing the resistance of the load, theory derived in this work predicts that phase noise will remain constant if constant output swing is maintained. Such an oscillator is designed in a 0.5 m CMOS process and the simulation results verify the theoretical analysis. Consequently, an oscillator design methodology is provided that dramatically reduces the phase noise optimization problem to just one frequency within the oscillator's output frequency range.     

A Low-Noise Wide-BW 3.6-GHz Digital $DeltaSigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital converter (TDC) with 6-ps raw resolution and first-order shaping of its quantization noise along with digital quantization noise cancellation to achieve integrated phase noise of less than 300 fs (1 kHz to 40 MHz). The synthesizer includes two 10-bit 50-MHz passive digital-to-analog converters for digital control of the oscillator and an asynchronous frequency divider that avoids divide-value delay variation at its output. Implemented in a 0.13-$mu$m CMOS process, the prototype occupies 0.95-mm$^{2}$ active area and dissipates 39 mW for the core parts with another 8 mW for the oscillator output buffer. Measured phase noise at 3.67 GHz carrier frequency is $-$108 and $-$150 dBc/Hz at 400 kHz and 20 MHz offset, respectively.      

Ring Oscillator Technique for MOSFET $CV$ Characterization

A technique for extracting small signal MOSFET gate capacitance as a function of bias voltage from measurements of circuit delay and power is described. This approach makes use of a ring oscillator with stages in which an independent bias voltage is applied to the gates of MOSFETs driven by an inverter. The square wave signal circulating around the ring oscillator, at a reduced power supply voltage, serves as a small signal excitation for the $CV$ characterization. Gate charging times of order 40 ps enable capacitance measurement in the presence of the high parallel conductance of thin gate dielectrics. MOSFET parameters such as inversion and depletion capacitances and electrical channel length can be self-consistently compared with circuit power/performance, all derived as averages over hundreds of MOSFETs from the same test structure. This minimizes dependencies on layout, spatial and statistical variations, as well as other ambiguities that can exist when a variety of test structures is used to evaluate different MOSFET and circuit performance parameters. At $≪$1 MHz, the frequency divided output is compatible with standard in-line test. Data from experimental partially depleted silicon-on-insulator hardware at the 65-nm CMOS technology node are presented.      

一种有载频超宽带脉冲源设计

针对无载频脉冲低频分量大、辐射效率低、频带可调性差等问题,设计了一种以阶跃恢复二极管、D触发器及超宽带调制器为主的宽频带、高重复频率、低振铃水平的有载频超宽带脉冲源。该脉冲源电路由驱动电路、高速开关电路、整形电路、超宽带调制器及振荡器电路组成。实测结果表明,脉冲源输出脉冲信号重复频率可达125 MHz,脉冲宽度600 ps（底宽）,脉冲振铃水平低于10%,峰-峰值为5.4 V,-10 dB带宽可达4.2 GHz。脉冲信号中心频率与载频相同,可在6.6~8.5 GHz之间灵活设置。利用所设计的脉冲源进行时域测量,其结果与矢量网络分析仪频域测量结果相比幅频特性均方根误差小于0.21 dB。该脉冲源可应用于超宽带时域测量、短距离高速无线通信、高精度室内定位等应用。     

Local Oscillator Generation Circuit for Direct Conversion Transmitter

In this paper a fully monolithic on-chip local oscillator signal generation circuit is presented for eliminating the negative effect of coupling between bond-wires, package pins and output and input lines of the power amplifier output to the local oscillator input for direct conversion transmitters. The proposed circuit generates the local oscillator signal at frequencies 1710–1785 GHz which is harmonically uncorrelated from two input signals at 464 MHz and 1792–2088 MHz. The required building blocks are a frequency divider, a mixer and an active band-pass filter. Fully monolithic high frequency band-pass filters have not been available until recently, and the designed circuit is in fact one of the first applications reported for MMIC active filters in cellular phones. The circuit is designed with a 0.5 m GaAs MESFET technology and the performance is verified with on-chip measurements.     

Scaling $LC$ Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

We present an oscillator design method that reduces the area of $LC$ oscillators in extremely scaled CMOS technologies by taking advantage of the high $f_{T}$ of the transistors. The oscillator is scaled to operate at a higher frequency and is followed by a fixed-ratio divider. It maintains the same power consumption and performance for a given wanted output frequency while occupying a much smaller area. In principle, by scaling up the oscillation frequency $N$ times, a factor of $1/N^{2}$ can be obtained in inductor area reduction. Simulated results show that with uniformly scaled inductors, the figure of merit (FoM) of the scaled oscillators at 1, 2, 4, and 8 GHz can be within a 1-dB difference, whereas the figure of merit normalized for area (FoMA) improves with the oscillation frequency.      

A Biphase Modulator Circuit for Impulse Radio-UWB Applications

This letter presents a circuit to provide binary phase shift keying to ultra-wideband (UWB) impulse transmitters. The circuit is based on a Gilbert-cell multiplier and uses active on-chip balun and unbalanced-to-balanced converters for single-ended to single-ended operation. Detailed measurements of the circuit show a gain ripple of $pm 1~{rm dB}$ at an overall gain of $-2~{rm dB}$, an input reflection below $-12~{rm dB}$, an output reflection below $-18~{rm dB}$, a group delay variation below 6 ps and a $-1~{rm dB}$ input compression point of more than 1 dBm in both switching states over the full 3.1–10.6 GHz UWB frequency range. A time domain measurement verifies the switching operation using an FCC-compliant impulse generator. The circuit is fabricated in a $0.8~mu {rm m}$ Si/SiGe HBT technology, consumes 31.4 mA at a 3.2 V supply and has a size of $510 times 490~mu{rm m}^{2}$ , including pads. It can be used in UWB systems using pulse correlation reception or spectral spreading.